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GET /api/patches/54471/?format=api
{ "id": 54471, "url": "http://patches.dpdk.org/api/patches/54471/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/74886a52875fbfc99e45c9ae9fd6b549cfcb33a6.1559818024.git.xuanziyang2@huawei.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<74886a52875fbfc99e45c9ae9fd6b549cfcb33a6.1559818024.git.xuanziyang2@huawei.com>", "list_archive_url": "https://inbox.dpdk.org/dev/74886a52875fbfc99e45c9ae9fd6b549cfcb33a6.1559818024.git.xuanziyang2@huawei.com", "date": "2019-06-06T11:06:28", "name": "[v4,08/11] net/hinic: add hinic PMD build and doc files", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": true, "hash": "8db63845bca645bbc976a39f9dca317c67b31df6", "submitter": { "id": 1321, "url": "http://patches.dpdk.org/api/people/1321/?format=api", "name": "Ziyang Xuan", "email": "xuanziyang2@huawei.com" }, "delegate": { "id": 319, "url": "http://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/74886a52875fbfc99e45c9ae9fd6b549cfcb33a6.1559818024.git.xuanziyang2@huawei.com/mbox/", "series": [ { "id": 4924, "url": "http://patches.dpdk.org/api/series/4924/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=4924", "date": "2019-06-06T11:04:33", "name": "A new net PMD - hinic", "version": 4, "mbox": "http://patches.dpdk.org/series/4924/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/54471/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/54471/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id EE8AC1B9AC;\n\tThu, 6 Jun 2019 12:55:07 +0200 (CEST)", "from huawei.com (szxga04-in.huawei.com [45.249.212.190])\n\tby dpdk.org (Postfix) with ESMTP id 603931B999\n\tfor <dev@dpdk.org>; Thu, 6 Jun 2019 12:55:06 +0200 (CEST)", "from DGGEMS404-HUB.china.huawei.com (unknown [172.30.72.59])\n\tby Forcepoint Email with ESMTP id 908353990C8DD87219AB;\n\tThu, 6 Jun 2019 18:55:04 +0800 (CST)", "from tester_149.localdomain (10.175.119.39) by\n\tDGGEMS404-HUB.china.huawei.com (10.3.19.204) with Microsoft SMTP\n\tServer id 14.3.439.0; Thu, 6 Jun 2019 18:54:57 +0800" ], "From": "Ziyang Xuan <xuanziyang2@huawei.com>", "To": "<dev@dpdk.org>", "CC": "<ferruh.yigit@intel.com>, <cloud.wangxiaoyun@huawei.com>,\n\t<zhouguoyang@huawei.com>, <shahar.belkar@huawei.com>,\n\t<stephen@networkplumber.org>, <luoxianjun@huawei.com>, Ziyang Xuan\n\t<xuanziyang2@huawei.com>", "Date": "Thu, 6 Jun 2019 19:06:28 +0800", "Message-ID": "<74886a52875fbfc99e45c9ae9fd6b549cfcb33a6.1559818024.git.xuanziyang2@huawei.com>", "X-Mailer": "git-send-email 2.18.0", "In-Reply-To": "<cover.1559818024.git.xuanziyang2@huawei.com>", "References": "<cover.1559818024.git.xuanziyang2@huawei.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Originating-IP": "[10.175.119.39]", "X-CFilter-Loop": "Reflected", "Subject": "[dpdk-dev] [PATCH v4 08/11] net/hinic: add hinic PMD build and doc\n\tfiles", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Add build and doc files, and common code files.\n\nSigned-off-by: Ziyang Xuan <xuanziyang2@huawei.com>\n---\n MAINTAINERS | 9 +\n config/common_base | 5 +\n config/common_linux | 5 +\n config/defconfig_arm-armv7a-linuxapp-gcc | 1 +\n config/defconfig_i686-native-linuxapp-gcc | 5 +\n config/defconfig_i686-native-linuxapp-icc | 5 +\n config/defconfig_ppc_64-power8-linuxapp-gcc | 1 +\n config/defconfig_x86_64-native-linuxapp-icc | 5 +\n config/defconfig_x86_x32-native-linuxapp-gcc | 5 +\n doc/guides/nics/features/hinic.ini | 37 +\n doc/guides/nics/hinic.rst | 55 ++\n drivers/net/Makefile | 1 +\n drivers/net/hinic/Makefile | 73 ++\n drivers/net/hinic/base/meson.build | 50 ++\n drivers/net/hinic/hinic_pmd_dpdev.c | 702 +++++++++++++++++++\n drivers/net/hinic/hinic_pmd_ethdev.c | 25 +\n drivers/net/hinic/meson.build | 18 +\n mk/rte.app.mk | 1 +\n 18 files changed, 1003 insertions(+)\n create mode 100644 doc/guides/nics/features/hinic.ini\n create mode 100644 doc/guides/nics/hinic.rst\n create mode 100644 drivers/net/hinic/Makefile\n create mode 100644 drivers/net/hinic/base/meson.build\n create mode 100644 drivers/net/hinic/hinic_pmd_dpdev.c\n create mode 100644 drivers/net/hinic/hinic_pmd_ethdev.c\n create mode 100644 drivers/net/hinic/meson.build", "diff": "diff --git a/MAINTAINERS b/MAINTAINERS\nindex d0bf259b8..bc56fbf26 100644\n--- a/MAINTAINERS\n+++ b/MAINTAINERS\n@@ -577,6 +577,15 @@ F: drivers/net/enic/\n F: doc/guides/nics/enic.rst\n F: doc/guides/nics/features/enic.ini\n \n+Huawei hinic\n+M: Xiaoyun Wang <cloud.wangxiaoyun@huawei.com>\n+M: Ziyang Xuan <xuanziyang2@huawei.com>\n+M: Guoyang Zhou <zhouguoyang@huawei.com>\n+M: Shahar Belkar <shahar.belkar@huawei.com>\n+F: drivers/net/hinic/\n+F: doc/guides/nics/hinic.rst\n+F: doc/guides/nics/features/hinic.ini\n+\n Intel e1000\n M: Wenzhuo Lu <wenzhuo.lu@intel.com>\n T: git://dpdk.org/next/dpdk-next-net-intel\ndiff --git a/config/common_base b/config/common_base\nindex 6f19ad5d2..53bb2512d 100644\n--- a/config/common_base\n+++ b/config/common_base\n@@ -276,6 +276,11 @@ CONFIG_RTE_LIBRTE_E1000_DEBUG_TX=n\n CONFIG_RTE_LIBRTE_E1000_DEBUG_TX_FREE=n\n CONFIG_RTE_LIBRTE_E1000_PF_DISABLE_STRIP_CRC=n\n \n+#\n+# Compile burst-oriented HINIC PMD driver\n+#\n+CONFIG_RTE_LIBRTE_HINIC_PMD=n\n+\n #\n # Compile burst-oriented IXGBE PMD driver\n #\ndiff --git a/config/common_linux b/config/common_linux\nindex 75334273d..d6d946138 100644\n--- a/config/common_linux\n+++ b/config/common_linux\n@@ -57,3 +57,8 @@ CONFIG_RTE_LIBRTE_PMD_DPAA2_QDMA_RAWDEV=y\n # NXP ENETC PMD Driver\n #\n CONFIG_RTE_LIBRTE_ENETC_PMD=y\n+\n+#\n+# HINIC PMD driver\n+#\n+CONFIG_RTE_LIBRTE_HINIC_PMD=y\ndiff --git a/config/defconfig_arm-armv7a-linuxapp-gcc b/config/defconfig_arm-armv7a-linuxapp-gcc\nindex c9509b274..562439c0b 100644\n--- a/config/defconfig_arm-armv7a-linuxapp-gcc\n+++ b/config/defconfig_arm-armv7a-linuxapp-gcc\n@@ -54,3 +54,4 @@ CONFIG_RTE_LIBRTE_QEDE_PMD=n\n CONFIG_RTE_LIBRTE_SFC_EFX_PMD=n\n CONFIG_RTE_LIBRTE_AVP_PMD=n\n CONFIG_RTE_LIBRTE_NFP_PMD=n\n+CONFIG_RTE_LIBRTE_HINIC_PMD=n\ndiff --git a/config/defconfig_i686-native-linuxapp-gcc b/config/defconfig_i686-native-linuxapp-gcc\nindex 0340c84cf..07fc5f880 100644\n--- a/config/defconfig_i686-native-linuxapp-gcc\n+++ b/config/defconfig_i686-native-linuxapp-gcc\n@@ -54,3 +54,8 @@ CONFIG_RTE_LIBRTE_NFP_PMD=n\n \n # 32-bit doesn't break up memory in lists, but does have VA allocation limit\n CONFIG_RTE_MAX_MEM_MB=2048\n+\n+#\n+# HINIC PMD is not supported on 32-bit\n+#\n+CONFIG_RTE_LIBRTE_HINIC_PMD=n\ndiff --git a/config/defconfig_i686-native-linuxapp-icc b/config/defconfig_i686-native-linuxapp-icc\nindex 34a55fd18..34f34d5ce 100644\n--- a/config/defconfig_i686-native-linuxapp-icc\n+++ b/config/defconfig_i686-native-linuxapp-icc\n@@ -54,3 +54,8 @@ CONFIG_RTE_LIBRTE_NFP_PMD=n\n \n # 32-bit doesn't break up memory in lists, but does have VA allocation limit\n CONFIG_RTE_MAX_MEM_MB=2048\n+\n+#\n+# HINIC PMD is not supported on 32-bit\n+#\n+CONFIG_RTE_LIBRTE_HINIC_PMD=n\ndiff --git a/config/defconfig_ppc_64-power8-linuxapp-gcc b/config/defconfig_ppc_64-power8-linuxapp-gcc\nindex 7e248b755..cec434563 100644\n--- a/config/defconfig_ppc_64-power8-linuxapp-gcc\n+++ b/config/defconfig_ppc_64-power8-linuxapp-gcc\n@@ -56,3 +56,4 @@ CONFIG_RTE_LIBRTE_ENIC_PMD=n\n CONFIG_RTE_LIBRTE_FM10K_PMD=n\n CONFIG_RTE_LIBRTE_SFC_EFX_PMD=n\n CONFIG_RTE_LIBRTE_AVP_PMD=n\n+CONFIG_RTE_LIBRTE_HINIC_PMD=n\ndiff --git a/config/defconfig_x86_64-native-linuxapp-icc b/config/defconfig_x86_64-native-linuxapp-icc\nindex d3ecae475..d82b9229d 100644\n--- a/config/defconfig_x86_64-native-linuxapp-icc\n+++ b/config/defconfig_x86_64-native-linuxapp-icc\n@@ -17,3 +17,8 @@ CONFIG_RTE_TOOLCHAIN_ICC=y\n # Solarflare PMD build is not supported using icc toolchain\n #\n CONFIG_RTE_LIBRTE_SFC_EFX_PMD=n\n+\n+#\n+# HINIC PMD build is not supported using icc toolchain\n+#\n+CONFIG_RTE_LIBRTE_HINIC_PMD=n\ndiff --git a/config/defconfig_x86_x32-native-linuxapp-gcc b/config/defconfig_x86_x32-native-linuxapp-gcc\nindex 14445abaa..bcc72086a 100644\n--- a/config/defconfig_x86_x32-native-linuxapp-gcc\n+++ b/config/defconfig_x86_x32-native-linuxapp-gcc\n@@ -34,3 +34,8 @@ CONFIG_RTE_LIBRTE_NFP_PMD=n\n \n # 32-bit doesn't break up memory in lists, but does have VA allocation limit\n CONFIG_RTE_MAX_MEM_MB=2048\n+\n+#\n+# HINIC PMD is not supported on 32-bit\n+#\n+CONFIG_RTE_LIBRTE_HINIC_PMD=n\ndiff --git a/doc/guides/nics/features/hinic.ini b/doc/guides/nics/features/hinic.ini\nnew file mode 100644\nindex 000000000..fe063d6f5\n--- /dev/null\n+++ b/doc/guides/nics/features/hinic.ini\n@@ -0,0 +1,37 @@\n+;\n+; Supported features of the 'hinic' network poll mode driver.\n+;\n+; Refer to default.ini for the full list of available PMD features.\n+;\n+[Features]\n+Speed capabilities = Y\n+Link status = Y\n+Link status event = Y\n+Free Tx mbuf on demand = Y\n+Queue start/stop = Y\n+Jumbo frame = N\n+Scattered Rx = Y\n+TSO = Y\n+Promiscuous mode = Y\n+Unicast MAC filter = Y\n+Multicast MAC filter = Y\n+RSS hash = Y\n+RSS key update = Y\n+RSS reta update = Y\n+Inner RSS = Y\n+CRC offload = Y\n+L3 checksum offload = Y\n+L4 checksum offload = Y\n+Inner L3 checksum = Y\n+Inner L4 checksum = Y\n+Basic stats = Y\n+Extended stats = Y\n+Stats per queue = Y\n+Linux UIO = Y\n+Linux VFIO = Y\n+BSD nic_uio = N\n+x86-64 = Y\n+ARMv8 = Y\n+ARMv7 = N\n+x86-32 = N\n+Power8 = N\ndiff --git a/doc/guides/nics/hinic.rst b/doc/guides/nics/hinic.rst\nnew file mode 100644\nindex 000000000..c56976bf9\n--- /dev/null\n+++ b/doc/guides/nics/hinic.rst\n@@ -0,0 +1,55 @@\n+.. SPDX-License-Identifier: BSD-3-Clause\n+ Copyright(c) 2017 Huawei Technologies Co., Ltd\n+\n+\n+HINIC Poll Mode Driver\n+======================\n+\n+The hinic PMD (librte_pmd_hinic) provides poll mode driver support for\n+25 Gbps Huawei Intelligent PCIE Network Adapters based on\n+the Huawei Ethernet Controller Hi1822.\n+\n+\n+Features\n+--------\n+\n+- Multi arch support: x86_64, ARMv8.\n+- Multiple queues for TX and RX\n+- Receiver Side Scaling (RSS)\n+- MAC/VLAN filtering\n+- Checksum offload\n+- TSO offload\n+- Promiscuous mode\n+- Port hardware statistics\n+- Jumbo frames\n+- Link state information\n+- Link flow control\n+- Scattered and gather for TX and RX\n+\n+Prerequisites\n+-------------\n+\n+- Follow the DPDK :ref:`Getting Started Guide for Linux <linux_gsg>` to setup the basic DPDK environment.\n+\n+Requires firmware 1.6.2.5\n+\n+Pre-Installation Configuration\n+------------------------------\n+\n+Config File Options\n+~~~~~~~~~~~~~~~~~~~\n+\n+The following options can be modified in the ``config`` file.\n+\n+- ``CONFIG_RTE_LIBRTE_HINIC_PMD`` (default ``y``)\n+\n+Driver compilation and testing\n+------------------------------\n+\n+Refer to the document :ref:`compiling and testing a PMD for a NIC <pmd_build_and_test>`\n+for details.\n+\n+Limitations or Known issues\n+---------------------------\n+Build with ICC is not supported yet.\n+X86-32, Power8, ARMv7 and BSD are not supported yet.\ndiff --git a/drivers/net/Makefile b/drivers/net/Makefile\nindex 3a72cf38c..606b27456 100644\n--- a/drivers/net/Makefile\n+++ b/drivers/net/Makefile\n@@ -29,6 +29,7 @@ DIRS-$(CONFIG_RTE_LIBRTE_ENETC_PMD) += enetc\n DIRS-$(CONFIG_RTE_LIBRTE_ENIC_PMD) += enic\n DIRS-$(CONFIG_RTE_LIBRTE_PMD_FAILSAFE) += failsafe\n DIRS-$(CONFIG_RTE_LIBRTE_FM10K_PMD) += fm10k\n+DIRS-$(CONFIG_RTE_LIBRTE_HINIC_PMD) += hinic\n DIRS-$(CONFIG_RTE_LIBRTE_I40E_PMD) += i40e\n DIRS-$(CONFIG_RTE_LIBRTE_IAVF_PMD) += iavf\n DIRS-$(CONFIG_RTE_LIBRTE_ICE_PMD) += ice\ndiff --git a/drivers/net/hinic/Makefile b/drivers/net/hinic/Makefile\nnew file mode 100644\nindex 000000000..d0f955ce1\n--- /dev/null\n+++ b/drivers/net/hinic/Makefile\n@@ -0,0 +1,73 @@\n+# SPDX-License-Identifier: BSD-3-Clause\n+# Copyright(c) 2017 Huawei Technologies Co., Ltd\n+\n+include $(RTE_SDK)/mk/rte.vars.mk\n+\n+#\n+# library name\n+#\n+LIB = librte_pmd_hinic.a\n+\n+CFLAGS += -O3\n+CFLAGS += $(WERROR_FLAGS)\n+\n+ifeq ($(CONFIG_RTE_ARCH_ARM64),y)\n+CFLAGS += -D__ARM64_NEON__\n+endif\n+\n+EXPORT_MAP := rte_pmd_hinic_version.map\n+\n+LIBABIVER := 1\n+\n+#\n+# Add extra flags for base driver files (also known as shared code)\n+# to disable warnings\n+#\n+ifeq ($(CONFIG_RTE_TOOLCHAIN_ICC),y)\n+CFLAGS_BASE_DRIVER = -diag-disable 593\n+else\n+CFLAGS_BASE_DRIVER = -Wno-sign-compare\n+CFLAGS_BASE_DRIVER += -Wno-unused-parameter\n+CFLAGS_BASE_DRIVER += -Wno-strict-aliasing\n+CFLAGS_BASE_DRIVER += -Wno-missing-field-initializers\n+CFLAGS_BASE_DRIVER += -Wno-pointer-to-int-cast\n+endif\n+\n+OBJS_BASE_DRIVER=$(sort $(patsubst %.c,%.o,$(notdir $(wildcard $(SRCDIR)/base/*.c))))\n+$(foreach obj, $(OBJS_BASE_DRIVER), $(eval CFLAGS_$(obj)+=$(CFLAGS_BASE_DRIVER)))\n+\n+VPATH += $(SRCDIR)/base\n+\n+#\n+# all source are stored in SRCS-y\n+#\n+SRCS-$(CONFIG_RTE_LIBRTE_HINIC_PMD) += hinic_pmd_api_cmd.c\n+SRCS-$(CONFIG_RTE_LIBRTE_HINIC_PMD) += hinic_pmd_cfg.c\n+SRCS-$(CONFIG_RTE_LIBRTE_HINIC_PMD) += hinic_pmd_cmdq.c\n+SRCS-$(CONFIG_RTE_LIBRTE_HINIC_PMD) += hinic_pmd_eqs.c\n+SRCS-$(CONFIG_RTE_LIBRTE_HINIC_PMD) += hinic_pmd_hwdev.c\n+SRCS-$(CONFIG_RTE_LIBRTE_HINIC_PMD) += hinic_pmd_hwif.c\n+SRCS-$(CONFIG_RTE_LIBRTE_HINIC_PMD) += hinic_pmd_mgmt.c\n+SRCS-$(CONFIG_RTE_LIBRTE_HINIC_PMD) += hinic_pmd_niccfg.c\n+SRCS-$(CONFIG_RTE_LIBRTE_HINIC_PMD) += hinic_pmd_nicio.c\n+SRCS-$(CONFIG_RTE_LIBRTE_HINIC_PMD) += hinic_pmd_qp.c\n+SRCS-$(CONFIG_RTE_LIBRTE_HINIC_PMD) += hinic_pmd_wq.c\n+\n+SRCS-$(CONFIG_RTE_LIBRTE_HINIC_PMD) += hinic_pmd_dpdev.c\n+SRCS-$(CONFIG_RTE_LIBRTE_HINIC_PMD) += hinic_pmd_ethdev.c\n+#SRCS-$(CONFIG_RTE_LIBRTE_HINIC_PMD) += hinic_pmd_rx.c\n+#SRCS-$(CONFIG_RTE_LIBRTE_HINIC_PMD) += hinic_pmd_tx.c\n+\n+# this lib depends upon:\n+DEPDIRS-$(CONFIG_RTE_LIBRTE_HINIC_PMD) += lib/librte_eal lib/librte_ether\n+DEPDIRS-$(CONFIG_RTE_LIBRTE_HINIC_PMD) += lib/librte_mempool lib/librte_mbuf\n+DEPDIRS-$(CONFIG_RTE_LIBRTE_HINIC_PMD) += lib/librte_net lib/librte_hash\n+DEPDIRS-$(CONFIG_RTE_LIBRTE_HINIC_PMD) += lib/librte_kvargs\n+DEPDIRS-$(CONFIG_RTE_LIBRTE_HINIC_PMD) += lib/librte_net\n+DEPDIRS-$(CONFIG_RTE_LIBRTE_HINIC_PMD) += lib/librte_ring\n+\n+LDLIBS += -lrte_eal -lrte_mbuf -lrte_mempool -lrte_ring\n+LDLIBS += -lrte_ethdev -lrte_net -lrte_kvargs -lrte_hash\n+LDLIBS += -lrte_bus_pci\n+\n+include $(RTE_SDK)/mk/rte.lib.mk\ndiff --git a/drivers/net/hinic/base/meson.build b/drivers/net/hinic/base/meson.build\nnew file mode 100644\nindex 000000000..fa235f462\n--- /dev/null\n+++ b/drivers/net/hinic/base/meson.build\n@@ -0,0 +1,50 @@\n+# SPDX-License-Identifier: BSD-3-Clause\n+# Copyright(c) 2017 Huawei Technologies Co., Ltd\n+\n+sources = [\n+\t'hinic_pmd_api_cmd.c',\n+\t'hinic_pmd_cfg.c',\n+\t'hinic_pmd_cmdq.c',\n+\t'hinic_pmd_eqs.c',\n+\t'hinic_pmd_hwdev.c',\n+\t'hinic_pmd_hwif.c',\n+\t'hinic_pmd_mgmt.c',\n+\t'hinic_pmd_niccfg.c',\n+\t'hinic_pmd_nicio.c',\n+\t'hinic_pmd_qp.c',\n+\t'hinic_pmd_wq.c',\n+]\n+\n+headers = [\n+\t'hinic_compat.h',\n+\t'hinic_csr.h',\n+\t'hinic_ctx_def.h',\n+\t'hinic_pmd_api_cmd.h',\n+\t'hinic_pmd_cfg.h',\n+\t'hinic_pmd_cmdq.h',\n+\t'hinic_pmd_dpdev.h',\n+\t'hinic_pmd_eqs.h',\n+\t'hinic_pmd_hwdev.h',\n+\t'hinic_pmd_hw.h',\n+\t'hinic_pmd_hwif.h',\n+\t'hinic_pmd_hw_mgmt.h',\n+\t'hinic_pmd_mgmt.h',\n+\t'hinic_pmd_mgmt_interface.h',\n+\t'hinic_pmd_niccfg.h',\n+\t'hinic_pmd_nic.h',\n+\t'hinic_pmd_nicio.h',\n+\t'hinic_pmd_qp.h',\n+\t'hinic_pmd_wq.h',\n+\t'hinic_port_cmd.h',\n+\t'hinic_qe_def.h',\n+]\n+\n+deps += 'ethdev'\n+deps += 'pci'\n+\n+c_args = cflags\n+\n+base_lib = static_library('hinic_base', sources,\n+\tdependencies: static_rte_eal,\n+\tc_args: c_args)\n+base_objs = base_lib.extract_all_objects()\ndiff --git a/drivers/net/hinic/hinic_pmd_dpdev.c b/drivers/net/hinic/hinic_pmd_dpdev.c\nnew file mode 100644\nindex 000000000..2e0abe406\n--- /dev/null\n+++ b/drivers/net/hinic/hinic_pmd_dpdev.c\n@@ -0,0 +1,702 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2017 Huawei Technologies Co., Ltd\n+ */\n+\n+#include <rte_hash.h>\n+#include <rte_jhash.h>\n+#include <rte_bus_pci.h>\n+#include <rte_ethdev_driver.h>\n+\n+#include \"base/hinic_pmd_dpdev.h\"\n+#include \"hinic_pmd_ethdev.h\"\n+\n+#define DEFAULT_BASE_COS\t(4)\n+#define NR_MAX_COS\t\t(8)\n+#define HINIC_HASH_FUNC rte_jhash\n+#define HINIC_HASH_KEY_LEN (sizeof(dma_addr_t))\n+#define HINIC_HASH_FUNC_INIT_VAL\t(0)\n+#define HINIC_SERVICE_MODE_OVS\t\t(0)\n+\n+/* dma pool */\n+struct dma_pool {\n+\tu32 inuse;\n+\tsize_t elem_size;\n+\tsize_t align;\n+\tsize_t boundary;\n+\tvoid *nic_dev;\n+\n+\tchar name[32];\n+};\n+\n+static int hinic_osdep_init(struct hinic_nic_dev *nic_dev)\n+{\n+\tstruct rte_hash_parameters dh_params = { 0 };\n+\tstruct rte_hash *paddr_hash = NULL;\n+\n+\tnic_dev->os_dep = &nic_dev->dumb_os_dep;\n+\n+\trte_atomic32_set(&nic_dev->os_dep->dma_alloc_cnt, 0);\n+\trte_spinlock_init(&nic_dev->os_dep->dma_hash_lock);\n+\n+\tdh_params.name = nic_dev->proc_dev_name;\n+\tdh_params.entries = HINIC_MAX_DMA_ENTRIES;\n+\tdh_params.key_len = HINIC_HASH_KEY_LEN;\n+\tdh_params.hash_func = HINIC_HASH_FUNC;\n+\tdh_params.hash_func_init_val = HINIC_HASH_FUNC_INIT_VAL;\n+\tdh_params.socket_id = SOCKET_ID_ANY;\n+\n+\tpaddr_hash = rte_hash_find_existing(dh_params.name);\n+\tif (paddr_hash == NULL) {\n+\t\tpaddr_hash = rte_hash_create(&dh_params);\n+\t\tif (paddr_hash == NULL) {\n+\t\t\tPMD_DRV_LOG(ERR, \"Create nic_dev phys_addr hash table failed\");\n+\t\t\treturn -ENOMEM;\n+\t\t}\n+\t} else {\n+\t\tPMD_DRV_LOG(INFO, \"Using existing dma hash table %s\",\n+\t\t\t dh_params.name);\n+\t}\n+\tnic_dev->os_dep->dma_addr_hash = paddr_hash;\n+\n+\treturn 0;\n+}\n+\n+static void hinic_osdep_deinit(struct hinic_nic_dev *nic_dev)\n+{\n+\tuint32_t iter = 0;\n+\tdma_addr_t key_pa;\n+\tstruct rte_memzone *data_mz = NULL;\n+\tstruct rte_hash *paddr_hash = nic_dev->os_dep->dma_addr_hash;\n+\n+\tif (paddr_hash) {\n+\t\t/* iterate through the hash table */\n+\t\twhile (rte_hash_iterate(paddr_hash, (const void **)&key_pa,\n+\t\t\t\t\t(void **)&data_mz, &iter) >= 0) {\n+\t\t\tif (data_mz) {\n+\t\t\t\tPMD_DRV_LOG(WARNING, \"Free leaked dma_addr: %p, mz: %s\",\n+\t\t\t\t\t(void *)key_pa, data_mz->name);\n+\t\t\t\t(void)rte_memzone_free(data_mz);\n+\t\t\t}\n+\t\t}\n+\n+\t\t/* free phys_addr hash table */\n+\t\trte_hash_free(paddr_hash);\n+\t}\n+\n+\tnic_dev->os_dep = NULL;\n+}\n+\n+void *hinic_dma_mem_zalloc(void *dev, size_t size, dma_addr_t *dma_handle,\n+\t\t\t unsigned int flag, unsigned int align)\n+{\n+\tint rc, alloc_cnt;\n+\tconst struct rte_memzone *mz;\n+\tchar z_name[RTE_MEMZONE_NAMESIZE];\n+\tstruct hinic_nic_dev *nic_dev = (struct hinic_nic_dev *)dev;\n+\thash_sig_t sig;\n+\trte_iova_t iova;\n+\n+\tHINIC_ASSERT((nic_dev != NULL) &&\n+\t\t (nic_dev->os_dep->dma_addr_hash != NULL));\n+\n+\tif (dma_handle == NULL || 0 == size)\n+\t\treturn NULL;\n+\n+\talloc_cnt = rte_atomic32_add_return(&nic_dev->os_dep->dma_alloc_cnt, 1);\n+\tsnprintf(z_name, sizeof(z_name), \"%s_%d\",\n+\t\t nic_dev->proc_dev_name, alloc_cnt);\n+\n+\tmz = rte_memzone_reserve_aligned(z_name, size, SOCKET_ID_ANY,\n+\t\t\t\t\t flag, align);\n+\tif (!mz) {\n+\t\tPMD_DRV_LOG(ERR, \"Alloc dma able memory failed, errno: %d, ma_name: %s, size: 0x%zx\",\n+\t\t\t rte_errno, z_name, size);\n+\t\treturn NULL;\n+\t}\n+\n+\tiova = mz->iova;\n+\n+\t/* check if phys_addr already exist */\n+\tsig = HINIC_HASH_FUNC(&iova, HINIC_HASH_KEY_LEN,\n+\t\t\t HINIC_HASH_FUNC_INIT_VAL);\n+\trc = rte_hash_lookup_with_hash(nic_dev->os_dep->dma_addr_hash,\n+\t\t\t\t &iova, sig);\n+\tif (rc >= 0) {\n+\t\tPMD_DRV_LOG(ERR, \"Dma addr: %p already in hash table, error: %d, mz_name: %s\",\n+\t\t\t(void *)iova, rc, z_name);\n+\t\tgoto phys_addr_hash_err;\n+\t}\n+\n+\t/* record paddr in hash table */\n+\trte_spinlock_lock(&nic_dev->os_dep->dma_hash_lock);\n+\trc = rte_hash_add_key_with_hash_data(nic_dev->os_dep->dma_addr_hash,\n+\t\t\t\t\t &iova, sig,\n+\t\t\t\t\t (void *)(u64)mz);\n+\trte_spinlock_unlock(&nic_dev->os_dep->dma_hash_lock);\n+\tif (rc) {\n+\t\tPMD_DRV_LOG(ERR, \"Insert dma addr: %p hash failed, error: %d, mz_name: %s\",\n+\t\t\t(void *)iova, rc, z_name);\n+\t\tgoto phys_addr_hash_err;\n+\t}\n+\t*dma_handle = iova;\n+\tmemset(mz->addr, 0, size);\n+\n+\treturn mz->addr;\n+\n+phys_addr_hash_err:\n+\t(void)rte_memzone_free(mz);\n+\n+\treturn NULL;\n+}\n+\n+void hinic_dma_mem_free(void *dev, size_t size, void *virt, dma_addr_t phys)\n+{\n+\tint rc;\n+\tstruct rte_memzone *mz = NULL;\n+\tstruct hinic_nic_dev *nic_dev = (struct hinic_nic_dev *)dev;\n+\tstruct rte_hash *hash;\n+\thash_sig_t sig;\n+\n+\tHINIC_ASSERT((nic_dev != NULL) &&\n+\t\t (nic_dev->os_dep->dma_addr_hash != NULL));\n+\n+\tif (virt == NULL || phys == 0)\n+\t\treturn;\n+\n+\thash = nic_dev->os_dep->dma_addr_hash;\n+\tsig = HINIC_HASH_FUNC(&phys, HINIC_HASH_KEY_LEN,\n+\t\t\t HINIC_HASH_FUNC_INIT_VAL);\n+\trc = rte_hash_lookup_with_hash_data(hash, &phys, sig, (void **)&mz);\n+\tif (rc < 0) {\n+\t\tPMD_DRV_LOG(ERR, \"Can not find phys_addr: %p, error: %d\",\n+\t\t\t(void *)phys, rc);\n+\t\treturn;\n+\t}\n+\n+\tHINIC_ASSERT(mz != NULL);\n+\tif (virt != mz->addr || size > mz->len) {\n+\t\tPMD_DRV_LOG(ERR, \"Match mz_info failed: \"\n+\t\t\t\"mz.name: %s, mz.phys: %p, mz.virt: %p, mz.len: %zu, \"\n+\t\t\t\"phys: %p, virt: %p, size: %zu\",\n+\t\t\tmz->name, (void *)mz->iova, mz->addr, mz->len,\n+\t\t\t(void *)phys, virt, size);\n+\t}\n+\n+\trte_spinlock_lock(&nic_dev->os_dep->dma_hash_lock);\n+\t(void)rte_hash_del_key_with_hash(hash, &phys, sig);\n+\trte_spinlock_unlock(&nic_dev->os_dep->dma_hash_lock);\n+\n+\t(void)rte_memzone_free(mz);\n+}\n+\n+void *dma_zalloc_coherent(void *dev, size_t size,\n+\t\t\t dma_addr_t *dma_handle, gfp_t flag)\n+{\n+\treturn hinic_dma_mem_zalloc(dev, size, dma_handle, flag,\n+\t\t\t\t RTE_CACHE_LINE_SIZE);\n+}\n+\n+void *dma_zalloc_coherent_aligned(void *dev, size_t size,\n+\t\t\t\t dma_addr_t *dma_handle, gfp_t flag)\n+{\n+\treturn hinic_dma_mem_zalloc(dev, size, dma_handle, flag,\n+\t\t\t\t HINIC_PAGE_SIZE);\n+}\n+\n+void *dma_zalloc_coherent_aligned256k(void *dev, size_t size,\n+\t\t\t\t dma_addr_t *dma_handle, gfp_t flag)\n+{\n+\treturn hinic_dma_mem_zalloc(dev, size, dma_handle, flag,\n+\t\t\t\t HINIC_PAGE_SIZE * 64);\n+}\n+\n+void dma_free_coherent(void *dev, size_t size, void *virt, dma_addr_t phys)\n+{\n+\thinic_dma_mem_free(dev, size, virt, phys);\n+}\n+\n+void dma_free_coherent_volatile(void *dev, size_t size,\n+\t\t\t\tvolatile void *virt, dma_addr_t phys)\n+{\n+\tint rc;\n+\tstruct rte_memzone *mz = NULL;\n+\tstruct hinic_nic_dev *nic_dev = (struct hinic_nic_dev *)dev;\n+\tstruct rte_hash *hash;\n+\thash_sig_t sig;\n+\n+\tHINIC_ASSERT((nic_dev != NULL) &&\n+\t\t (nic_dev->os_dep->dma_addr_hash != NULL));\n+\n+\tif (virt == NULL || phys == 0)\n+\t\treturn;\n+\n+\thash = nic_dev->os_dep->dma_addr_hash;\n+\tsig = HINIC_HASH_FUNC(&phys, HINIC_HASH_KEY_LEN,\n+\t\t\t HINIC_HASH_FUNC_INIT_VAL);\n+\trc = rte_hash_lookup_with_hash_data(hash, &phys, sig, (void **)&mz);\n+\tif (rc < 0) {\n+\t\tPMD_DRV_LOG(ERR, \"Can not find phys_addr: %p, error: %d\",\n+\t\t\t(void *)phys, rc);\n+\t\treturn;\n+\t}\n+\n+\tHINIC_ASSERT(mz != NULL);\n+\tif (virt != mz->addr || size > mz->len) {\n+\t\tPMD_DRV_LOG(ERR, \"Match mz_info failed: \"\n+\t\t\t\"mz.name:%s, mz.phys:%p, mz.virt:%p, mz.len:%zu, \"\n+\t\t\t\"phys:%p, virt:%p, size:%zu\",\n+\t\t\tmz->name, (void *)mz->iova, mz->addr, mz->len,\n+\t\t\t(void *)phys, virt, size);\n+\t}\n+\n+\trte_spinlock_lock(&nic_dev->os_dep->dma_hash_lock);\n+\t(void)rte_hash_del_key_with_hash(hash, &phys, sig);\n+\trte_spinlock_unlock(&nic_dev->os_dep->dma_hash_lock);\n+\n+\t(void)rte_memzone_free(mz);\n+}\n+\n+struct dma_pool *dma_pool_create(const char *name, void *dev,\n+\t\t\t\t size_t size, size_t align, size_t boundary)\n+{\n+\tstruct pci_pool *pool;\n+\n+\tpool = (struct pci_pool *)rte_zmalloc(NULL, sizeof(*pool),\n+\t\t\t\t\t HINIC_MEM_ALLOC_ALIGNE_MIN);\n+\tif (!pool)\n+\t\treturn NULL;\n+\n+\tpool->inuse = 0;\n+\tpool->elem_size = size;\n+\tpool->align = align;\n+\tpool->boundary = boundary;\n+\tpool->nic_dev = dev;\n+\tstrncpy(pool->name, name, (sizeof(pool->name) - 1));\n+\n+\treturn pool;\n+}\n+\n+void dma_pool_destroy(struct dma_pool *pool)\n+{\n+\tif (!pool)\n+\t\treturn;\n+\n+\tif (pool->inuse != 0) {\n+\t\tPMD_DRV_LOG(ERR, \"Leak memory, dma_pool:%s, inuse_count:%u\",\n+\t\t\t pool->name, pool->inuse);\n+\t}\n+\n+\trte_free(pool);\n+}\n+\n+void *dma_pool_alloc(struct pci_pool *pool, int flags, dma_addr_t *dma_addr)\n+{\n+\tvoid *buf;\n+\n+\tbuf = hinic_dma_mem_zalloc(pool->nic_dev, pool->elem_size,\n+\t\t\t\t dma_addr, flags, (u32)pool->align);\n+\tif (buf)\n+\t\tpool->inuse++;\n+\n+\treturn buf;\n+}\n+\n+void dma_pool_free(struct pci_pool *pool, void *vaddr, dma_addr_t dma)\n+{\n+\tpool->inuse--;\n+\thinic_dma_mem_free(pool->nic_dev, pool->elem_size, vaddr, dma);\n+}\n+\n+int hinic_link_event_process(struct rte_eth_dev *dev, u8 status)\n+{\n+\tstruct hinic_nic_dev *nic_dev = HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev);\n+\tuint32_t port_speed[LINK_SPEED_MAX] = {ETH_SPEED_NUM_10M,\n+\t\t\t\t\tETH_SPEED_NUM_100M, ETH_SPEED_NUM_1G,\n+\t\t\t\t\tETH_SPEED_NUM_10G, ETH_SPEED_NUM_25G,\n+\t\t\t\t\tETH_SPEED_NUM_40G, ETH_SPEED_NUM_100G};\n+\tstruct nic_port_info port_info;\n+\tstruct rte_eth_link link;\n+\tint rc = HINIC_OK;\n+\n+\tnic_dev->link_status = status;\n+\tif (!status) {\n+\t\tlink.link_status = ETH_LINK_DOWN;\n+\t\tlink.link_speed = 0;\n+\t\tlink.link_duplex = ETH_LINK_HALF_DUPLEX;\n+\t\tlink.link_autoneg = ETH_LINK_FIXED;\n+\t} else {\n+\t\tlink.link_status = ETH_LINK_UP;\n+\n+\t\tmemset(&port_info, 0, sizeof(port_info));\n+\t\trc = hinic_get_port_info(nic_dev->hwdev, &port_info);\n+\t\tif (rc) {\n+\t\t\tlink.link_speed = ETH_SPEED_NUM_NONE;\n+\t\t\tlink.link_duplex = ETH_LINK_FULL_DUPLEX;\n+\t\t\tlink.link_autoneg = ETH_LINK_FIXED;\n+\t\t} else {\n+\t\t\tlink.link_speed = port_speed[port_info.speed %\n+\t\t\t\t\t\tLINK_SPEED_MAX];\n+\t\t\tlink.link_duplex = port_info.duplex;\n+\t\t\tlink.link_autoneg = port_info.autoneg_state;\n+\t\t}\n+\t}\n+\t(void)rte_eth_linkstatus_set(dev, &link);\n+\n+\treturn rc;\n+}\n+\n+void hinic_lsc_process(struct rte_eth_dev *rte_dev, u8 status)\n+{\n+\tint ret;\n+\n+\tret = hinic_link_event_process(rte_dev, status);\n+\t/* check if link has changed, notify callback */\n+\tif (ret == 0)\n+\t\t_rte_eth_dev_callback_process(rte_dev,\n+\t\t\t\t\t RTE_ETH_EVENT_INTR_LSC,\n+\t\t\t\t\t NULL);\n+}\n+\n+static int hinic_set_default_pause_feature(struct hinic_nic_dev *nic_dev)\n+{\n+\tstruct nic_pause_config pause_config = {0};\n+\n+\tpause_config.auto_neg = 0;\n+\tpause_config.rx_pause = HINIC_DEFAUT_PAUSE_CONFIG;\n+\tpause_config.tx_pause = HINIC_DEFAUT_PAUSE_CONFIG;\n+\n+\treturn hinic_set_pause_config(nic_dev->hwdev, pause_config);\n+}\n+\n+static int hinic_set_default_dcb_feature(struct hinic_nic_dev *nic_dev)\n+{\n+\tu8 up_tc[HINIC_DCB_UP_MAX] = {0};\n+\tu8 up_pgid[HINIC_DCB_UP_MAX] = {0};\n+\tu8 up_bw[HINIC_DCB_UP_MAX] = {0};\n+\tu8 pg_bw[HINIC_DCB_UP_MAX] = {0};\n+\tu8 up_strict[HINIC_DCB_UP_MAX] = {0};\n+\tint i = 0;\n+\n+\tpg_bw[0] = 100;\n+\tfor (i = 0; i < HINIC_DCB_UP_MAX; i++)\n+\t\tup_bw[i] = 100;\n+\n+\treturn hinic_dcb_set_ets(nic_dev->hwdev, up_tc, pg_bw,\n+\t\t\t\t\tup_pgid, up_bw, up_strict);\n+}\n+\n+static void hinic_init_default_cos(struct hinic_nic_dev *nic_dev)\n+{\n+\tnic_dev->default_cos =\n+\t\t\t(hinic_global_func_id(nic_dev->hwdev) +\n+\t\t\t DEFAULT_BASE_COS) % NR_MAX_COS;\n+}\n+\n+static int hinic_set_default_hw_feature(struct hinic_nic_dev *nic_dev)\n+{\n+\tint err;\n+\n+\thinic_init_default_cos(nic_dev);\n+\n+\t/* Restore DCB configure to default status */\n+\terr = hinic_set_default_dcb_feature(nic_dev);\n+\tif (err)\n+\t\treturn err;\n+\n+\t/* disable LRO */\n+\terr = hinic_set_rx_lro(nic_dev->hwdev, 0, 0, (u8)0);\n+\tif (err)\n+\t\treturn err;\n+\n+\t/* Set pause enable, and up will disable pfc. */\n+\terr = hinic_set_default_pause_feature(nic_dev);\n+\tif (err)\n+\t\treturn err;\n+\n+\terr = hinic_reset_port_link_cfg(nic_dev->hwdev);\n+\tif (err)\n+\t\treturn err;\n+\n+\terr = hinic_set_link_status_follow(nic_dev->hwdev,\n+\t\t\t\t\t HINIC_LINK_FOLLOW_PORT);\n+\tif (err == HINIC_MGMT_CMD_UNSUPPORTED)\n+\t\tPMD_DRV_LOG(WARNING, \"Don't support to set link status follow phy port status\");\n+\telse if (err)\n+\t\treturn err;\n+\n+\treturn hinic_set_anti_attack(nic_dev->hwdev, true);\n+}\n+\n+static int32_t hinic_card_workmode_check(struct hinic_nic_dev *nic_dev)\n+{\n+\tstruct hinic_board_info info = { 0 };\n+\tint rc;\n+\n+\trc = hinic_get_board_info(nic_dev->hwdev, &info);\n+\tif (rc)\n+\t\treturn rc;\n+\n+\t/*pf can not run dpdk in ovs mode*/\n+\treturn (info.service_mode != HINIC_SERVICE_MODE_OVS ? HINIC_OK :\n+\t\t\t\t\t\tHINIC_ERROR);\n+}\n+\n+static int hinic_copy_mempool_init(struct hinic_nic_dev *nic_dev)\n+{\n+\tnic_dev->cpy_mpool = rte_mempool_lookup(nic_dev->proc_dev_name);\n+\tif (nic_dev->cpy_mpool == NULL) {\n+\t\tnic_dev->cpy_mpool =\n+\t\trte_pktmbuf_pool_create(nic_dev->proc_dev_name,\n+\t\t\t\t\tHINIC_COPY_MEMPOOL_DEPTH,\n+\t\t\t\t\tRTE_CACHE_LINE_SIZE, 0,\n+\t\t\t\t\tHINIC_COPY_MBUF_SIZE,\n+\t\t\t\t\trte_socket_id());\n+\t\tif (!nic_dev->cpy_mpool) {\n+\t\t\tPMD_DRV_LOG(ERR, \"Create copy mempool failed, errno: %d, dev_name: %s\",\n+\t\t\t\t rte_errno, nic_dev->proc_dev_name);\n+\t\t\treturn -ENOMEM;\n+\t\t}\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static void hinic_copy_mempool_uninit(struct hinic_nic_dev *nic_dev)\n+{\n+\tif (nic_dev->cpy_mpool != NULL)\n+\t\trte_mempool_free(nic_dev->cpy_mpool);\n+}\n+\n+int hinic_init_sw_rxtxqs(struct hinic_nic_dev *nic_dev)\n+{\n+\tu32 txq_size;\n+\tu32 rxq_size;\n+\n+\t/* allocate software txq array */\n+\ttxq_size = nic_dev->nic_cap.max_sqs * sizeof(*nic_dev->txqs);\n+\tnic_dev->txqs = kzalloc_aligned(txq_size, GFP_KERNEL);\n+\tif (!nic_dev->txqs) {\n+\t\tPMD_DRV_LOG(ERR, \"Allocate txqs failed\");\n+\t\treturn -ENOMEM;\n+\t}\n+\n+\t/* allocate software rxq array */\n+\trxq_size = nic_dev->nic_cap.max_rqs * sizeof(*nic_dev->rxqs);\n+\tnic_dev->rxqs = kzalloc_aligned(rxq_size, GFP_KERNEL);\n+\tif (!nic_dev->rxqs) {\n+\t\t/* free txqs */\n+\t\tkfree(nic_dev->txqs);\n+\t\tnic_dev->txqs = NULL;\n+\n+\t\tPMD_DRV_LOG(ERR, \"Allocate rxqs failed\");\n+\t\treturn -ENOMEM;\n+\t}\n+\n+\treturn HINIC_OK;\n+}\n+\n+void hinic_deinit_sw_rxtxqs(struct hinic_nic_dev *nic_dev)\n+{\n+\tkfree(nic_dev->txqs);\n+\tnic_dev->txqs = NULL;\n+\n+\tkfree(nic_dev->rxqs);\n+\tnic_dev->rxqs = NULL;\n+}\n+\n+int32_t hinic_nic_dev_create(struct rte_eth_dev *eth_dev)\n+{\n+\tstruct hinic_nic_dev *nic_dev =\n+\t\t\t\tHINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(eth_dev);\n+\tint rc;\n+\n+\tnic_dev->hwdev =\n+\t\t(struct hinic_hwdev *)rte_zmalloc(\"hinic_hwdev\",\n+\t\t\t\t\t\t sizeof(*nic_dev->hwdev),\n+\t\t\t\t\t\t RTE_CACHE_LINE_SIZE);\n+\tif (!nic_dev->hwdev) {\n+\t\tPMD_DRV_LOG(ERR, \"Allocate hinic hwdev memory failed, dev_name: %s\",\n+\t\t\t eth_dev->data->name);\n+\t\treturn -ENOMEM;\n+\t}\n+\n+\tnic_dev->hwdev->pcidev_hdl =\n+\t\t\t(struct rte_pci_device *)RTE_ETH_DEV_TO_PCI(eth_dev);\n+\tnic_dev->hwdev->dev_hdl = nic_dev;\n+\n+\t/* init osdep*/\n+\trc = hinic_osdep_init(nic_dev);\n+\tif (rc) {\n+\t\tPMD_DRV_LOG(ERR, \"Initialize os_dep failed, dev_name: %s\",\n+\t\t\t eth_dev->data->name);\n+\t\tgoto init_osdep_fail;\n+\t}\n+\n+\t/* init_hwif */\n+\trc = hinic_hwif_res_init(nic_dev);\n+\tif (rc) {\n+\t\tPMD_DRV_LOG(ERR, \"Initialize hwif failed, dev_name: %s\",\n+\t\t\t eth_dev->data->name);\n+\t\tgoto init_hwif_fail;\n+\t}\n+\n+\t/* init_cfg_mgmt */\n+\trc = init_cfg_mgmt(nic_dev->hwdev);\n+\tif (rc) {\n+\t\tPMD_DRV_LOG(ERR, \"Initialize cfg_mgmt failed, dev_name: %s\",\n+\t\t\t eth_dev->data->name);\n+\t\tgoto init_cfgmgnt_fail;\n+\t}\n+\n+\t/* init_aeqs */\n+\trc = hinic_comm_aeqs_init(nic_dev);\n+\tif (rc) {\n+\t\tPMD_DRV_LOG(ERR, \"Initialize aeqs failed, dev_name: %s\",\n+\t\t\t eth_dev->data->name);\n+\t\tgoto init_aeqs_fail;\n+\t}\n+\n+\t/* init_pf_to_mgnt */\n+\trc = hinic_comm_pf_to_mgmt_init(nic_dev);\n+\tif (rc) {\n+\t\tPMD_DRV_LOG(ERR, \"Initialize pf_to_mgmt failed, dev_name: %s\",\n+\t\t\t eth_dev->data->name);\n+\t\tgoto init_pf_to_mgmt_fail;\n+\t}\n+\n+\trc = hinic_card_workmode_check(nic_dev);\n+\tif (rc) {\n+\t\tPMD_DRV_LOG(ERR, \"Check card workmode failed, dev_name: %s\",\n+\t\t\t eth_dev->data->name);\n+\t\tgoto workmode_check_fail;\n+\t}\n+\n+\t/* do l2nic reset to make chip clear */\n+\trc = hinic_l2nic_reset(nic_dev->hwdev);\n+\tif (rc) {\n+\t\tPMD_DRV_LOG(ERR, \"Do l2nic reset failed, dev_name: %s\",\n+\t\t\t eth_dev->data->name);\n+\t\tgoto l2nic_reset_fail;\n+\t}\n+\n+\t/* init dma and aeq msix attribute table */\n+\t(void)hinic_init_attr_table(nic_dev->hwdev);\n+\n+\t/* init_cmdqs */\n+\trc = hinic_comm_cmdqs_init(nic_dev->hwdev);\n+\tif (rc) {\n+\t\tPMD_DRV_LOG(ERR, \"Initialize cmdq failed, dev_name: %s\",\n+\t\t\t eth_dev->data->name);\n+\t\tgoto init_cmdq_fail;\n+\t}\n+\n+\t/* set hardware state active */\n+\trc = hinic_activate_hwdev_state(nic_dev->hwdev);\n+\tif (rc) {\n+\t\tPMD_DRV_LOG(ERR, \"Initialize resources state failed, dev_name: %s\",\n+\t\t\t eth_dev->data->name);\n+\t\tgoto init_resources_state_fail;\n+\t}\n+\n+\t/* init_capability */\n+\trc = hinic_init_capability(nic_dev);\n+\tif (rc) {\n+\t\tPMD_DRV_LOG(ERR, \"Initialize capability failed, dev_name: %s\",\n+\t\t\t eth_dev->data->name);\n+\t\tgoto init_cap_fail;\n+\t}\n+\n+\t/* init root cla and function table */\n+\trc = hinic_init_nicio(nic_dev);\n+\tif (rc) {\n+\t\tPMD_DRV_LOG(ERR, \"Initialize nic_io failed, dev_name: %s\",\n+\t\t\t eth_dev->data->name);\n+\t\tgoto init_nicio_fail;\n+\t}\n+\n+\t/* init_software_txrxq */\n+\trc = hinic_init_sw_rxtxqs(nic_dev);\n+\tif (rc) {\n+\t\tPMD_DRV_LOG(ERR, \"Initialize sw_rxtxqs failed, dev_name: %s\",\n+\t\t\t eth_dev->data->name);\n+\t\tgoto init_sw_rxtxqs_fail;\n+\t}\n+\n+\trc = hinic_copy_mempool_init(nic_dev);\n+\tif (rc) {\n+\t\tPMD_DRV_LOG(ERR, \"Create copy mempool failed, dev_name: %s\",\n+\t\t\t eth_dev->data->name);\n+\t\tgoto init_mpool_fail;\n+\t}\n+\n+\t/* set hardware feature to default status */\n+\trc = hinic_set_default_hw_feature(nic_dev);\n+\tif (rc) {\n+\t\tPMD_DRV_LOG(ERR, \"Initialize hardware default features failed, dev_name: %s\",\n+\t\t\t eth_dev->data->name);\n+\t\tgoto set_default_hw_feature_fail;\n+\t}\n+\n+\treturn 0;\n+\n+set_default_hw_feature_fail:\n+\thinic_copy_mempool_uninit(nic_dev);\n+\n+init_mpool_fail:\n+\thinic_deinit_sw_rxtxqs(nic_dev);\n+\n+init_sw_rxtxqs_fail:\n+\thinic_deinit_nicio(nic_dev);\n+\n+init_nicio_fail:\n+init_cap_fail:\n+\thinic_deactivate_hwdev_state(nic_dev->hwdev);\n+\n+init_resources_state_fail:\n+\thinic_comm_cmdqs_free(nic_dev->hwdev);\n+\n+init_cmdq_fail:\n+l2nic_reset_fail:\n+workmode_check_fail:\n+\thinic_comm_pf_to_mgmt_free(nic_dev);\n+\n+init_pf_to_mgmt_fail:\n+\thinic_comm_aeqs_free(nic_dev);\n+\n+init_aeqs_fail:\n+\tfree_cfg_mgmt(nic_dev->hwdev);\n+\n+init_cfgmgnt_fail:\n+\thinic_hwif_res_free(nic_dev);\n+\n+init_hwif_fail:\n+\thinic_osdep_deinit(nic_dev);\n+\n+init_osdep_fail:\n+\trte_free(nic_dev->hwdev);\n+\tnic_dev->hwdev = NULL;\n+\n+\treturn rc;\n+}\n+\n+void hinic_nic_dev_destroy(struct rte_eth_dev *rte_dev)\n+{\n+\tstruct hinic_nic_dev *nic_dev =\n+\t\t\tHINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(rte_dev);\n+\n+\t(void)hinic_set_link_status_follow(nic_dev->hwdev,\n+\t\t\t\t\t HINIC_LINK_FOLLOW_DEFAULT);\n+\thinic_copy_mempool_uninit(nic_dev);\n+\thinic_deinit_sw_rxtxqs(nic_dev);\n+\thinic_deinit_nicio(nic_dev);\n+\thinic_deactivate_hwdev_state(nic_dev->hwdev);\n+\thinic_comm_cmdqs_free(nic_dev->hwdev);\n+\thinic_comm_pf_to_mgmt_free(nic_dev);\n+\thinic_comm_aeqs_free(nic_dev);\n+\tfree_cfg_mgmt(nic_dev->hwdev);\n+\thinic_hwif_res_free(nic_dev);\n+\thinic_osdep_deinit(nic_dev);\n+\n+\trte_free(nic_dev->hwdev);\n+\tnic_dev->hwdev = NULL;\n+}\ndiff --git a/drivers/net/hinic/hinic_pmd_ethdev.c b/drivers/net/hinic/hinic_pmd_ethdev.c\nnew file mode 100644\nindex 000000000..f19e457c1\n--- /dev/null\n+++ b/drivers/net/hinic/hinic_pmd_ethdev.c\n@@ -0,0 +1,25 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2017 Huawei Technologies Co., Ltd\n+ */\n+\n+#include <stdio.h>\n+#include <rte_pci.h>\n+#include <rte_bus_pci.h>\n+#include <rte_ethdev_pci.h>\n+#include <rte_mbuf.h>\n+#include <rte_malloc.h>\n+#include <rte_memcpy.h>\n+#include <rte_mempool.h>\n+#include <rte_dev.h>\n+#include <rte_errno.h>\n+#include <rte_kvargs.h>\n+\n+/** Driver-specific log messages type. */\n+int hinic_logtype;\n+\n+RTE_INIT(hinic_init_log)\n+{\n+\thinic_logtype = rte_log_register(\"pmd.net.hinic\");\n+\tif (hinic_logtype >= 0)\n+\t\trte_log_set_level(hinic_logtype, RTE_LOG_INFO);\n+}\ndiff --git a/drivers/net/hinic/meson.build b/drivers/net/hinic/meson.build\nnew file mode 100644\nindex 000000000..f55f5210e\n--- /dev/null\n+++ b/drivers/net/hinic/meson.build\n@@ -0,0 +1,18 @@\n+# SPDX-License-Identifier: BSD-3-Clause\n+# Copyright(c) 2017 Huawei Technologies Co., Ltd\n+\n+subdir('base')\n+objs = [base_objs]\n+\n+sources = files(\n+\t'hinic_pmd_dpdev.c',\n+\t'hinic_pmd_ethdev.c',\n+#\t'hinic_pmd_rx.c',\n+#\t'hinic_pmd_tx.c'\n+\t)\n+\n+deps += 'ethdev'\n+deps += 'pci'\n+deps += 'hash'\n+\n+includes += include_directories('base')\ndiff --git a/mk/rte.app.mk b/mk/rte.app.mk\nindex 7c9b4b538..afea28a58 100644\n--- a/mk/rte.app.mk\n+++ b/mk/rte.app.mk\n@@ -166,6 +166,7 @@ _LDLIBS-$(CONFIG_RTE_LIBRTE_ENETC_PMD) += -lrte_pmd_enetc\n _LDLIBS-$(CONFIG_RTE_LIBRTE_ENIC_PMD) += -lrte_pmd_enic\n _LDLIBS-$(CONFIG_RTE_LIBRTE_FM10K_PMD) += -lrte_pmd_fm10k\n _LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_FAILSAFE) += -lrte_pmd_failsafe\n+_LDLIBS-$(CONFIG_RTE_LIBRTE_HINIC_PMD) += -lrte_pmd_hinic\n _LDLIBS-$(CONFIG_RTE_LIBRTE_I40E_PMD) += -lrte_pmd_i40e\n _LDLIBS-$(CONFIG_RTE_LIBRTE_IAVF_PMD) += -lrte_pmd_iavf\n _LDLIBS-$(CONFIG_RTE_LIBRTE_ICE_PMD) += -lrte_pmd_ice\n", "prefixes": [ "v4", "08/11" ] }