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GET /api/patches/54452/?format=api
{ "id": 54452, "url": "http://patches.dpdk.org/api/patches/54452/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1559769660-363320-3-git-send-email-nicolas.chautru@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1559769660-363320-3-git-send-email-nicolas.chautru@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1559769660-363320-3-git-send-email-nicolas.chautru@intel.com", "date": "2019-06-05T21:20:59", "name": "[v2,2/3] doc/guides: documentation for the FPGA BBDEV PMD", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "d4d3f19ae720e0720aa5a5eda439a44e80169b40", "submitter": { "id": 1314, "url": "http://patches.dpdk.org/api/people/1314/?format=api", "name": "Chautru, Nicolas", "email": "nicolas.chautru@intel.com" }, "delegate": { "id": 6690, "url": "http://patches.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1559769660-363320-3-git-send-email-nicolas.chautru@intel.com/mbox/", "series": [ { "id": 4916, "url": "http://patches.dpdk.org/api/series/4916/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=4916", "date": "2019-06-05T21:20:57", "name": "baseband/fpga_lte_fec: adding driver for FEC on FPGA", "version": 2, "mbox": "http://patches.dpdk.org/series/4916/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/54452/comments/", "check": "fail", "checks": "http://patches.dpdk.org/api/patches/54452/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 1956C1B9D6;\n\tWed, 5 Jun 2019 23:22:01 +0200 (CEST)", "from mga04.intel.com (mga04.intel.com [192.55.52.120])\n\tby dpdk.org (Postfix) with ESMTP id E865A1B9BA\n\tfor <dev@dpdk.org>; Wed, 5 Jun 2019 23:21:57 +0200 (CEST)", "from orsmga001.jf.intel.com ([10.7.209.18])\n\tby fmsmga104.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t05 Jun 2019 14:21:56 -0700", "from skx-5gnr-sc12-1.sc.intel.com ([172.25.69.194])\n\tby orsmga001.jf.intel.com with ESMTP; 05 Jun 2019 14:21:56 -0700" ], "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "From": "Nicolas Chautru <nicolas.chautru@intel.com>", "To": "thomas@monjalon.net,\n\takhil.goyal@nxp.com,\n\tdev@dpdk.org", "Cc": "ferruh.yigit@intel.com, amr.mokhtar@intel.com,\n\tNicolas Chautru <nicolas.chautru@intel.com>", "Date": "Wed, 5 Jun 2019 14:20:59 -0700", "Message-Id": "<1559769660-363320-3-git-send-email-nicolas.chautru@intel.com>", "X-Mailer": "git-send-email 1.8.3.1", "In-Reply-To": "<1559769660-363320-1-git-send-email-nicolas.chautru@intel.com>", "References": "<1559756323-179855-2-git-send-email-nicolas.chautru@intel.com>\n\t<1559769660-363320-1-git-send-email-nicolas.chautru@intel.com>", "Subject": "[dpdk-dev] [PATCH v2 2/3] doc/guides: documentation for the FPGA\n\tBBDEV PMD", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Adding documentation related to the new PMD driver\nin previous commit\n\nSigned-off-by: Nicolas Chautru <nicolas.chautru@intel.com>\n---\n doc/guides/bbdevs/fpga_lte_fec.rst | 318 +++++++++++++++++++++++++++++++++++++\n doc/guides/bbdevs/index.rst | 1 +\n 2 files changed, 319 insertions(+)\n create mode 100644 doc/guides/bbdevs/fpga_lte_fec.rst", "diff": "diff --git a/doc/guides/bbdevs/fpga_lte_fec.rst b/doc/guides/bbdevs/fpga_lte_fec.rst\nnew file mode 100644\nindex 0000000..71b058c\n--- /dev/null\n+++ b/doc/guides/bbdevs/fpga_lte_fec.rst\n@@ -0,0 +1,318 @@\n+.. SPDX-License-Identifier: BSD-3-Clause\n+ Copyright(c) 2018 Intel Corporation\n+\n+Intel(R) FPGA LTE FEC Poll Mode Driver\n+======================================\n+\n+The BBDEV FPGA LTE FEC poll mode driver (PMD) supports an FPGA implementation of a VRAN\n+Turbo Encode / Decode LTE wireless acceleration function, using Intel's PCI-e and FPGA\n+based Vista Creek device.\n+\n+Features\n+--------\n+\n+FPGA LTE FEC PMD supports the following features:\n+\n+- Turbo Encode in the DL with total throughput of 4.5 Gbits/s\n+- Turbo Decode in the UL with total throughput of 1.5 Gbits/s assuming 8 decoder iterations\n+- 8 VFs per PF (physical device)\n+- Maximum of 32 UL queues per VF\n+- Maximum of 32 DL queues per VF\n+- PCIe Gen-3 x8 Interface\n+- MSI-X\n+- SR-IOV\n+\n+\n+FPGA LTE FEC PMD supports the following BBDEV capabilities:\n+\n+* For the turbo encode operation:\n+ - ``RTE_BBDEV_TURBO_CRC_24B_ATTACH`` : set to attach CRC24B to CB(s)\n+ - ``RTE_BBDEV_TURBO_RATE_MATCH`` : if set then do not do Rate Match bypass\n+ - ``RTE_BBDEV_TURBO_ENC_INTERRUPTS`` : set for encoder dequeue interrupts\n+\n+\n+* For the turbo decode operation:\n+ - ``RTE_BBDEV_TURBO_CRC_TYPE_24B`` : check CRC24B from CB(s)\n+ - ``RTE_BBDEV_TURBO_SUBBLOCK_DEINTERLEAVE`` : perform subblock de-interleave\n+ - ``RTE_BBDEV_TURBO_DEC_INTERRUPTS`` : set for decoder dequeue interrupts\n+ - ``RTE_BBDEV_TURBO_NEG_LLR_1_BIT_IN`` : set if negative LLR encoder i/p is supported\n+ - ``RTE_BBDEV_TURBO_DEC_TB_CRC_24B_KEEP`` : keep CRC24B bits appended while decoding\n+\n+\n+Limitations\n+-----------\n+\n+FPGA LTE FEC does not support the following:\n+\n+- Scatter-Gather function\n+\n+\n+Installation\n+--------------\n+\n+Section 3 of the DPDK manual provides instuctions on installing and compiling DPDK. The\n+default set of bbdev compile flags may be found in config/common_base, where for example\n+the flag to build the FPGA LTE FEC device, ``CONFIG_RTE_LIBRTE_PMD_FPGA_LTE_FEC``, is already\n+set. It is assumed DPDK has been compiled using for instance:\n+\n+.. code-block:: console\n+\n+ make install T=x86_64-native-linuxapp-gcc\n+\n+\n+DPDK requires hugepages to be configured as detailed in section 2 of the DPDK manual.\n+The bbdev test application has been tested with a configuration 40 x 1GB hugepages. The\n+hugepage configuration of a server may be examined using:\n+\n+.. code-block:: console\n+\n+ grep Huge* /proc/meminfo\n+\n+\n+Initialization\n+--------------\n+\n+When the device first powers up, its PCI Physical Functions (PF) can be listed through this command:\n+\n+.. code-block:: console\n+\n+ sudo lspci -vd1172:5052\n+\n+The physical and virtual functions are compatible with Linux UIO drivers:\n+``vfio`` and ``igb_uio``. However, in order to work the FPGA LTE FEC device firstly needs\n+to be bound to one of these linux drivers through DPDK.\n+\n+\n+Bind PF UIO driver(s)\n+~~~~~~~~~~~~~~~~~~~~~\n+\n+Install the DPDK igb_uio driver, bind it with the PF PCI device ID and use\n+``lspci`` to confirm the PF device is under use by ``igb_uio`` DPDK UIO driver.\n+\n+The igb_uio driver may be bound to the PF PCI device using one of three methods:\n+\n+\n+1. PCI functions (physical or virtual, depending on the use case) can be bound to\n+the UIO driver by repeating this command for every function.\n+\n+.. code-block:: console\n+\n+ cd <dpdk-top-level-directory>\n+ insmod ./build/kmod/igb_uio.ko\n+ echo \"1172 5052\" > /sys/bus/pci/drivers/igb_uio/new_id\n+ lspci -vd1172:\n+\n+\n+2. Another way to bind PF with DPDK UIO driver is by using the ``dpdk-devbind.py`` tool\n+\n+.. code-block:: console\n+\n+ cd <dpdk-top-level-directory>\n+ ./usertools/dpdk-devbind.py -b igb_uio 0000:06:00.0\n+\n+where the PCI device ID (example: 0000:06:00.0) is obtained using lspci -vd1172:\n+\n+\n+3. A third way to bind is to use ``dpdk-setup.sh`` tool\n+\n+.. code-block:: console\n+\n+ cd <dpdk-top-level-directory>\n+ ./usertools/dpdk-setup.sh\n+\n+ select 'Bind Ethernet/Crypto/Baseband device to IGB UIO module'\n+ or\n+ select 'Bind Ethernet/Crypto/Baseband device to VFIO module' depending on driver required\n+ enter PCI device ID\n+ select 'Display current Ethernet/Crypto/Baseband device settings' to confirm binding\n+\n+\n+In the same way the FPGA LTE FEC PF can be bound with vfio, but vfio driver does not\n+support SR-IOV configuration right out of the box, so it will need to be patched.\n+\n+\n+Enable Virtual Functions\n+~~~~~~~~~~~~~~~~~~~~~~~~\n+\n+Now, it should be visible in the printouts that PCI PF is under igb_uio control\n+\"``Kernel driver in use: igb_uio``\"\n+\n+To show the number of available VFs on the device, read ``sriov_totalvfs`` file..\n+\n+.. code-block:: console\n+\n+ cat /sys/bus/pci/devices/0000\\:<b>\\:<d>.<f>/sriov_totalvfs\n+\n+ where 0000\\:<b>\\:<d>.<f> is the PCI device ID\n+\n+\n+To enable VFs via igb_uio, echo the number of virtual functions intended to\n+enable to ``max_vfs`` file..\n+\n+.. code-block:: console\n+\n+ echo <num-of-vfs> > /sys/bus/pci/devices/0000\\:<b>\\:<d>.<f>/max_vfs\n+\n+\n+Afterwards, all VFs must be bound to appropriate UIO drivers as required, same\n+way it was done with the physical function previously.\n+\n+Enabling SR-IOV via vfio driver is pretty much the same, except that the file\n+name is different:\n+\n+.. code-block:: console\n+\n+ echo <num-of-vfs> > /sys/bus/pci/devices/0000\\:<b>\\:<d>.<f>/sriov_numvfs\n+\n+\n+Configure the VFs through PF\n+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n+\n+The PCI virtual functions must be configured before working or getting assigned\n+to VMs/Containers. The configuration involves allocating the number of hardware\n+queues, priorities, load balance, bandwidth and other settings necessary for the\n+device to perform FEC functions.\n+\n+This configuration needs to be executed at least once after reboot or PCI FLR and can\n+be achieved by using the function ``fpga_lte_fec_configure()``, which sets up the\n+parameters defined in ``fpga_lte_fec_conf`` structure:\n+\n+.. code-block:: c\n+\n+ struct fpga_lte_fec_conf {\n+ bool pf_mode_en;\n+ uint8_t vf_ul_queues_number[FPGA_LTE_FEC_NUM_VFS];\n+ uint8_t vf_dl_queues_number[FPGA_LTE_FEC_NUM_VFS];\n+ uint8_t ul_bandwidth;\n+ uint8_t dl_bandwidth;\n+ uint8_t ul_load_balance;\n+ uint8_t dl_load_balance;\n+ uint16_t flr_time_out;\n+ };\n+\n+- ``pf_mode_en``: identifies whether only PF is to be used, or the VFs. PF and\n+ VFs are mutually exclusive and cannot run simultaneously.\n+ Set to 1 for PF mode enabled.\n+ If PF mode is enabled all queues available in the device are assigned\n+ exclusively to PF and 0 queues given to VFs.\n+\n+- ``vf_*l_queues_number``: defines the hardware queue mapping for every VF.\n+\n+- ``*l_bandwidth``: in case of congestion on PCIe interface. The device\n+ allocates different bandwidth to UL and DL. The weight is configured by this\n+ setting. The unit of weight is 3 code blocks. For example, if the code block\n+ cbps (code block per second) ratio between UL and DL is 12:1, then the\n+ configuration value should be set to 36:3. The schedule algorithm is based\n+ on code block regardless the length of each block.\n+\n+- ``*l_load_balance``: hardware queues are load-balanced in a round-robin\n+ fashion. Queues get filled first-in first-out until they reach a pre-defined\n+ watermark level, if exceeded, they won't get assigned new code blocks..\n+ This watermark is defined by this setting.\n+\n+ If all hardware queues exceeds the watermark, no code blocks will be\n+ streamed in from UL/DL code block FIFO.\n+\n+- ``flr_time_out``: specifies how many 16.384us to be FLR time out. The\n+ time_out = flr_time_out x 16.384us. For instance, if you want to set 10ms for\n+ the FLR time out then set this setting to 0x262=610.\n+\n+\n+An example configuration code calling the function ``fpga_lte_fec_configure()`` is shown\n+below:\n+\n+.. code-block:: c\n+\n+ struct fpga_lte_fec_conf conf;\n+ unsigned int i;\n+\n+ memset(&conf, 0, sizeof(struct fpga_lte_fec_conf));\n+ conf.pf_mode_en = 1;\n+\n+ for (i = 0; i < FPGA_LTE_FEC_NUM_VFS; ++i) {\n+ conf.vf_ul_queues_number[i] = 4;\n+ conf.vf_dl_queues_number[i] = 4;\n+ }\n+ conf.ul_bandwidth = 12;\n+ conf.dl_bandwidth = 5;\n+ conf.dl_load_balance = 64;\n+ conf.ul_load_balance = 64;\n+\n+ /* setup FPGA PF */\n+ ret = fpga_lte_fec_configure(info->dev_name, &conf);\n+ TEST_ASSERT_SUCCESS(ret,\n+ \"Failed to configure 4G FPGA PF for bbdev %s\",\n+ info->dev_name);\n+\n+\n+Test Application\n+----------------\n+\n+BBDEV provides a test application, ``test-bbdev.py`` and range of test data for testing\n+the functionality of FPGA LTE FEC turbo encode and turbo decode, depending on the device's\n+capabilities. The test application is located under app->test-bbdev folder and has the\n+following options:\n+\n+.. code-block:: console\n+\n+ \"-p\", \"--testapp-path\": specifies path to the bbdev test app.\n+ \"-e\", \"--eal-params\"\t: EAL arguments which are passed to the test app.\n+ \"-t\", \"--timeout\"\t: Timeout in seconds (default=300).\n+ \"-c\", \"--test-cases\"\t: Defines test cases to run. Run all if not specified.\n+ \"-v\", \"--test-vector\"\t: Test vector path (default=dpdk_path+/app/test-bbdev/test_vectors/bbdev_null.data).\n+ \"-n\", \"--num-ops\"\t: Number of operations to process on device (default=32).\n+ \"-b\", \"--burst-size\"\t: Operations enqueue/dequeue burst size (default=32).\n+ \"-l\", \"--num-lcores\"\t: Number of lcores to run (default=16).\n+ \"-i\", \"--init-device\" : Initialise PF device with default values.\n+\n+\n+To execute the test application tool using simple turbo decode or turbo encode data,\n+type one of the following:\n+\n+.. code-block:: console\n+\n+ ./test-bbdev.py -c validation -n 64 -b 8 -v ./turbo_dec_default.data\n+ ./test-bbdev.py -c validation -n 64 -b 8 -v ./turbo_enc_default.data\n+\n+\n+The test application ``test-bbdev.py``, supports the ability to configure the PF device with\n+a default set of values, if the \"-i\" or \"- -init-device\" option is included. The default values\n+are defined in test_bbdev_perf.c as:\n+\n+- VF_UL_QUEUE_VALUE 4\n+- VF_DL_QUEUE_VALUE 4\n+- UL_BANDWIDTH 3\n+- DL_BANDWIDTH 3\n+- UL_LOAD_BALANCE 128\n+- DL_LOAD_BALANCE 128\n+- FLR_TIMEOUT 610\n+\n+\n+Test Vectors\n+~~~~~~~~~~~~\n+\n+In addition to the simple turbo decoder and turbo encoder tests, bbdev also provides\n+a range of additional tests under the test_vectors folder, which may be useful. The results\n+of these tests will depend on the FPGA LTE FEC capabilities:\n+\n+* turbo decoder tests:\n+ - ``turbo_dec_c1_k6144_r0_e10376_crc24b_sbd_negllr_high_snr.data``\n+ - ``turbo_dec_c1_k6144_r0_e10376_crc24b_sbd_negllr_low_snr.data``\n+ - ``turbo_dec_c1_k6144_r0_e34560_negllr.data``\n+ - ``turbo_dec_c1_k6144_r0_e34560_sbd_negllr.data``\n+ - ``turbo_dec_c2_k3136_r0_e4920_sbd_negllr_crc24b.data``\n+ - ``turbo_dec_c2_k3136_r0_e4920_sbd_negllr.data``\n+\n+\n+* turbo encoder tests:\n+ - ``turbo_enc_c1_k40_r0_e1190_rm.data``\n+ - ``turbo_enc_c1_k40_r0_e1194_rm.data``\n+ - ``turbo_enc_c1_k40_r0_e1196_rm.data``\n+ - ``turbo_enc_c1_k40_r0_e272_rm.data``\n+ - ``turbo_enc_c1_k6144_r0_e18444.data``\n+ - ``turbo_enc_c1_k6144_r0_e32256_crc24b_rm.data``\n+ - ``turbo_enc_c2_k5952_r0_e17868_crc24b.data``\n+ - ``turbo_enc_c3_k4800_r2_e14412_crc24b.data``\n+ - ``turbo_enc_c4_k4800_r2_e14412_crc24b.data``\n+\n+\ndiff --git a/doc/guides/bbdevs/index.rst b/doc/guides/bbdevs/index.rst\nindex 93276ed..005b95e 100644\n--- a/doc/guides/bbdevs/index.rst\n+++ b/doc/guides/bbdevs/index.rst\n@@ -10,3 +10,4 @@ Baseband Device Drivers\n \n null\n turbo_sw\n+ fpga_lte_fec\n", "prefixes": [ "v2", "2/3" ] }