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GET /api/patches/54304/?format=api
{ "id": 54304, "url": "http://patches.dpdk.org/api/patches/54304/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20190604054248.68510-29-leyi.rong@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20190604054248.68510-29-leyi.rong@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20190604054248.68510-29-leyi.rong@intel.com", "date": "2019-06-04T05:42:27", "name": "[28/49] net/ice/base: add some minor features", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "6c32fa5a76e0a5f3adc86536e28ef34a26967179", "submitter": { "id": 1204, "url": "http://patches.dpdk.org/api/people/1204/?format=api", "name": "Leyi Rong", "email": "leyi.rong@intel.com" }, "delegate": { "id": 1540, "url": "http://patches.dpdk.org/api/users/1540/?format=api", "username": "qzhan15", "first_name": "Qi", "last_name": "Zhang", "email": "qi.z.zhang@intel.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20190604054248.68510-29-leyi.rong@intel.com/mbox/", "series": [ { "id": 4879, "url": "http://patches.dpdk.org/api/series/4879/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=4879", "date": "2019-06-04T05:41:59", "name": "shared code update", "version": 1, "mbox": "http://patches.dpdk.org/series/4879/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/54304/comments/", "check": "fail", "checks": "http://patches.dpdk.org/api/patches/54304/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 9847C1BBD8;\n\tTue, 4 Jun 2019 07:45:09 +0200 (CEST)", "from mga04.intel.com (mga04.intel.com [192.55.52.120])\n\tby dpdk.org (Postfix) with ESMTP id 825F91BB06\n\tfor <dev@dpdk.org>; Tue, 4 Jun 2019 07:44:24 +0200 (CEST)", "from fmsmga008.fm.intel.com ([10.253.24.58])\n\tby fmsmga104.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t03 Jun 2019 22:44:23 -0700", "from lrong-srv-03.sh.intel.com ([10.67.119.177])\n\tby fmsmga008.fm.intel.com with ESMTP; 03 Jun 2019 22:44:23 -0700" ], "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "From": "Leyi Rong <leyi.rong@intel.com>", "To": "qi.z.zhang@intel.com", "Cc": "dev@dpdk.org, Leyi Rong <leyi.rong@intel.com>,\n\tPaul M Stillwell Jr <paul.m.stillwell.jr@intel.com>", "Date": "Tue, 4 Jun 2019 13:42:27 +0800", "Message-Id": "<20190604054248.68510-29-leyi.rong@intel.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20190604054248.68510-1-leyi.rong@intel.com>", "References": "<20190604054248.68510-1-leyi.rong@intel.com>", "Subject": "[dpdk-dev] [PATCH 28/49] net/ice/base: add some minor features", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "1. Disable TX pacing option.\n2. Use a different ICE_DBG bit for firmware log messages.\n3. Always set prefena when configuring a RX queue.\n4. make FDID available for FlexDescriptor.\n\nSigned-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>\nSigned-off-by: Leyi Rong <leyi.rong@intel.com>\n---\n drivers/net/ice/base/ice_common.c | 44 +++++++++++++---------------\n drivers/net/ice/base/ice_fdir.c | 2 +-\n drivers/net/ice/base/ice_lan_tx_rx.h | 3 +-\n drivers/net/ice/base/ice_type.h | 2 +-\n 4 files changed, 25 insertions(+), 26 deletions(-)", "diff": "diff --git a/drivers/net/ice/base/ice_common.c b/drivers/net/ice/base/ice_common.c\nindex 6e5a60a38..89c922bed 100644\n--- a/drivers/net/ice/base/ice_common.c\n+++ b/drivers/net/ice/base/ice_common.c\n@@ -449,11 +449,7 @@ ice_aq_set_mac_cfg(struct ice_hw *hw, u16 max_frame_size, struct ice_sq_cd *cd)\n {\n \tu16 fc_threshold_val, tx_timer_val;\n \tstruct ice_aqc_set_mac_cfg *cmd;\n-\tstruct ice_port_info *pi;\n \tstruct ice_aq_desc desc;\n-\tenum ice_status status;\n-\tu8 port_num = 0;\n-\tbool link_up;\n \tu32 reg_val;\n \n \tcmd = &desc.params.set_mac_cfg;\n@@ -465,21 +461,6 @@ ice_aq_set_mac_cfg(struct ice_hw *hw, u16 max_frame_size, struct ice_sq_cd *cd)\n \n \tcmd->max_frame_size = CPU_TO_LE16(max_frame_size);\n \n-\t/* Retrieve the current data_pacing value in FW*/\n-\tpi = &hw->port_info[port_num];\n-\n-\t/* We turn on the get_link_info so that ice_update_link_info(...)\n-\t * can be called.\n-\t */\n-\tpi->phy.get_link_info = 1;\n-\n-\tstatus = ice_get_link_status(pi, &link_up);\n-\n-\tif (status)\n-\t\treturn status;\n-\n-\tcmd->params = pi->phy.link_info.pacing;\n-\n \t/* We read back the transmit timer and fc threshold value of\n \t * LFC. Thus, we will use index =\n \t * PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_MAX_INDEX.\n@@ -544,7 +525,15 @@ static void ice_cleanup_fltr_mgmt_struct(struct ice_hw *hw)\n \t}\n \trecps = hw->switch_info->recp_list;\n \tfor (i = 0; i < ICE_MAX_NUM_RECIPES; i++) {\n+\t\tstruct ice_recp_grp_entry *rg_entry, *tmprg_entry;\n+\n \t\trecps[i].root_rid = i;\n+\t\tLIST_FOR_EACH_ENTRY_SAFE(rg_entry, tmprg_entry,\n+\t\t\t\t\t &recps[i].rg_list, ice_recp_grp_entry,\n+\t\t\t\t\t l_entry) {\n+\t\t\tLIST_DEL(&rg_entry->l_entry);\n+\t\t\tice_free(hw, rg_entry);\n+\t\t}\n \n \t\tif (recps[i].adv_rule) {\n \t\t\tstruct ice_adv_fltr_mgmt_list_entry *tmp_entry;\n@@ -571,6 +560,8 @@ static void ice_cleanup_fltr_mgmt_struct(struct ice_hw *hw)\n \t\t\t\tice_free(hw, lst_itr);\n \t\t\t}\n \t\t}\n+\t\tif (recps[i].root_buf)\n+\t\t\tice_free(hw, recps[i].root_buf);\n \t}\n \tice_rm_all_sw_replay_rule_info(hw);\n \tice_free(hw, sw->recp_list);\n@@ -789,10 +780,10 @@ static enum ice_status ice_cfg_fw_log(struct ice_hw *hw, bool enable)\n */\n void ice_output_fw_log(struct ice_hw *hw, struct ice_aq_desc *desc, void *buf)\n {\n-\tice_debug(hw, ICE_DBG_AQ_MSG, \"[ FW Log Msg Start ]\\n\");\n-\tice_debug_array(hw, ICE_DBG_AQ_MSG, 16, 1, (u8 *)buf,\n+\tice_debug(hw, ICE_DBG_FW_LOG, \"[ FW Log Msg Start ]\\n\");\n+\tice_debug_array(hw, ICE_DBG_FW_LOG, 16, 1, (u8 *)buf,\n \t\t\tLE16_TO_CPU(desc->datalen));\n-\tice_debug(hw, ICE_DBG_AQ_MSG, \"[ FW Log Msg End ]\\n\");\n+\tice_debug(hw, ICE_DBG_FW_LOG, \"[ FW Log Msg End ]\\n\");\n }\n \n /**\n@@ -1213,6 +1204,7 @@ static const struct ice_ctx_ele ice_rlan_ctx_info[] = {\n \tICE_CTX_STORE(ice_rlan_ctx, tphdata_ena,\t1,\t195),\n \tICE_CTX_STORE(ice_rlan_ctx, tphhead_ena,\t1,\t196),\n \tICE_CTX_STORE(ice_rlan_ctx, lrxqthresh,\t\t3,\t198),\n+\tICE_CTX_STORE(ice_rlan_ctx, prefena,\t\t1,\t201),\n \t{ 0 }\n };\n \n@@ -1223,7 +1215,8 @@ static const struct ice_ctx_ele ice_rlan_ctx_info[] = {\n * @rxq_index: the index of the Rx queue\n *\n * Converts rxq context from sparse to dense structure and then writes\n- * it to HW register space\n+ * it to HW register space and enables the hardware to prefetch descriptors\n+ * instead of only fetching them on demand\n */\n enum ice_status\n ice_write_rxq_ctx(struct ice_hw *hw, struct ice_rlan_ctx *rlan_ctx,\n@@ -1231,6 +1224,11 @@ ice_write_rxq_ctx(struct ice_hw *hw, struct ice_rlan_ctx *rlan_ctx,\n {\n \tu8 ctx_buf[ICE_RXQ_CTX_SZ] = { 0 };\n \n+\tif (!rlan_ctx)\n+\t\treturn ICE_ERR_BAD_PTR;\n+\n+\trlan_ctx->prefena = 1;\n+\n \tice_set_ctx((u8 *)rlan_ctx, ctx_buf, ice_rlan_ctx_info);\n \treturn ice_copy_rxq_ctx_to_hw(hw, ctx_buf, rxq_index);\n }\ndiff --git a/drivers/net/ice/base/ice_fdir.c b/drivers/net/ice/base/ice_fdir.c\nindex 4bc8e6dcb..bde676a8f 100644\n--- a/drivers/net/ice/base/ice_fdir.c\n+++ b/drivers/net/ice/base/ice_fdir.c\n@@ -186,7 +186,7 @@ ice_set_dflt_val_fd_desc(struct ice_fd_fltr_desc_ctx *fd_fltr_ctx)\n \tfd_fltr_ctx->desc_prof_prio = ICE_FXD_FLTR_QW1_PROF_PRIO_ZERO;\n \tfd_fltr_ctx->desc_prof = ICE_FXD_FLTR_QW1_PROF_ZERO;\n \tfd_fltr_ctx->swap = ICE_FXD_FLTR_QW1_SWAP_SET;\n-\tfd_fltr_ctx->fdid_prio = ICE_FXD_FLTR_QW1_FDID_PRI_ZERO;\n+\tfd_fltr_ctx->fdid_prio = ICE_FXD_FLTR_QW1_FDID_PRI_ONE;\n \tfd_fltr_ctx->fdid_mdid = ICE_FXD_FLTR_QW1_FDID_MDID_FD;\n \tfd_fltr_ctx->fdid = ICE_FXD_FLTR_QW1_FDID_ZERO;\n }\ndiff --git a/drivers/net/ice/base/ice_lan_tx_rx.h b/drivers/net/ice/base/ice_lan_tx_rx.h\nindex 8c9902994..fa2309bf1 100644\n--- a/drivers/net/ice/base/ice_lan_tx_rx.h\n+++ b/drivers/net/ice/base/ice_lan_tx_rx.h\n@@ -162,7 +162,7 @@ struct ice_fltr_desc {\n \n #define ICE_FXD_FLTR_QW1_FDID_PRI_S\t25\n #define ICE_FXD_FLTR_QW1_FDID_PRI_M\t(0x7ULL << ICE_FXD_FLTR_QW1_FDID_PRI_S)\n-#define ICE_FXD_FLTR_QW1_FDID_PRI_ZERO\t0x0ULL\n+#define ICE_FXD_FLTR_QW1_FDID_PRI_ONE\t0x1ULL\n \n #define ICE_FXD_FLTR_QW1_FDID_MDID_S\t28\n #define ICE_FXD_FLTR_QW1_FDID_MDID_M\t(0xFULL << ICE_FXD_FLTR_QW1_FDID_MDID_S)\n@@ -807,6 +807,7 @@ struct ice_rlan_ctx {\n \tu8 tphdata_ena;\n \tu8 tphhead_ena;\n \tu16 lrxqthresh; /* bigger than needed, see above for reason */\n+\tu8 prefena;\t/* NOTE: normally must be set to 1 at init */\n };\n \n struct ice_ctx_ele {\ndiff --git a/drivers/net/ice/base/ice_type.h b/drivers/net/ice/base/ice_type.h\nindex 477f34595..116cfe647 100644\n--- a/drivers/net/ice/base/ice_type.h\n+++ b/drivers/net/ice/base/ice_type.h\n@@ -82,7 +82,7 @@ static inline u32 ice_round_to_num(u32 N, u32 R)\n /* debug masks - set these bits in hw->debug_mask to control output */\n #define ICE_DBG_INIT\t\tBIT_ULL(1)\n #define ICE_DBG_RELEASE\t\tBIT_ULL(2)\n-\n+#define ICE_DBG_FW_LOG\t\tBIT_ULL(3)\n #define ICE_DBG_LINK\t\tBIT_ULL(4)\n #define ICE_DBG_PHY\t\tBIT_ULL(5)\n #define ICE_DBG_QCTX\t\tBIT_ULL(6)\n", "prefixes": [ "28/49" ] }