get:
Show a patch.

patch:
Update a patch.

put:
Update a patch.

GET /api/patches/54149/?format=api
HTTP 200 OK
Allow: GET, PUT, PATCH, HEAD, OPTIONS
Content-Type: application/json
Vary: Accept

{
    "id": 54149,
    "url": "http://patches.dpdk.org/api/patches/54149/?format=api",
    "web_url": "http://patches.dpdk.org/project/dpdk/patch/20190603093156.381-5-pbhagavatula@marvell.com/",
    "project": {
        "id": 1,
        "url": "http://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<20190603093156.381-5-pbhagavatula@marvell.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/20190603093156.381-5-pbhagavatula@marvell.com",
    "date": "2019-06-03T09:31:54",
    "name": "[4/5] event/octeontx2: add Tx adadpter support",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": true,
    "hash": "27fcc1c4ccbfcfccfeca0130694f51ad1f8c24ea",
    "submitter": {
        "id": 1183,
        "url": "http://patches.dpdk.org/api/people/1183/?format=api",
        "name": "Pavan Nikhilesh Bhagavatula",
        "email": "pbhagavatula@marvell.com"
    },
    "delegate": null,
    "mbox": "http://patches.dpdk.org/project/dpdk/patch/20190603093156.381-5-pbhagavatula@marvell.com/mbox/",
    "series": [
        {
            "id": 4858,
            "url": "http://patches.dpdk.org/api/series/4858/?format=api",
            "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=4858",
            "date": "2019-06-03T09:31:50",
            "name": "event/octeontx2: add Rx/Tx adapter support",
            "version": 1,
            "mbox": "http://patches.dpdk.org/series/4858/mbox/"
        }
    ],
    "comments": "http://patches.dpdk.org/api/patches/54149/comments/",
    "check": "fail",
    "checks": "http://patches.dpdk.org/api/patches/54149/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@dpdk.org",
        "Delivered-To": "patchwork@dpdk.org",
        "Received": [
            "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id AE80A1B96E;\n\tMon,  3 Jun 2019 11:32:12 +0200 (CEST)",
            "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n\t[67.231.148.174]) by dpdk.org (Postfix) with ESMTP id 9B6461B955\n\tfor <dev@dpdk.org>; Mon,  3 Jun 2019 11:32:10 +0200 (CEST)",
            "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n\tby mx0a-0016f401.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id\n\tx539VAiT007375 for <dev@dpdk.org>; Mon, 3 Jun 2019 02:32:09 -0700",
            "from sc-exch04.marvell.com ([199.233.58.184])\n\tby mx0a-0016f401.pphosted.com with ESMTP id 2supqm075a-1\n\t(version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n\tfor <dev@dpdk.org>; Mon, 03 Jun 2019 02:32:09 -0700",
            "from SC-EXCH01.marvell.com (10.93.176.81) by SC-EXCH04.marvell.com\n\t(10.93.176.84) with Microsoft SMTP Server (TLS) id 15.0.1367.3;\n\tMon, 3 Jun 2019 02:32:09 -0700",
            "from maili.marvell.com (10.93.176.43) by SC-EXCH01.marvell.com\n\t(10.93.176.81) with Microsoft SMTP Server id 15.0.1367.3 via Frontend\n\tTransport; Mon, 3 Jun 2019 02:32:09 -0700",
            "from BG-LT7430.marvell.com (bg-lt7430.marvell.com [10.28.20.231])\n\tby maili.marvell.com (Postfix) with ESMTP id D0FB23F7043;\n\tMon,  3 Jun 2019 02:32:07 -0700 (PDT)"
        ],
        "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n\th=from : to : cc :\n\tsubject : date : message-id : in-reply-to : references : mime-version\n\t: content-transfer-encoding : content-type; s=pfpt0818;\n\tbh=Gv8JH+62OKkIzb4GtlJly4np5NB9BMrFRJxjw8e7Oc0=;\n\tb=LOVzKUtWM7CngSnmXGcVnGJAyUe9ElrqSMUYHHYoyIzQucPnQUBbhxp6mtPfi/zbOUP4\n\tTk834IGgb8rxXVt/BOMs+8/yzFtFOLI0UwAeKPgQR5VHJKYTex2oP0AlXGs9+O/8VXBX\n\t5d+HoE7XxJi/kj2xaa0E9IVxi/Dh1Jp7yVF9kafW9UyEn6ipeHnASRo8QOIGNnDaDxIf\n\t23g3IYNHVzIBabP22R8ia84wY6/gkrSzgxLIuAHG5E2Fgz31v8/sPX/Z2ufJ3WDvrQcq\n\ta9pfzwHT43q1MGI8HzczFd6maMWskRvBpOY6bta+idzv0rMck4gbbB5ezb2uHxBIvlxD\n\tNg== ",
        "From": "<pbhagavatula@marvell.com>",
        "To": "<jerinj@marvell.com>, Pavan Nikhilesh <pbhagavatula@marvell.com>",
        "CC": "<dev@dpdk.org>, Nithin Dabilpuram <ndabilpuram@marvell.com>",
        "Date": "Mon, 3 Jun 2019 15:01:54 +0530",
        "Message-ID": "<20190603093156.381-5-pbhagavatula@marvell.com>",
        "X-Mailer": "git-send-email 2.17.1",
        "In-Reply-To": "<20190603093156.381-1-pbhagavatula@marvell.com>",
        "References": "<20190603093156.381-1-pbhagavatula@marvell.com>",
        "MIME-Version": "1.0",
        "Content-Transfer-Encoding": "8bit",
        "Content-Type": "text/plain",
        "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:, ,\n\tdefinitions=2019-06-03_07:, , signatures=0",
        "Subject": "[dpdk-dev]  [PATCH 4/5] event/octeontx2: add Tx adadpter support",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.15",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "From: Pavan Nikhilesh <pbhagavatula@marvell.com>\n\nAdd event eth Tx adapter support to octeontx2 SSO.\n\nSigned-off-by: Jerin Jacob <jerinj@marvell.com>\nSigned-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>\nSigned-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>\n---\n drivers/event/octeontx2/otx2_evdev.c       | 78 ++++++++++++++++++++++\n drivers/event/octeontx2/otx2_evdev.h       | 26 ++++++++\n drivers/event/octeontx2/otx2_evdev_adptr.c | 32 +++++++++\n drivers/event/octeontx2/otx2_worker.c      | 29 ++++++++\n drivers/event/octeontx2/otx2_worker.h      | 68 +++++++++++++++++++\n drivers/event/octeontx2/otx2_worker_dual.c | 35 ++++++++++\n 6 files changed, 268 insertions(+)",
    "diff": "diff --git a/drivers/event/octeontx2/otx2_evdev.c b/drivers/event/octeontx2/otx2_evdev.c\nindex 138f4e4fa..4fdc02bf1 100644\n--- a/drivers/event/octeontx2/otx2_evdev.c\n+++ b/drivers/event/octeontx2/otx2_evdev.c\n@@ -168,6 +168,39 @@ SSO_RX_ADPTR_ENQ_FASTPATH_FUNC\n #undef R\n \t};\n \n+\t/* Tx modes */\n+\tconst event_tx_adapter_enqueue ssogws_tx_adptr_enq[2][2][2][2][2] = {\n+#define T(name, f4, f3, f2, f1, f0, sz, flags)\t\t\t\t\\\n+\t\t[f4][f3][f2][f1][f0] =  otx2_ssogws_tx_adptr_enq_ ## name,\n+SSO_TX_ADPTR_ENQ_FASTPATH_FUNC\n+#undef T\n+\t};\n+\n+\tconst event_tx_adapter_enqueue\n+\t\tssogws_tx_adptr_enq_seg[2][2][2][2][2] = {\n+#define T(name, f4, f3, f2, f1, f0, sz, flags)\t\t\t\t\\\n+\t\t[f4][f3][f2][f1][f0] =  otx2_ssogws_tx_adptr_enq_seg_ ## name,\n+SSO_TX_ADPTR_ENQ_FASTPATH_FUNC\n+#undef T\n+\t};\n+\n+\tconst event_tx_adapter_enqueue\n+\t\tssogws_dual_tx_adptr_enq[2][2][2][2][2] = {\n+#define T(name, f4, f3, f2, f1, f0, sz, flags)\t\t\t\t\\\n+\t\t[f4][f3][f2][f1][f0] =  otx2_ssogws_dual_tx_adptr_enq_ ## name,\n+SSO_TX_ADPTR_ENQ_FASTPATH_FUNC\n+#undef T\n+\t};\n+\n+\tconst event_tx_adapter_enqueue\n+\t\tssogws_dual_tx_adptr_enq_seg[2][2][2][2][2] = {\n+#define T(name, f4, f3, f2, f1, f0, sz, flags)\t\t\t\t\\\n+\t\t[f4][f3][f2][f1][f0] =\t\t\t\t\t\\\n+\t\t\totx2_ssogws_dual_tx_adptr_enq_seg_ ## name,\n+SSO_TX_ADPTR_ENQ_FASTPATH_FUNC\n+#undef T\n+\t};\n+\n \tevent_dev->enqueue\t\t\t= otx2_ssogws_enq;\n \tevent_dev->enqueue_burst\t\t= otx2_ssogws_enq_burst;\n \tevent_dev->enqueue_new_burst\t\t= otx2_ssogws_enq_new_burst;\n@@ -238,6 +271,23 @@ SSO_RX_ADPTR_ENQ_FASTPATH_FUNC\n \t\t}\n \t}\n \n+\tif (dev->tx_offloads & NIX_TX_MULTI_SEG_F) {\n+\t\t/* [TSMP] [MBUF_NOFF] [VLAN] [OL3_L4_CSUM] [L3_L4_CSUM] */\n+\t\tevent_dev->txa_enqueue = ssogws_tx_adptr_enq_seg\n+\t\t\t[!!(dev->tx_offloads & NIX_TX_OFFLOAD_TSTAMP_F)]\n+\t\t\t[!!(dev->tx_offloads & NIX_TX_OFFLOAD_MBUF_NOFF_F)]\n+\t\t\t[!!(dev->tx_offloads & NIX_TX_OFFLOAD_VLAN_QINQ_F)]\n+\t\t\t[!!(dev->tx_offloads & NIX_TX_OFFLOAD_OL3_OL4_CSUM_F)]\n+\t\t\t[!!(dev->tx_offloads & NIX_TX_OFFLOAD_L3_L4_CSUM_F)];\n+\t} else {\n+\t\tevent_dev->txa_enqueue = ssogws_tx_adptr_enq\n+\t\t\t[!!(dev->tx_offloads & NIX_TX_OFFLOAD_TSTAMP_F)]\n+\t\t\t[!!(dev->tx_offloads & NIX_TX_OFFLOAD_MBUF_NOFF_F)]\n+\t\t\t[!!(dev->tx_offloads & NIX_TX_OFFLOAD_VLAN_QINQ_F)]\n+\t\t\t[!!(dev->tx_offloads & NIX_TX_OFFLOAD_OL3_OL4_CSUM_F)]\n+\t\t\t[!!(dev->tx_offloads & NIX_TX_OFFLOAD_L3_L4_CSUM_F)];\n+\t}\n+\n \tif (dev->dual_ws) {\n \t\tevent_dev->enqueue\t\t= otx2_ssogws_dual_enq;\n \t\tevent_dev->enqueue_burst\t= otx2_ssogws_dual_enq_burst;\n@@ -352,6 +402,31 @@ SSO_RX_ADPTR_ENQ_FASTPATH_FUNC\n \t\t\t\t\t\t\tNIX_RX_OFFLOAD_RSS_F)];\n \t\t\t}\n \t\t}\n+\n+\t\tif (dev->tx_offloads & NIX_TX_MULTI_SEG_F) {\n+\t\t/* [TSMP] [MBUF_NOFF] [VLAN] [OL3_L4_CSUM] [L3_L4_CSUM] */\n+\t\t\tevent_dev->txa_enqueue = ssogws_dual_tx_adptr_enq_seg\n+\t\t\t\t[!!(dev->tx_offloads & NIX_TX_OFFLOAD_TSTAMP_F)]\n+\t\t\t\t[!!(dev->tx_offloads &\n+\t\t\t\t\t\tNIX_TX_OFFLOAD_MBUF_NOFF_F)]\n+\t\t\t\t[!!(dev->tx_offloads &\n+\t\t\t\t\t\tNIX_TX_OFFLOAD_VLAN_QINQ_F)]\n+\t\t\t\t[!!(dev->tx_offloads &\n+\t\t\t\t\t\tNIX_TX_OFFLOAD_OL3_OL4_CSUM_F)]\n+\t\t\t\t[!!(dev->tx_offloads &\n+\t\t\t\t\t\tNIX_TX_OFFLOAD_L3_L4_CSUM_F)];\n+\t\t} else {\n+\t\t\tevent_dev->txa_enqueue = ssogws_dual_tx_adptr_enq\n+\t\t\t\t[!!(dev->tx_offloads & NIX_TX_OFFLOAD_TSTAMP_F)]\n+\t\t\t\t[!!(dev->tx_offloads &\n+\t\t\t\t\t\tNIX_TX_OFFLOAD_MBUF_NOFF_F)]\n+\t\t\t\t[!!(dev->tx_offloads &\n+\t\t\t\t\t\tNIX_TX_OFFLOAD_VLAN_QINQ_F)]\n+\t\t\t\t[!!(dev->tx_offloads &\n+\t\t\t\t\t\tNIX_TX_OFFLOAD_OL3_OL4_CSUM_F)]\n+\t\t\t\t[!!(dev->tx_offloads &\n+\t\t\t\t\t\tNIX_TX_OFFLOAD_L3_L4_CSUM_F)];\n+\t\t}\n \t}\n \trte_mb();\n }\n@@ -1410,6 +1485,9 @@ static struct rte_eventdev_ops otx2_sso_ops = {\n \t.eth_rx_adapter_start = otx2_sso_rx_adapter_start,\n \t.eth_rx_adapter_stop = otx2_sso_rx_adapter_stop,\n \n+\t.eth_tx_adapter_caps_get = otx2_sso_tx_adapter_caps_get,\n+\t.eth_tx_adapter_queue_add = otx2_sso_tx_adapter_queue_add,\n+\n \t.timer_adapter_caps_get = otx2_tim_caps_get,\n \n \t.xstats_get       = otx2_sso_xstats_get,\ndiff --git a/drivers/event/octeontx2/otx2_evdev.h b/drivers/event/octeontx2/otx2_evdev.h\nindex dd493715b..0f0be341f 100644\n--- a/drivers/event/octeontx2/otx2_evdev.h\n+++ b/drivers/event/octeontx2/otx2_evdev.h\n@@ -8,6 +8,7 @@\n #include <rte_eventdev.h>\n #include <rte_eventdev_pmd.h>\n #include <rte_event_eth_rx_adapter.h>\n+#include <rte_event_eth_tx_adapter.h>\n \n #include \"otx2_common.h\"\n #include \"otx2_dev.h\"\n@@ -118,6 +119,7 @@ struct otx2_sso_evdev {\n \trte_iova_t fc_iova;\n \tstruct rte_mempool *xaq_pool;\n \tuint64_t rx_offloads;\n+\tuint64_t tx_offloads;\n \tuint16_t rx_adptr_pool_cnt;\n \tuint32_t adptr_xae_cnt;\n \tuint64_t *rx_adptr_pools;\n@@ -308,6 +310,22 @@ uint16_t otx2_ssogws_dual_deq_seg_timeout_burst_ ##name(void *port,\t       \\\n SSO_RX_ADPTR_ENQ_FASTPATH_FUNC\n #undef R\n \n+#define T(name, f4, f3, f2, f1, f0, sz, flags)\t\t\t\t     \\\n+uint16_t otx2_ssogws_tx_adptr_enq_ ## name(void *port, struct rte_event ev[],\\\n+\t\t\t\t\t   uint16_t nb_events);\t\t     \\\n+uint16_t otx2_ssogws_tx_adptr_enq_seg_ ## name(void *port,\t\t     \\\n+\t\t\t\t\t       struct rte_event ev[],\t     \\\n+\t\t\t\t\t       uint16_t nb_events);\t     \\\n+uint16_t otx2_ssogws_dual_tx_adptr_enq_ ## name(void *port,\t\t     \\\n+\t\t\t\t\t\tstruct rte_event ev[],\t     \\\n+\t\t\t\t\t\tuint16_t nb_events);\t     \\\n+uint16_t otx2_ssogws_dual_tx_adptr_enq_seg_ ## name(void *port,\t\t     \\\n+\t\t\t\t\t\t    struct rte_event ev[],   \\\n+\t\t\t\t\t\t    uint16_t nb_events);     \\\n+\n+SSO_TX_ADPTR_ENQ_FASTPATH_FUNC\n+#undef T\n+\n void sso_updt_xae_cnt(struct otx2_sso_evdev *dev, void *data,\n \t\t      uint32_t event_type);\n int sso_xae_reconfigure(struct rte_eventdev *event_dev);\n@@ -327,6 +345,14 @@ int otx2_sso_rx_adapter_start(const struct rte_eventdev *event_dev,\n \t\t\t      const struct rte_eth_dev *eth_dev);\n int otx2_sso_rx_adapter_stop(const struct rte_eventdev *event_dev,\n \t\t\t     const struct rte_eth_dev *eth_dev);\n+int otx2_sso_tx_adapter_caps_get(const struct rte_eventdev *dev,\n+\t\t\t\t const struct rte_eth_dev *eth_dev,\n+\t\t\t\t uint32_t *caps);\n+int otx2_sso_tx_adapter_queue_add(uint8_t id,\n+\t\t\t\t  const struct rte_eventdev *event_dev,\n+\t\t\t\t  const struct rte_eth_dev *eth_dev,\n+\t\t\t\t  int32_t tx_queue_id);\n+\n /* Clean up API's */\n typedef void (*otx2_handle_event_t)(void *arg, struct rte_event ev);\n void ssogws_flush_events(struct otx2_ssogws *ws, uint8_t queue_id,\ndiff --git a/drivers/event/octeontx2/otx2_evdev_adptr.c b/drivers/event/octeontx2/otx2_evdev_adptr.c\nindex c2cf4196e..62ae5b61c 100644\n--- a/drivers/event/octeontx2/otx2_evdev_adptr.c\n+++ b/drivers/event/octeontx2/otx2_evdev_adptr.c\n@@ -327,3 +327,35 @@ otx2_sso_rx_adapter_stop(const struct rte_eventdev *event_dev,\n \n \treturn 0;\n }\n+\n+int\n+otx2_sso_tx_adapter_caps_get(const struct rte_eventdev *dev,\n+\t\t\t     const struct rte_eth_dev *eth_dev, uint32_t *caps)\n+{\n+\tint ret;\n+\n+\tRTE_SET_USED(dev);\n+\tret = strncmp(eth_dev->device->driver->name, \"net_octeontx2,\", 13);\n+\tif (ret)\n+\t\t*caps = 0;\n+\telse\n+\t\t*caps = RTE_EVENT_ETH_TX_ADAPTER_CAP_INTERNAL_PORT;\n+\n+\treturn 0;\n+}\n+\n+int\n+otx2_sso_tx_adapter_queue_add(uint8_t id, const struct rte_eventdev *event_dev,\n+\t\t\t      const struct rte_eth_dev *eth_dev,\n+\t\t\t      int32_t tx_queue_id)\n+{\n+\tstruct otx2_eth_dev *otx2_eth_dev = eth_dev->data->dev_private;\n+\tstruct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);\n+\n+\tRTE_SET_USED(id);\n+\tRTE_SET_USED(tx_queue_id);\n+\tdev->tx_offloads |= otx2_eth_dev->tx_offload_flags;\n+\tsso_fastpath_fns_set((struct rte_eventdev *)(uintptr_t)event_dev);\n+\n+\treturn 0;\n+}\ndiff --git a/drivers/event/octeontx2/otx2_worker.c b/drivers/event/octeontx2/otx2_worker.c\nindex ea2d0b5a4..cd14cd3d2 100644\n--- a/drivers/event/octeontx2/otx2_worker.c\n+++ b/drivers/event/octeontx2/otx2_worker.c\n@@ -267,6 +267,35 @@ otx2_ssogws_enq_fwd_burst(void *port, const struct rte_event ev[],\n \treturn 1;\n }\n \n+#define T(name, f4, f3, f2, f1, f0, sz, flags)\t\t\t\t\\\n+uint16_t __hot\t\t\t\t\t\t\t\t\\\n+otx2_ssogws_tx_adptr_enq_ ## name(void *port, struct rte_event ev[],\t\\\n+\t\t\t\t  uint16_t nb_events)\t\t\t\\\n+{\t\t\t\t\t\t\t\t\t\\\n+\tstruct otx2_ssogws *ws = port;\t\t\t\t\t\\\n+\tuint64_t cmd[sz];\t\t\t\t\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\tRTE_SET_USED(nb_events);\t\t\t\t\t\\\n+\treturn otx2_ssogws_event_tx(ws, ev, cmd, flags);\t\t\\\n+}\n+SSO_TX_ADPTR_ENQ_FASTPATH_FUNC\n+#undef T\n+\n+#define T(name, f4, f3, f2, f1, f0, sz, flags)\t\t\t\t\\\n+uint16_t __hot\t\t\t\t\t\t\t\t\\\n+otx2_ssogws_tx_adptr_enq_seg_ ## name(void *port, struct rte_event ev[],\\\n+\t\t\t\t      uint16_t nb_events)\t\t\\\n+{\t\t\t\t\t\t\t\t\t\\\n+\tstruct otx2_ssogws *ws = port;\t\t\t\t\t\\\n+\tuint64_t cmd[(sz) + NIX_TX_MSEG_SG_DWORDS - 2];\t\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\tRTE_SET_USED(nb_events);\t\t\t\t\t\\\n+\treturn otx2_ssogws_event_tx(ws, ev, cmd, (flags) |\t\t\\\n+\t\t\t\t    NIX_TX_MULTI_SEG_F);\t\t\\\n+}\n+SSO_TX_ADPTR_ENQ_FASTPATH_FUNC\n+#undef T\n+\n void\n ssogws_flush_events(struct otx2_ssogws *ws, uint8_t queue_id, uintptr_t base,\n \t\t    otx2_handle_event_t fn, void *arg)\ndiff --git a/drivers/event/octeontx2/otx2_worker.h b/drivers/event/octeontx2/otx2_worker.h\nindex 9d116f1ac..9c13cb1f0 100644\n--- a/drivers/event/octeontx2/otx2_worker.h\n+++ b/drivers/event/octeontx2/otx2_worker.h\n@@ -218,4 +218,72 @@ otx2_ssogws_swtag_wait(struct otx2_ssogws *ws)\n #endif\n }\n \n+static __rte_always_inline void\n+otx2_ssogws_head_wait(struct otx2_ssogws *ws)\n+{\n+\twhile (!(otx2_read64(ws->tag_op) & BIT_ULL(35)))\n+\t\t;\n+}\n+\n+static __rte_always_inline const struct otx2_eth_txq *\n+otx2_ssogws_xtract_meta(struct rte_mbuf *m)\n+{\n+\treturn rte_eth_devices[m->port].data->tx_queues[\n+\t\t\trte_event_eth_tx_adapter_txq_get(m)];\n+}\n+\n+static __rte_always_inline void\n+otx2_ssogws_prepare_pkt(const struct otx2_eth_txq *txq, struct rte_mbuf *m,\n+\t\t\tuint64_t *cmd, const uint32_t flags)\n+{\n+\totx2_lmt_mov(cmd, txq->cmd, otx2_nix_tx_ext_subs(flags));\n+\totx2_nix_xmit_prepare(m, cmd, flags);\n+}\n+\n+static __rte_always_inline uint16_t\n+otx2_ssogws_event_tx(struct otx2_ssogws *ws, struct rte_event ev[],\n+\t\t     uint64_t *cmd, const uint32_t flags)\n+{\n+\tconst struct otx2_eth_txq *txq = NULL;\n+\tstruct rte_mbuf *m = ev[0].mbuf;\n+\tuint16_t segdw;\n+\n+\trte_prefetch_non_temporal(m);\n+\n+\tswitch (ev->sched_type) {\n+\tcase SSO_SYNC_ORDERED:\n+\t\trte_cio_wmb();\n+\t\ttxq = otx2_ssogws_xtract_meta(m);\n+\t\totx2_ssogws_prepare_pkt(txq, m, cmd, flags);\n+\t\totx2_ssogws_head_wait(ws);\n+\t\tbreak;\n+\tcase SSO_SYNC_UNTAGGED:\n+\t\totx2_ssogws_swtag_norm(ws, ev->event, SSO_SYNC_ATOMIC);\n+\t\trte_cio_wmb();\n+\t\ttxq = otx2_ssogws_xtract_meta(m);\n+\t\totx2_ssogws_prepare_pkt(txq, m, cmd, flags);\n+\t\totx2_ssogws_swtag_wait(ws);\n+\t\tbreak;\n+\tcase SSO_SYNC_ATOMIC:\n+\t\trte_cio_wmb();\n+\t\ttxq = otx2_ssogws_xtract_meta(m);\n+\t\totx2_ssogws_prepare_pkt(txq, m, cmd, flags);\n+\t\tbreak;\n+\t}\n+\n+\tif (flags & NIX_TX_MULTI_SEG_F) {\n+\t\tsegdw = otx2_nix_prepare_mseg(m, cmd, flags);\n+\t\totx2_nix_xmit_prepare_tstamp(cmd, &txq->cmd[0],\n+\t\t\t\t\t     m->ol_flags, segdw, flags);\n+\t\totx2_nix_xmit_mseg_one(cmd, txq->lmt_addr, txq->io_addr, segdw);\n+\t} else {\n+\t\t/* Passing no of segdw as 4: HDR + EXT + SG + SMEM */\n+\t\totx2_nix_xmit_prepare_tstamp(cmd, &txq->cmd[0],\n+\t\t\t\t\t     m->ol_flags, 4, flags);\n+\t\totx2_nix_xmit_one(cmd, txq->lmt_addr, txq->io_addr, flags);\n+\t}\n+\n+\treturn 1;\n+}\n+\n #endif\ndiff --git a/drivers/event/octeontx2/otx2_worker_dual.c b/drivers/event/octeontx2/otx2_worker_dual.c\nindex cbe03c1bb..37c274a54 100644\n--- a/drivers/event/octeontx2/otx2_worker_dual.c\n+++ b/drivers/event/octeontx2/otx2_worker_dual.c\n@@ -305,3 +305,38 @@ otx2_ssogws_dual_deq_seg_timeout_burst_ ##name(void *port,\t\t\\\n \n SSO_RX_ADPTR_ENQ_FASTPATH_FUNC\n #undef R\n+\n+#define T(name, f4, f3, f2, f1, f0, sz, flags)\t\t\t\t\\\n+uint16_t __hot\t\t\t\t\t\t\t\t\\\n+otx2_ssogws_dual_tx_adptr_enq_ ## name(void *port,\t\t\t\\\n+\t\t\t\t       struct rte_event ev[],\t\t\\\n+\t\t\t\t       uint16_t nb_events)\t\t\\\n+{\t\t\t\t\t\t\t\t\t\\\n+\tstruct otx2_ssogws_dual *ws = port;\t\t\t\t\\\n+\tstruct otx2_ssogws *vws =\t\t\t\t\t\\\n+\t\t(struct otx2_ssogws *)&ws->ws_state[!ws->vws];\t\t\\\n+\tuint64_t cmd[sz];\t\t\t\t\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\tRTE_SET_USED(nb_events);\t\t\t\t\t\\\n+\treturn otx2_ssogws_event_tx(vws, ev, cmd, flags);\t\t\\\n+}\n+SSO_TX_ADPTR_ENQ_FASTPATH_FUNC\n+#undef T\n+\n+#define T(name, f4, f3, f2, f1, f0, sz, flags)\t\t\t\t\\\n+uint16_t __hot\t\t\t\t\t\t\t\t\\\n+otx2_ssogws_dual_tx_adptr_enq_seg_ ## name(void *port,\t\t\t\\\n+\t\t\t\t\t   struct rte_event ev[],\t\\\n+\t\t\t\t\t   uint16_t nb_events)\t\t\\\n+{\t\t\t\t\t\t\t\t\t\\\n+\tstruct otx2_ssogws_dual *ws = port;\t\t\t\t\\\n+\tstruct otx2_ssogws *vws =\t\t\t\t\t\\\n+\t\t(struct otx2_ssogws *)&ws->ws_state[!ws->vws];\t\t\\\n+\tuint64_t cmd[(sz) + NIX_TX_MSEG_SG_DWORDS - 2];\t\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\tRTE_SET_USED(nb_events);\t\t\t\t\t\\\n+\treturn otx2_ssogws_event_tx(vws, ev, cmd, (flags) |\t\t\\\n+\t\t\t\t    NIX_TX_MULTI_SEG_F);\t\t\\\n+}\n+SSO_TX_ADPTR_ENQ_FASTPATH_FUNC\n+#undef T\n",
    "prefixes": [
        "4/5"
    ]
}