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GET /api/patches/54113/?format=api
{ "id": 54113, "url": "http://patches.dpdk.org/api/patches/54113/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20190602152434.23996-54-jerinj@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20190602152434.23996-54-jerinj@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20190602152434.23996-54-jerinj@marvell.com", "date": "2019-06-02T15:24:29", "name": "[v1,53/58] net/octeontx2: add Tx multi segment version", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "4ecd69e1e1d5a44e773563d190c85da8350c3e0e", "submitter": { "id": 1188, "url": "http://patches.dpdk.org/api/people/1188/?format=api", "name": "Jerin Jacob Kollanukkaran", "email": "jerinj@marvell.com" }, "delegate": { "id": 319, "url": "http://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20190602152434.23996-54-jerinj@marvell.com/mbox/", "series": [ { "id": 4848, "url": "http://patches.dpdk.org/api/series/4848/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=4848", "date": "2019-06-02T15:23:36", "name": "OCTEON TX2 Ethdev driver", "version": 1, "mbox": "http://patches.dpdk.org/series/4848/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/54113/comments/", "check": "fail", "checks": "http://patches.dpdk.org/api/patches/54113/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 865661BC20;\n\tSun, 2 Jun 2019 17:27:21 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n\t[67.231.156.173]) by dpdk.org (Postfix) with ESMTP id 9B0D01BC19\n\tfor <dev@dpdk.org>; Sun, 2 Jun 2019 17:27:20 +0200 (CEST)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n\tby mx0b-0016f401.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id\n\tx52FK4kA020253; Sun, 2 Jun 2019 08:27:20 -0700", "from sc-exch01.marvell.com ([199.233.58.181])\n\tby mx0b-0016f401.pphosted.com with ESMTP id 2survk49ac-1\n\t(version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); \n\tSun, 02 Jun 2019 08:27:19 -0700", "from SC-EXCH01.marvell.com (10.93.176.81) by SC-EXCH01.marvell.com\n\t(10.93.176.81) with Microsoft SMTP Server (TLS) id 15.0.1367.3;\n\tSun, 2 Jun 2019 08:27:18 -0700", "from maili.marvell.com (10.93.176.43) by SC-EXCH01.marvell.com\n\t(10.93.176.81) with Microsoft SMTP Server id 15.0.1367.3 via Frontend\n\tTransport; Sun, 2 Jun 2019 08:27:18 -0700", "from jerin-lab.marvell.com (jerin-lab.marvell.com [10.28.34.14])\n\tby maili.marvell.com (Postfix) with ESMTP id 10B3C3F703F;\n\tSun, 2 Jun 2019 08:27:16 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n\th=from : to : cc :\n\tsubject : date : message-id : in-reply-to : references : mime-version\n\t: content-transfer-encoding : content-type; s=pfpt0818;\n\tbh=2LeZdjdFkyChC2FTBBYLW6SkrNOqvXIhNwL3ihcZvww=;\n\tb=sIg4kMorEC1Ht49kZE8mZcrzf5D99ZwkQWN9kMSaiig9mWpCvyRN3Tfrs0PvX+GxFY95\n\tHNsvX0e1cpKMhNdh6n4bvcmZ9qXHkg87ysaYPlJCkoGVUW2jtwysG8bF5tSUdjNqJFHK\n\tNKhSjyEjn+zEUwQ8OVdSruzRp5l2rwQA3DavRFTFzgzYAN2z5RNs6vgFhAZub6JHh+Gr\n\t6pgam/ksVSOje1QhoncE1KhNDMuKBI39HySaLiDfL+mv9RNW0DRflwG8sZXbBJNFNjgT\n\thdXbvrG4r0cXcBXcqchRokRWN53mZzSgOGwUSaRDOkuQWTHLOQHgqpiL2+O0XMpmi8T3\n\tnQ== ", "From": "<jerinj@marvell.com>", "To": "<dev@dpdk.org>, Jerin Jacob <jerinj@marvell.com>, Nithin Dabilpuram\n\t<ndabilpuram@marvell.com>, Kiran Kumar K <kirankumark@marvell.com>", "CC": "<ferruh.yigit@intel.com>, Pavan Nikhilesh <pbhagavatula@marvell.com>", "Date": "Sun, 2 Jun 2019 20:54:29 +0530", "Message-ID": "<20190602152434.23996-54-jerinj@marvell.com>", "X-Mailer": "git-send-email 2.21.0", "In-Reply-To": "<20190602152434.23996-1-jerinj@marvell.com>", "References": "<20190602152434.23996-1-jerinj@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:, ,\n\tdefinitions=2019-06-02_09:, , signatures=0", "Subject": "[dpdk-dev] [PATCH v1 53/58] net/octeontx2: add Tx multi segment\n\tversion", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Nithin Dabilpuram <ndabilpuram@marvell.com>\n\nAdd multi segment version of packet Transmit function.\n\nSigned-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>\nSigned-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>\n---\n drivers/net/octeontx2/otx2_ethdev.h | 4 ++\n drivers/net/octeontx2/otx2_tx.c | 58 +++++++++++++++++++++\n drivers/net/octeontx2/otx2_tx.h | 81 +++++++++++++++++++++++++++++\n 3 files changed, 143 insertions(+)", "diff": "diff --git a/drivers/net/octeontx2/otx2_ethdev.h b/drivers/net/octeontx2/otx2_ethdev.h\nindex bcc351b76..dff4de250 100644\n--- a/drivers/net/octeontx2/otx2_ethdev.h\n+++ b/drivers/net/octeontx2/otx2_ethdev.h\n@@ -71,6 +71,10 @@\n #define NIX_TX_NB_SEG_MAX\t\t9\n #endif\n \n+#define NIX_TX_MSEG_SG_DWORDS\t\t\t\t\\\n+\t((RTE_ALIGN_MUL_CEIL(NIX_TX_NB_SEG_MAX, 3) / 3)\t\\\n+\t + NIX_TX_NB_SEG_MAX)\n+\n /* Apply BP when CQ is 75% full */\n #define NIX_CQ_BP_LEVEL (25 * 256 / 100)\n \ndiff --git a/drivers/net/octeontx2/otx2_tx.c b/drivers/net/octeontx2/otx2_tx.c\nindex 16d69b74f..0ac5ea652 100644\n--- a/drivers/net/octeontx2/otx2_tx.c\n+++ b/drivers/net/octeontx2/otx2_tx.c\n@@ -49,6 +49,37 @@ nix_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,\n \treturn pkts;\n }\n \n+static __rte_always_inline uint16_t\n+nix_xmit_pkts_mseg(void *tx_queue, struct rte_mbuf **tx_pkts,\n+\t\t uint16_t pkts, uint64_t *cmd, const uint16_t flags)\n+{\n+\tstruct otx2_eth_txq *txq = tx_queue; uint64_t i;\n+\tconst rte_iova_t io_addr = txq->io_addr;\n+\tvoid *lmt_addr = txq->lmt_addr;\n+\tuint16_t segdw;\n+\n+\tNIX_XMIT_FC_OR_RETURN(txq, pkts);\n+\n+\totx2_lmt_mov(cmd, &txq->cmd[0], otx2_nix_tx_ext_subs(flags));\n+\n+\t/* Lets commit any changes in the packet */\n+\trte_cio_wmb();\n+\n+\tfor (i = 0; i < pkts; i++) {\n+\t\totx2_nix_xmit_prepare(tx_pkts[i], cmd, flags);\n+\t\tsegdw = otx2_nix_prepare_mseg(tx_pkts[i], cmd, flags);\n+\t\totx2_nix_xmit_prepare_tstamp(cmd, &txq->cmd[0],\n+\t\t\t\t\t tx_pkts[i]->ol_flags, segdw,\n+\t\t\t\t\t flags);\n+\t\totx2_nix_xmit_mseg_one(cmd, lmt_addr, io_addr, segdw);\n+\t}\n+\n+\t/* Reduce the cached count */\n+\ttxq->fc_cache_pkts -= pkts;\n+\n+\treturn pkts;\n+}\n+\n #define T(name, f4, f3, f2, f1, f0, sz, flags)\t\t\t\t\\\n static uint16_t __rte_noinline\t__hot\t\t\t\t\t\\\n otx2_nix_xmit_pkts_ ## name(void *tx_queue,\t\t\t\t\\\n@@ -62,6 +93,20 @@ otx2_nix_xmit_pkts_ ## name(void *tx_queue,\t\t\t\t\\\n NIX_TX_FASTPATH_MODES\n #undef T\n \n+#define T(name, f4, f3, f2, f1, f0, sz, flags)\t\t\t\t\\\n+static uint16_t __rte_noinline\t__hot\t\t\t\t\t\\\n+otx2_nix_xmit_pkts_mseg_ ## name(void *tx_queue,\t\t\t\\\n+\t\t\tstruct rte_mbuf **tx_pkts, uint16_t pkts)\t\\\n+{\t\t\t\t\t\t\t\t\t\\\n+\tuint64_t cmd[(sz) + NIX_TX_MSEG_SG_DWORDS - 2];\t\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\treturn nix_xmit_pkts_mseg(tx_queue, tx_pkts, pkts, cmd,\t\t\\\n+\t\t\t\t (flags) | NIX_TX_MULTI_SEG_F);\t\\\n+}\n+\n+NIX_TX_FASTPATH_MODES\n+#undef T\n+\n static inline void\n pick_tx_func(struct rte_eth_dev *eth_dev,\n \t const eth_tx_burst_t tx_burst[2][2][2][2][2])\n@@ -80,15 +125,28 @@ pick_tx_func(struct rte_eth_dev *eth_dev,\n void\n otx2_eth_set_tx_function(struct rte_eth_dev *eth_dev)\n {\n+\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n+\n \tconst eth_tx_burst_t nix_eth_tx_burst[2][2][2][2][2] = {\n #define T(name, f4, f3, f2, f1, f0, sz, flags)\t\t\t\t\\\n \t[f4][f3][f2][f1][f0] = otx2_nix_xmit_pkts_ ## name,\n \n+NIX_TX_FASTPATH_MODES\n+#undef T\n+\t};\n+\n+\tconst eth_tx_burst_t nix_eth_tx_burst_mseg[2][2][2][2][2] = {\n+#define T(name, f4, f3, f2, f1, f0, sz, flags)\t\t\t\t\\\n+\t[f4][f3][f2][f1][f0] = otx2_nix_xmit_pkts_mseg_ ## name,\n+\n NIX_TX_FASTPATH_MODES\n #undef T\n \t};\n \n \tpick_tx_func(eth_dev, nix_eth_tx_burst);\n \n+\tif (dev->tx_offloads & DEV_TX_OFFLOAD_MULTI_SEGS)\n+\t\tpick_tx_func(eth_dev, nix_eth_tx_burst_mseg);\n+\n \trte_mb();\n }\ndiff --git a/drivers/net/octeontx2/otx2_tx.h b/drivers/net/octeontx2/otx2_tx.h\nindex db4c1f70f..b75a220ea 100644\n--- a/drivers/net/octeontx2/otx2_tx.h\n+++ b/drivers/net/octeontx2/otx2_tx.h\n@@ -212,6 +212,87 @@ otx2_nix_xmit_one(uint64_t *cmd, void *lmt_addr,\n \t} while (lmt_status == 0);\n }\n \n+static __rte_always_inline uint16_t\n+otx2_nix_prepare_mseg(struct rte_mbuf *m, uint64_t *cmd, const uint16_t flags)\n+{\n+\tstruct nix_send_hdr_s *send_hdr;\n+\tunion nix_send_sg_s *sg;\n+\tstruct rte_mbuf *m_next;\n+\tuint64_t *slist, sg_u;\n+\tuint64_t nb_segs;\n+\tuint64_t segdw;\n+\tuint8_t off, i;\n+\n+\tsend_hdr = (struct nix_send_hdr_s *)cmd;\n+\tsend_hdr->w0.total = m->pkt_len;\n+\tsend_hdr->w0.aura = npa_lf_aura_handle_to_aura(m->pool->pool_id);\n+\n+\tif (flags & NIX_TX_NEED_EXT_HDR)\n+\t\toff = 2;\n+\telse\n+\t\toff = 0;\n+\n+\tsg = (union nix_send_sg_s *)&cmd[2 + off];\n+\tsg_u = sg->u;\n+\tslist = &cmd[3 + off];\n+\n+\ti = 0;\n+\tnb_segs = m->nb_segs;\n+\n+\t/* Fill mbuf segments */\n+\tdo {\n+\t\tm_next = m->next;\n+\t\tsg_u = sg_u | ((uint64_t)m->data_len << (i << 4));\n+\t\t*slist = rte_mbuf_data_iova(m);\n+\t\t/* Set invert df if reference count > 1 */\n+\t\tif (flags & NIX_TX_OFFLOAD_MBUF_NOFF_F)\n+\t\t\tsg_u |=\n+\t\t\t((uint64_t)(rte_pktmbuf_prefree_seg(m) == NULL) <<\n+\t\t\t (i + 55));\n+\t\t/* Mark mempool object as \"put\" since it is freed by NIX */\n+\t\tif (!(sg_u & (1ULL << (i + 55)))) {\n+\t\t\tm->next = NULL;\n+\t\t\t__mempool_check_cookies(m->pool, (void **)&m, 1, 0);\n+\t\t}\n+\t\tslist++;\n+\t\ti++;\n+\t\tnb_segs--;\n+\t\tif (i > 2 && nb_segs) {\n+\t\t\ti = 0;\n+\t\t\t/* Next SG subdesc */\n+\t\t\t*(uint64_t *)slist = sg_u & 0xFC00000000000000;\n+\t\t\tsg->u = sg_u;\n+\t\t\tsg->segs = 3;\n+\t\t\tsg = (union nix_send_sg_s *)slist;\n+\t\t\tsg_u = sg->u;\n+\t\t\tslist++;\n+\t\t}\n+\t\tm = m_next;\n+\t} while (nb_segs);\n+\n+\tsg->u = sg_u;\n+\tsg->segs = i;\n+\tsegdw = (uint64_t *)slist - (uint64_t *)&cmd[2 + off];\n+\t/* Roundup extra dwords to multiple of 2 */\n+\tsegdw = (segdw >> 1) + (segdw & 0x1);\n+\t/* Default dwords */\n+\tsegdw += (off >> 1) + 1 + !!(flags & NIX_TX_OFFLOAD_TSTAMP_F);\n+\tsend_hdr->w0.sizem1 = segdw - 1;\n+\n+\treturn segdw;\n+}\n+\n+static __rte_always_inline void\n+otx2_nix_xmit_mseg_one(uint64_t *cmd, void *lmt_addr,\n+\t\t rte_iova_t io_addr, uint16_t segdw)\n+{\n+\tuint64_t lmt_status;\n+\n+\tdo {\n+\t\totx2_lmt_mov_seg(lmt_addr, (const void *)cmd, segdw);\n+\t\tlmt_status = otx2_lmt_submit(io_addr);\n+\t} while (lmt_status == 0);\n+}\n \n #define L3L4CSUM_F NIX_TX_OFFLOAD_L3_L4_CSUM_F\n #define OL3OL4CSUM_F NIX_TX_OFFLOAD_OL3_OL4_CSUM_F\n", "prefixes": [ "v1", "53/58" ] }