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GET /api/patches/54104/?format=api
{ "id": 54104, "url": "http://patches.dpdk.org/api/patches/54104/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20190602152434.23996-31-jerinj@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20190602152434.23996-31-jerinj@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20190602152434.23996-31-jerinj@marvell.com", "date": "2019-06-02T15:24:06", "name": "[v1,30/58] net/octeontx2: add flow control support", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "1a116d131fcfe20a7a00c2d8f6a8ba82e508281f", "submitter": { "id": 1188, "url": "http://patches.dpdk.org/api/people/1188/?format=api", "name": "Jerin Jacob Kollanukkaran", "email": "jerinj@marvell.com" }, "delegate": { "id": 319, "url": "http://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20190602152434.23996-31-jerinj@marvell.com/mbox/", "series": [ { "id": 4848, "url": "http://patches.dpdk.org/api/series/4848/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=4848", "date": "2019-06-02T15:23:36", "name": "OCTEON TX2 Ethdev driver", "version": 1, "mbox": "http://patches.dpdk.org/series/4848/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/54104/comments/", "check": "fail", "checks": "http://patches.dpdk.org/api/patches/54104/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 690CF1BAE4;\n\tSun, 2 Jun 2019 17:26:14 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n\t[67.231.156.173]) by dpdk.org (Postfix) with ESMTP id 9F9601BACE\n\tfor <dev@dpdk.org>; Sun, 2 Jun 2019 17:26:10 +0200 (CEST)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n\tby mx0b-0016f401.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id\n\tx52FKK4k020364; Sun, 2 Jun 2019 08:26:10 -0700", "from sc-exch02.marvell.com ([199.233.58.182])\n\tby mx0b-0016f401.pphosted.com with ESMTP id 2survk496a-1\n\t(version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); \n\tSun, 02 Jun 2019 08:26:09 -0700", "from SC-EXCH03.marvell.com (10.93.176.83) by SC-EXCH02.marvell.com\n\t(10.93.176.82) with Microsoft SMTP Server (TLS) id 15.0.1367.3;\n\tSun, 2 Jun 2019 08:26:08 -0700", "from maili.marvell.com (10.93.176.43) by SC-EXCH03.marvell.com\n\t(10.93.176.83) with Microsoft SMTP Server id 15.0.1367.3 via Frontend\n\tTransport; Sun, 2 Jun 2019 08:26:08 -0700", "from jerin-lab.marvell.com (jerin-lab.marvell.com [10.28.34.14])\n\tby maili.marvell.com (Postfix) with ESMTP id 0B8ED3F703F;\n\tSun, 2 Jun 2019 08:26:05 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n\th=from : to : cc :\n\tsubject : date : message-id : in-reply-to : references : mime-version\n\t: content-transfer-encoding : content-type; s=pfpt0818;\n\tbh=UdX/E1T53oNXe8WvwAJIbJhI/clmkjV54i0L7JoKxPk=;\n\tb=qtM0O/w13Qh7vF2hxwrQ3G4cY1WQCk1w7YdQfLQCQfjxQ2e/QeYoPUknRIVJgRozS2xx\n\tVYhmzB5obvRpnvs6PKB3g67Ks3EBbPRjKXt8bx0Ch7pWuyer6ydqygBshoUtjD2jvy16\n\tpfHjFVz4ZHTV6brQjKfmgZ03Ymn3foDQu6Nb4egWYoV84mMuRQKEoMv4LwDDYQSnzQx2\n\tgtnntP1WmswWHanZF1IgpkgfjV/i7XQizs6RL4NJSCPf68NiB+efKewOOvHcEfk5/eoB\n\t3vCmP1G2+xqDbOFyF0CRaItBa0uM3AgwK10z5yJ8r5liNVMxhYfW903tX+SaTn5UebeP\n\tJA== ", "From": "<jerinj@marvell.com>", "To": "<dev@dpdk.org>, John McNamara <john.mcnamara@intel.com>, Marko Kovacevic\n\t<marko.kovacevic@intel.com>, Jerin Jacob <jerinj@marvell.com>, \"Nithin\n\tDabilpuram\" <ndabilpuram@marvell.com>, Kiran Kumar K\n\t<kirankumark@marvell.com>", "CC": "<ferruh.yigit@intel.com>, Vamsi Attunuru <vattunuru@marvell.com>", "Date": "Sun, 2 Jun 2019 20:54:06 +0530", "Message-ID": "<20190602152434.23996-31-jerinj@marvell.com>", "X-Mailer": "git-send-email 2.21.0", "In-Reply-To": "<20190602152434.23996-1-jerinj@marvell.com>", "References": "<20190602152434.23996-1-jerinj@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:, ,\n\tdefinitions=2019-06-02_09:, , signatures=0", "Subject": "[dpdk-dev] [PATCH v1 30/58] net/octeontx2: add flow control support", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Vamsi Attunuru <vattunuru@marvell.com>\n\nAdd flow control operations and exposed\notx2_nix_update_flow_ctrl_mode() to enable on the\nconfigured mode in dev_start().\n\nSigned-off-by: Vamsi Attunuru <vattunuru@marvell.com>\nSigned-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>\n---\n doc/guides/nics/features/octeontx2.ini | 1 +\n doc/guides/nics/features/octeontx2_vec.ini | 1 +\n drivers/net/octeontx2/Makefile | 1 +\n drivers/net/octeontx2/meson.build | 1 +\n drivers/net/octeontx2/otx2_ethdev.c | 20 ++\n drivers/net/octeontx2/otx2_ethdev.h | 23 +++\n drivers/net/octeontx2/otx2_flow_ctrl.c | 230 +++++++++++++++++++++\n 7 files changed, 277 insertions(+)\n create mode 100644 drivers/net/octeontx2/otx2_flow_ctrl.c", "diff": "diff --git a/doc/guides/nics/features/octeontx2.ini b/doc/guides/nics/features/octeontx2.ini\nindex 18daccc49..ba7fdc868 100644\n--- a/doc/guides/nics/features/octeontx2.ini\n+++ b/doc/guides/nics/features/octeontx2.ini\n@@ -21,6 +21,7 @@ RSS hash = Y\n RSS key update = Y\n RSS reta update = Y\n Inner RSS = Y\n+Flow control = Y\n Packet type parsing = Y\n Rx descriptor status = Y\n Basic stats = Y\ndiff --git a/doc/guides/nics/features/octeontx2_vec.ini b/doc/guides/nics/features/octeontx2_vec.ini\nindex ccf4dac42..b909918ce 100644\n--- a/doc/guides/nics/features/octeontx2_vec.ini\n+++ b/doc/guides/nics/features/octeontx2_vec.ini\n@@ -21,6 +21,7 @@ RSS hash = Y\n RSS key update = Y\n RSS reta update = Y\n Inner RSS = Y\n+Flow control = Y\n Packet type parsing = Y\n Rx descriptor status = Y\n Basic stats = Y\ndiff --git a/drivers/net/octeontx2/Makefile b/drivers/net/octeontx2/Makefile\nindex 00f61c354..1d3788466 100644\n--- a/drivers/net/octeontx2/Makefile\n+++ b/drivers/net/octeontx2/Makefile\n@@ -37,6 +37,7 @@ SRCS-$(CONFIG_RTE_LIBRTE_OCTEONTX2_PMD) += \\\n \totx2_stats.c\t\\\n \totx2_lookup.c\t\\\n \totx2_ethdev.c\t\\\n+\totx2_flow_ctrl.c \\\n \totx2_ethdev_irq.c \\\n \totx2_ethdev_ops.c \\\n \totx2_ethdev_debug.c \\\ndiff --git a/drivers/net/octeontx2/meson.build b/drivers/net/octeontx2/meson.build\nindex eb5206ea1..e4fcac763 100644\n--- a/drivers/net/octeontx2/meson.build\n+++ b/drivers/net/octeontx2/meson.build\n@@ -10,6 +10,7 @@ sources = files(\n \t\t'otx2_stats.c',\n \t\t'otx2_lookup.c',\n \t\t'otx2_ethdev.c',\n+\t\t'otx2_flow_ctrl.c',\n \t\t'otx2_ethdev_irq.c',\n \t\t'otx2_ethdev_ops.c',\n \t\t'otx2_ethdev_debug.c',\ndiff --git a/drivers/net/octeontx2/otx2_ethdev.c b/drivers/net/octeontx2/otx2_ethdev.c\nindex 0df487983..97e0e3465 100644\n--- a/drivers/net/octeontx2/otx2_ethdev.c\n+++ b/drivers/net/octeontx2/otx2_ethdev.c\n@@ -216,6 +216,14 @@ nix_cq_rq_init(struct rte_eth_dev *eth_dev, struct otx2_eth_dev *dev,\n \taq->cq.cq_err_int_ena = BIT(NIX_CQERRINT_CQE_FAULT);\n \taq->cq.cq_err_int_ena |= BIT(NIX_CQERRINT_DOOR_ERR);\n \n+\t/* TX pause frames enable flowctrl on RX side */\n+\tif (dev->fc_info.tx_pause) {\n+\t\t/* Single bpid is allocated for all rx channels for now */\n+\t\taq->cq.bpid = dev->fc_info.bpid[0];\n+\t\taq->cq.bp = NIX_CQ_BP_LEVEL;\n+\t\taq->cq.bp_ena = 1;\n+\t}\n+\n \t/* Many to one reduction */\n \taq->cq.qint_idx = qid % dev->qints;\n \n@@ -1069,6 +1077,7 @@ otx2_nix_configure(struct rte_eth_dev *eth_dev)\n \n \t/* Free the resources allocated from the previous configure */\n \tif (dev->configured == 1) {\n+\t\totx2_nix_rxchan_bpid_cfg(eth_dev, false);\n \t\toxt2_nix_unregister_queue_irqs(eth_dev);\n \t\tnix_set_nop_rxtx_function(eth_dev);\n \t\trc = nix_store_queue_cfg_and_then_release(eth_dev);\n@@ -1122,6 +1131,12 @@ otx2_nix_configure(struct rte_eth_dev *eth_dev)\n \t\tgoto free_nix_lf;\n \t}\n \n+\trc = otx2_nix_rxchan_bpid_cfg(eth_dev, true);\n+\tif (rc) {\n+\t\totx2_err(\"Failed to configure nix rx chan bpid cfg rc=%d\", rc);\n+\t\tgoto free_nix_lf;\n+\t}\n+\n \t/*\n \t * Restore queue config when reconfigure followed by\n \t * reconfigure and no queue configure invoked from application case.\n@@ -1300,6 +1315,8 @@ static const struct eth_dev_ops otx2_eth_dev_ops = {\n \t.pool_ops_supported = otx2_nix_pool_ops_supported,\n \t.get_module_info = otx2_nix_get_module_info,\n \t.get_module_eeprom = otx2_nix_get_module_eeprom,\n+\t.flow_ctrl_get = otx2_nix_flow_ctrl_get,\n+\t.flow_ctrl_set = otx2_nix_flow_ctrl_set,\n };\n \n static inline int\n@@ -1501,6 +1518,9 @@ otx2_eth_dev_uninit(struct rte_eth_dev *eth_dev, bool mbox_close)\n \tif (rte_eal_process_type() != RTE_PROC_PRIMARY)\n \t\treturn 0;\n \n+\t/* Disable nix bpid config */\n+\totx2_nix_rxchan_bpid_cfg(eth_dev, false);\n+\n \t/* Free up SQs */\n \tfor (i = 0; i < eth_dev->data->nb_tx_queues; i++) {\n \t\totx2_nix_tx_queue_release(eth_dev->data->tx_queues[i]);\ndiff --git a/drivers/net/octeontx2/otx2_ethdev.h b/drivers/net/octeontx2/otx2_ethdev.h\nindex 8fbd4532e..fad151b54 100644\n--- a/drivers/net/octeontx2/otx2_ethdev.h\n+++ b/drivers/net/octeontx2/otx2_ethdev.h\n@@ -68,6 +68,9 @@\n #define NIX_TX_NB_SEG_MAX\t\t9\n #endif\n \n+/* Apply BP when CQ is 75% full */\n+#define NIX_CQ_BP_LEVEL (25 * 256 / 100)\n+\n #define CQ_OP_STAT_OP_ERR\t63\n #define CQ_OP_STAT_CQ_ERR\t46\n \n@@ -150,6 +153,14 @@ struct otx2_npc_flow_info {\n \tuint16_t flow_max_priority;\n };\n \n+struct otx2_fc_info {\n+\tenum rte_eth_fc_mode mode; /**< Link flow control mode */\n+\tuint8_t rx_pause;\n+\tuint8_t tx_pause;\n+\tuint8_t chan_cnt;\n+\tuint16_t bpid[NIX_MAX_CHAN];\n+};\n+\n struct otx2_eth_dev {\n \tOTX2_DEV; /* Base class */\n \tMARKER otx2_eth_dev_data_start;\n@@ -196,6 +207,7 @@ struct otx2_eth_dev {\n \tstruct otx2_nix_tm_node_list node_list;\n \tstruct otx2_nix_tm_shaper_profile_list shaper_profile_list;\n \tstruct otx2_rss_info rss_info;\n+\tstruct otx2_fc_info fc_info;\n \tuint32_t txmap[RTE_ETHDEV_QUEUE_STAT_CNTRS];\n \tuint32_t rxmap[RTE_ETHDEV_QUEUE_STAT_CNTRS];\n \tstruct otx2_npc_flow_info npc_flow;\n@@ -350,6 +362,17 @@ int otx2_cgx_rxtx_stop(struct otx2_eth_dev *dev);\n int otx2_cgx_mac_addr_set(struct rte_eth_dev *eth_dev,\n \t\t\t struct rte_ether_addr *addr);\n \n+/* Flow Control */\n+int otx2_nix_flow_ctrl_get(struct rte_eth_dev *eth_dev,\n+\t\t\t struct rte_eth_fc_conf *fc_conf);\n+\n+int otx2_nix_flow_ctrl_set(struct rte_eth_dev *eth_dev,\n+\t\t\t struct rte_eth_fc_conf *fc_conf);\n+\n+int otx2_nix_rxchan_bpid_cfg(struct rte_eth_dev *eth_dev, bool enb);\n+\n+int otx2_nix_update_flow_ctrl_mode(struct rte_eth_dev *eth_dev);\n+\n /* Lookup configuration */\n void *otx2_nix_fastpath_lookup_mem_get(void);\n \ndiff --git a/drivers/net/octeontx2/otx2_flow_ctrl.c b/drivers/net/octeontx2/otx2_flow_ctrl.c\nnew file mode 100644\nindex 000000000..bd3cda594\n--- /dev/null\n+++ b/drivers/net/octeontx2/otx2_flow_ctrl.c\n@@ -0,0 +1,230 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2019 Marvell International Ltd.\n+ */\n+\n+#include \"otx2_ethdev.h\"\n+\n+int\n+otx2_nix_rxchan_bpid_cfg(struct rte_eth_dev *eth_dev, bool enb)\n+{\n+\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n+\tstruct otx2_fc_info *fc = &dev->fc_info;\n+\tstruct otx2_mbox *mbox = dev->mbox;\n+\tstruct nix_bp_cfg_req *req;\n+\tstruct nix_bp_cfg_rsp *rsp;\n+\tint rc;\n+\n+\tif (otx2_dev_is_vf(dev))\n+\t\treturn 0;\n+\n+\tif (enb) {\n+\t\treq = otx2_mbox_alloc_msg_nix_bp_enable(mbox);\n+\t\treq->chan_base = 0;\n+\t\treq->chan_cnt = 1;\n+\t\treq->bpid_per_chan = 0;\n+\n+\t\trc = otx2_mbox_process_msg(mbox, (void *)&rsp);\n+\t\tif (rc || req->chan_cnt != rsp->chan_cnt) {\n+\t\t\totx2_err(\"Insufficient BPIDs, alloc=%u < req=%u rc=%d\",\n+\t\t\t\t rsp->chan_cnt, req->chan_cnt, rc);\n+\t\t\treturn rc;\n+\t\t}\n+\n+\t\tfc->bpid[0] = rsp->chan_bpid[0];\n+\t} else {\n+\t\treq = otx2_mbox_alloc_msg_nix_bp_disable(mbox);\n+\t\treq->chan_base = 0;\n+\t\treq->chan_cnt = 1;\n+\n+\t\trc = otx2_mbox_process(mbox);\n+\n+\t\tmemset(fc->bpid, 0, sizeof(uint16_t) * NIX_MAX_CHAN);\n+\t}\n+\n+\treturn rc;\n+}\n+\n+int\n+otx2_nix_flow_ctrl_get(struct rte_eth_dev *eth_dev,\n+\t\t struct rte_eth_fc_conf *fc_conf)\n+{\n+\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n+\tstruct cgx_pause_frm_cfg *req, *rsp;\n+\tstruct otx2_mbox *mbox = dev->mbox;\n+\tint rc;\n+\n+\tif (otx2_dev_is_vf(dev))\n+\t\treturn -ENOTSUP;\n+\n+\treq = otx2_mbox_alloc_msg_cgx_cfg_pause_frm(mbox);\n+\treq->set = 0;\n+\n+\trc = otx2_mbox_process_msg(mbox, (void *)&rsp);\n+\tif (rc)\n+\t\tgoto done;\n+\n+\tif (rsp->rx_pause && rsp->tx_pause)\n+\t\tfc_conf->mode = RTE_FC_FULL;\n+\telse if (rsp->rx_pause)\n+\t\tfc_conf->mode = RTE_FC_RX_PAUSE;\n+\telse if (rsp->tx_pause)\n+\t\tfc_conf->mode = RTE_FC_TX_PAUSE;\n+\telse\n+\t\tfc_conf->mode = RTE_FC_NONE;\n+\n+done:\n+\treturn rc;\n+}\n+\n+static int\n+otx2_nix_cq_bp_cfg(struct rte_eth_dev *eth_dev, bool enb)\n+{\n+\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n+\tstruct otx2_fc_info *fc = &dev->fc_info;\n+\tstruct otx2_mbox *mbox = dev->mbox;\n+\tstruct nix_aq_enq_req *aq;\n+\tstruct otx2_eth_rxq *rxq;\n+\tint i, rc;\n+\n+\tfor (i = 0; i < eth_dev->data->nb_rx_queues; i++) {\n+\t\trxq = eth_dev->data->rx_queues[i];\n+\n+\t\taq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);\n+\t\tif (!aq) {\n+\t\t\t/* The shared memory buffer can be full.\n+\t\t\t * flush it and retry\n+\t\t\t */\n+\t\t\totx2_mbox_msg_send(mbox, 0);\n+\t\t\trc = otx2_mbox_wait_for_rsp(mbox, 0);\n+\t\t\tif (rc < 0)\n+\t\t\t\treturn rc;\n+\n+\t\t\taq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);\n+\t\t\tif (!aq)\n+\t\t\t\treturn -ENOMEM;\n+\t\t}\n+\t\taq->qidx = rxq->rq;\n+\t\taq->ctype = NIX_AQ_CTYPE_CQ;\n+\t\taq->op = NIX_AQ_INSTOP_WRITE;\n+\n+\t\tif (enb) {\n+\t\t\taq->cq.bpid = fc->bpid[0];\n+\t\t\taq->cq_mask.bpid = ~(aq->cq_mask.bpid);\n+\t\t\taq->cq.bp = NIX_CQ_BP_LEVEL;\n+\t\t\taq->cq_mask.bp = ~(aq->cq_mask.bp);\n+\t\t}\n+\n+\t\taq->cq.bp_ena = !!enb;\n+\t\taq->cq_mask.bp_ena = ~(aq->cq_mask.bp_ena);\n+\t}\n+\n+\totx2_mbox_msg_send(mbox, 0);\n+\trc = otx2_mbox_wait_for_rsp(mbox, 0);\n+\tif (rc < 0)\n+\t\treturn rc;\n+\n+\treturn 0;\n+}\n+\n+static int\n+otx2_nix_rx_fc_cfg(struct rte_eth_dev *eth_dev, bool enb)\n+{\n+\treturn otx2_nix_cq_bp_cfg(eth_dev, enb);\n+}\n+\n+int\n+otx2_nix_flow_ctrl_set(struct rte_eth_dev *eth_dev,\n+\t\t struct rte_eth_fc_conf *fc_conf)\n+{\n+\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n+\tstruct otx2_fc_info *fc = &dev->fc_info;\n+\tstruct otx2_mbox *mbox = dev->mbox;\n+\tstruct cgx_pause_frm_cfg *req;\n+\tuint8_t tx_pause, rx_pause;\n+\tint rc = 0;\n+\n+\tif (otx2_dev_is_vf(dev))\n+\t\treturn -ENOTSUP;\n+\n+\tif (fc_conf->high_water || fc_conf->low_water || fc_conf->pause_time ||\n+\t fc_conf->mac_ctrl_frame_fwd || fc_conf->autoneg) {\n+\t\totx2_info(\"Flowctrl parameter is not supported\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tif (fc_conf->mode == fc->mode)\n+\t\treturn 0;\n+\n+\trx_pause = (fc_conf->mode == RTE_FC_FULL) ||\n+\t\t (fc_conf->mode == RTE_FC_RX_PAUSE);\n+\ttx_pause = (fc_conf->mode == RTE_FC_FULL) ||\n+\t\t (fc_conf->mode == RTE_FC_TX_PAUSE);\n+\n+\t/* Check if TX pause frame is already enabled or not */\n+\tif (fc->tx_pause ^ tx_pause) {\n+\t\tif (otx2_dev_is_A0(dev) && eth_dev->data->dev_started) {\n+\t\t\t/* on A0, CQ should be in disabled state\n+\t\t\t * while setting flow control configuration.\n+\t\t\t */\n+\t\t\totx2_info(\"Stop the port=%d for setting flow control\\n\",\n+\t\t\t\t eth_dev->data->port_id);\n+\t\t\t\treturn 0;\n+\t\t}\n+\t\t/* TX pause frames, enable/disable flowctrl on RX side. */\n+\t\trc = otx2_nix_rx_fc_cfg(eth_dev, tx_pause);\n+\t\tif (rc)\n+\t\t\treturn rc;\n+\t}\n+\n+\treq = otx2_mbox_alloc_msg_cgx_cfg_pause_frm(mbox);\n+\treq->set = 1;\n+\treq->rx_pause = rx_pause;\n+\treq->tx_pause = tx_pause;\n+\n+\trc = otx2_mbox_process(mbox);\n+\tif (rc)\n+\t\treturn rc;\n+\n+\tfc->tx_pause = tx_pause;\n+\tfc->rx_pause = rx_pause;\n+\tfc->mode = fc_conf->mode;\n+\n+\treturn rc;\n+}\n+\n+int\n+otx2_nix_update_flow_ctrl_mode(struct rte_eth_dev *eth_dev)\n+{\n+\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n+\tstruct otx2_fc_info *fc = &dev->fc_info;\n+\tstruct rte_eth_fc_conf fc_conf;\n+\n+\tif (otx2_dev_is_vf(dev))\n+\t\treturn 0;\n+\n+\tmemset(&fc_conf, 0, sizeof(struct rte_eth_fc_conf));\n+\t/* Both Rx & Tx flow ctrl get enabled(RTE_FC_FULL) in HW\n+\t * by AF driver, update those info in PMD structure.\n+\t */\n+\totx2_nix_flow_ctrl_get(eth_dev, &fc_conf);\n+\n+\tif (fc_conf.mode != fc->mode && fc->mode == RTE_FC_NONE) {\n+\t/* PMD disables HW flow control in the initial application's call\n+\t * to dev_start(), application uses flow_ctrl_set() API to set\n+\t * flow control later.\n+\t */\n+\t\tfc->mode = fc_conf.mode;\n+\t\tfc_conf.mode = RTE_FC_NONE;\n+\t}\n+\n+\t/* To avoid Link credit deadlock on A0, disable Tx FC if it's enabled */\n+\tif (otx2_dev_is_A0(dev) &&\n+\t (fc_conf.mode == RTE_FC_FULL || fc_conf.mode == RTE_FC_RX_PAUSE)) {\n+\t\tfc_conf.mode =\n+\t\t\t\t(fc_conf.mode == RTE_FC_FULL ||\n+\t\t\t\tfc_conf.mode == RTE_FC_TX_PAUSE) ?\n+\t\t\t\tRTE_FC_TX_PAUSE : RTE_FC_NONE;\n+\t}\n+\n+\treturn otx2_nix_flow_ctrl_set(eth_dev, &fc_conf);\n+}\n", "prefixes": [ "v1", "30/58" ] }