get:
Show a patch.

patch:
Update a patch.

put:
Update a patch.

GET /api/patches/54099/?format=api
HTTP 200 OK
Allow: GET, PUT, PATCH, HEAD, OPTIONS
Content-Type: application/json
Vary: Accept

{
    "id": 54099,
    "url": "http://patches.dpdk.org/api/patches/54099/?format=api",
    "web_url": "http://patches.dpdk.org/project/dpdk/patch/20190602152434.23996-26-jerinj@marvell.com/",
    "project": {
        "id": 1,
        "url": "http://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<20190602152434.23996-26-jerinj@marvell.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/20190602152434.23996-26-jerinj@marvell.com",
    "date": "2019-06-02T15:24:01",
    "name": "[v1,25/58] net/octeontx2: add ptype support",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": true,
    "hash": "e7414c1d355042d026c1541f84ad5d5c4c6b7a19",
    "submitter": {
        "id": 1188,
        "url": "http://patches.dpdk.org/api/people/1188/?format=api",
        "name": "Jerin Jacob Kollanukkaran",
        "email": "jerinj@marvell.com"
    },
    "delegate": {
        "id": 319,
        "url": "http://patches.dpdk.org/api/users/319/?format=api",
        "username": "fyigit",
        "first_name": "Ferruh",
        "last_name": "Yigit",
        "email": "ferruh.yigit@amd.com"
    },
    "mbox": "http://patches.dpdk.org/project/dpdk/patch/20190602152434.23996-26-jerinj@marvell.com/mbox/",
    "series": [
        {
            "id": 4848,
            "url": "http://patches.dpdk.org/api/series/4848/?format=api",
            "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=4848",
            "date": "2019-06-02T15:23:36",
            "name": "OCTEON TX2 Ethdev driver",
            "version": 1,
            "mbox": "http://patches.dpdk.org/series/4848/mbox/"
        }
    ],
    "comments": "http://patches.dpdk.org/api/patches/54099/comments/",
    "check": "fail",
    "checks": "http://patches.dpdk.org/api/patches/54099/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@dpdk.org",
        "Delivered-To": "patchwork@dpdk.org",
        "Received": [
            "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 96BBD1BA59;\n\tSun,  2 Jun 2019 17:25:58 +0200 (CEST)",
            "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n\t[67.231.156.173]) by dpdk.org (Postfix) with ESMTP id C49CE1BA56\n\tfor <dev@dpdk.org>; Sun,  2 Jun 2019 17:25:54 +0200 (CEST)",
            "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n\tby mx0b-0016f401.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id\n\tx52FLOCZ021032; Sun, 2 Jun 2019 08:25:54 -0700",
            "from sc-exch02.marvell.com ([199.233.58.182])\n\tby mx0b-0016f401.pphosted.com with ESMTP id 2survk495f-1\n\t(version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); \n\tSun, 02 Jun 2019 08:25:54 -0700",
            "from SC-EXCH01.marvell.com (10.93.176.81) by SC-EXCH02.marvell.com\n\t(10.93.176.82) with Microsoft SMTP Server (TLS) id 15.0.1367.3;\n\tSun, 2 Jun 2019 08:25:52 -0700",
            "from maili.marvell.com (10.93.176.43) by SC-EXCH01.marvell.com\n\t(10.93.176.81) with Microsoft SMTP Server id 15.0.1367.3 via Frontend\n\tTransport; Sun, 2 Jun 2019 08:25:52 -0700",
            "from jerin-lab.marvell.com (jerin-lab.marvell.com [10.28.34.14])\n\tby maili.marvell.com (Postfix) with ESMTP id C51EB3F703F;\n\tSun,  2 Jun 2019 08:25:50 -0700 (PDT)"
        ],
        "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n\th=from : to : cc :\n\tsubject : date : message-id : in-reply-to : references : mime-version\n\t: content-transfer-encoding : content-type; s=pfpt0818;\n\tbh=vscKQO4sF2vl6d471hKbv4L3S9mt3Ssh403ApMLfhuY=;\n\tb=tfuLbDIwjyMEcbd4wuX5vi8+Xzuz7Ip52QbDNEmBYabfbBvnlIEAagdnX6J77QVpN7Wj\n\tq7QbYPKP1/KQP+5locfiZnUopnriaJ5flCGGcU8T0t/xDik9j5WH3OTdJgXoq9Q78iQr\n\tIquEdkXKbMsPL4GWP91YN2vMQpqPfQHzprwULm3O9VG8xeUWSzBY7KjT6tB6bQ2Dduw+\n\tSj0O7TqQFhfsAkYA/eJSzFxSal5xZWecH7E2pA1D++CKZ40FdPIg8MB+Y/4d6rnVgGVt\n\ti500ME3x9nWH9b1oCbzL8mqzadDHiwUA3R3YjlTNRnyruFY/bI8dI6vABMWuxR+bFJB2\n\t9Q== ",
        "From": "<jerinj@marvell.com>",
        "To": "<dev@dpdk.org>, John McNamara <john.mcnamara@intel.com>, Marko Kovacevic\n\t<marko.kovacevic@intel.com>, Jerin Jacob <jerinj@marvell.com>, \"Nithin\n\tDabilpuram\" <ndabilpuram@marvell.com>, Kiran Kumar K\n\t<kirankumark@marvell.com>",
        "CC": "<ferruh.yigit@intel.com>, Harman Kalra <hkalra@marvell.com>",
        "Date": "Sun, 2 Jun 2019 20:54:01 +0530",
        "Message-ID": "<20190602152434.23996-26-jerinj@marvell.com>",
        "X-Mailer": "git-send-email 2.21.0",
        "In-Reply-To": "<20190602152434.23996-1-jerinj@marvell.com>",
        "References": "<20190602152434.23996-1-jerinj@marvell.com>",
        "MIME-Version": "1.0",
        "Content-Transfer-Encoding": "8bit",
        "Content-Type": "text/plain",
        "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:, ,\n\tdefinitions=2019-06-02_09:, , signatures=0",
        "Subject": "[dpdk-dev]  [PATCH v1 25/58] net/octeontx2: add ptype support",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.15",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "From: Jerin Jacob <jerinj@marvell.com>\n\nThe fields from CQE needs to be converted to\nptype and rx ol flags in mbuf. This patch adds\ncreate lookup memory for those items to be\nused in Fastpath.\n\nSigned-off-by: Jerin Jacob <jerinj@marvell.com>\nSigned-off-by: Kiran Kumar K <kirankumark@marvell.com>\nSigned-off-by: Harman Kalra <hkalra@marvell.com>\n---\n doc/guides/nics/features/octeontx2.ini        |   1 +\n doc/guides/nics/features/octeontx2_vec.ini    |   1 +\n doc/guides/nics/features/octeontx2_vf.ini     |   1 +\n drivers/net/octeontx2/Makefile                |   1 +\n drivers/net/octeontx2/meson.build             |   1 +\n drivers/net/octeontx2/otx2_ethdev.c           |   2 +\n drivers/net/octeontx2/otx2_ethdev.h           |   6 +\n drivers/net/octeontx2/otx2_lookup.c           | 279 ++++++++++++++++++\n drivers/net/octeontx2/otx2_rx.h               |   7 +\n .../octeontx2/rte_pmd_octeontx2_version.map   |   3 +\n 10 files changed, 302 insertions(+)\n create mode 100644 drivers/net/octeontx2/otx2_lookup.c",
    "diff": "diff --git a/doc/guides/nics/features/octeontx2.ini b/doc/guides/nics/features/octeontx2.ini\nindex 31816a183..221fc84d8 100644\n--- a/doc/guides/nics/features/octeontx2.ini\n+++ b/doc/guides/nics/features/octeontx2.ini\n@@ -20,6 +20,7 @@ RSS hash             = Y\n RSS key update       = Y\n RSS reta update      = Y\n Inner RSS            = Y\n+Packet type parsing  = Y\n Basic stats          = Y\n Stats per queue      = Y\n Extended stats       = Y\ndiff --git a/doc/guides/nics/features/octeontx2_vec.ini b/doc/guides/nics/features/octeontx2_vec.ini\nindex d79428652..e11327c7a 100644\n--- a/doc/guides/nics/features/octeontx2_vec.ini\n+++ b/doc/guides/nics/features/octeontx2_vec.ini\n@@ -20,6 +20,7 @@ RSS hash             = Y\n RSS key update       = Y\n RSS reta update      = Y\n Inner RSS            = Y\n+Packet type parsing  = Y\n Basic stats          = Y\n Extended stats       = Y\n Stats per queue      = Y\ndiff --git a/doc/guides/nics/features/octeontx2_vf.ini b/doc/guides/nics/features/octeontx2_vf.ini\nindex d4deb52af..b2115cea4 100644\n--- a/doc/guides/nics/features/octeontx2_vf.ini\n+++ b/doc/guides/nics/features/octeontx2_vf.ini\n@@ -16,6 +16,7 @@ RSS hash             = Y\n RSS key update       = Y\n RSS reta update      = Y\n Inner RSS            = Y\n+Packet type parsing  = Y\n Basic stats          = Y\n Extended stats       = Y\n Stats per queue      = Y\ndiff --git a/drivers/net/octeontx2/Makefile b/drivers/net/octeontx2/Makefile\nindex cf2ba0e0e..00f61c354 100644\n--- a/drivers/net/octeontx2/Makefile\n+++ b/drivers/net/octeontx2/Makefile\n@@ -35,6 +35,7 @@ SRCS-$(CONFIG_RTE_LIBRTE_OCTEONTX2_PMD) += \\\n \totx2_mac.c\t\\\n \totx2_link.c\t\\\n \totx2_stats.c\t\\\n+\totx2_lookup.c\t\\\n \totx2_ethdev.c\t\\\n \totx2_ethdev_irq.c \\\n \totx2_ethdev_ops.c \\\ndiff --git a/drivers/net/octeontx2/meson.build b/drivers/net/octeontx2/meson.build\nindex 14e8e78f8..eb5206ea1 100644\n--- a/drivers/net/octeontx2/meson.build\n+++ b/drivers/net/octeontx2/meson.build\n@@ -8,6 +8,7 @@ sources = files(\n \t\t'otx2_mac.c',\n \t\t'otx2_link.c',\n \t\t'otx2_stats.c',\n+\t\t'otx2_lookup.c',\n \t\t'otx2_ethdev.c',\n \t\t'otx2_ethdev_irq.c',\n \t\t'otx2_ethdev_ops.c',\ndiff --git a/drivers/net/octeontx2/otx2_ethdev.c b/drivers/net/octeontx2/otx2_ethdev.c\nindex a269e1be6..9fbade075 100644\n--- a/drivers/net/octeontx2/otx2_ethdev.c\n+++ b/drivers/net/octeontx2/otx2_ethdev.c\n@@ -441,6 +441,7 @@ otx2_nix_rx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t rq,\n \trxq->pool = mp;\n \trxq->qlen = nix_qsize_to_val(qsize);\n \trxq->qsize = qsize;\n+\trxq->lookup_mem = otx2_nix_fastpath_lookup_mem_get();\n \n \t/* Alloc completion queue */\n \trc = nix_cq_rq_init(eth_dev, dev, rq, rxq, mp);\n@@ -1267,6 +1268,7 @@ static const struct eth_dev_ops otx2_eth_dev_ops = {\n \t.tx_queue_stop            = otx2_nix_tx_queue_stop,\n \t.rx_queue_start           = otx2_nix_rx_queue_start,\n \t.rx_queue_stop            = otx2_nix_rx_queue_stop,\n+\t.dev_supported_ptypes_get = otx2_nix_supported_ptypes_get,\n \t.stats_get                = otx2_nix_dev_stats_get,\n \t.stats_reset              = otx2_nix_dev_stats_reset,\n \t.get_reg                  = otx2_nix_dev_get_reg,\ndiff --git a/drivers/net/octeontx2/otx2_ethdev.h b/drivers/net/octeontx2/otx2_ethdev.h\nindex b2b7d4186..83d6b2dc2 100644\n--- a/drivers/net/octeontx2/otx2_ethdev.h\n+++ b/drivers/net/octeontx2/otx2_ethdev.h\n@@ -335,6 +335,12 @@ int otx2_cgx_rxtx_stop(struct otx2_eth_dev *dev);\n int otx2_cgx_mac_addr_set(struct rte_eth_dev *eth_dev,\n \t\t\t  struct rte_ether_addr *addr);\n \n+/* Lookup configuration */\n+void *otx2_nix_fastpath_lookup_mem_get(void);\n+\n+/* PTYPES */\n+const uint32_t *otx2_nix_supported_ptypes_get(struct rte_eth_dev *dev);\n+\n /* Mac address handling */\n int otx2_nix_mac_addr_set(struct rte_eth_dev *eth_dev,\n \t\t\t  struct rte_ether_addr *addr);\ndiff --git a/drivers/net/octeontx2/otx2_lookup.c b/drivers/net/octeontx2/otx2_lookup.c\nnew file mode 100644\nindex 000000000..025933efa\n--- /dev/null\n+++ b/drivers/net/octeontx2/otx2_lookup.c\n@@ -0,0 +1,279 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2019 Marvell International Ltd.\n+ */\n+\n+#include <rte_common.h>\n+#include <rte_memzone.h>\n+\n+#include \"otx2_ethdev.h\"\n+\n+/* NIX_RX_PARSE_S's ERRCODE + ERRLEV (12 bits) */\n+#define ERRCODE_ERRLEN_WIDTH\t\t12\n+#define ERR_ARRAY_SZ\t\t\t((BIT(ERRCODE_ERRLEN_WIDTH)) *\\\n+\t\t\t\t\tsizeof(uint32_t))\n+\n+#define LOOKUP_ARRAY_SZ\t\t\t(PTYPE_ARRAY_SZ + ERR_ARRAY_SZ)\n+\n+const uint32_t *\n+otx2_nix_supported_ptypes_get(struct rte_eth_dev *eth_dev)\n+{\n+\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n+\n+\tstatic const uint32_t ptypes[] = {\n+\t\tRTE_PTYPE_L2_ETHER_QINQ, /* LB */\n+\t\tRTE_PTYPE_L2_ETHER_VLAN, /* LB */\n+\t\tRTE_PTYPE_L2_ETHER_TIMESYNC, /* LB */\n+\t\tRTE_PTYPE_L2_ETHER_ARP,\t /* LC */\n+\t\tRTE_PTYPE_L2_ETHER_NSH,\t /* LC */\n+\t\tRTE_PTYPE_L2_ETHER_FCOE, /* LC */\n+\t\tRTE_PTYPE_L2_ETHER_MPLS, /* LC */\n+\t\tRTE_PTYPE_L3_IPV4,\t /* LC */\n+\t\tRTE_PTYPE_L3_IPV4_EXT,\t /* LC */\n+\t\tRTE_PTYPE_L3_IPV6,\t /* LC */\n+\t\tRTE_PTYPE_L3_IPV6_EXT,\t /* LC */\n+\t\tRTE_PTYPE_L4_TCP,\t /* LD */\n+\t\tRTE_PTYPE_L4_UDP,\t /* LD */\n+\t\tRTE_PTYPE_L4_SCTP,\t /* LD */\n+\t\tRTE_PTYPE_L4_ICMP,\t /* LD */\n+\t\tRTE_PTYPE_L4_IGMP,\t /* LD */\n+\t\tRTE_PTYPE_TUNNEL_GRE,\t /* LD */\n+\t\tRTE_PTYPE_TUNNEL_ESP,\t /* LD */\n+\t\tRTE_PTYPE_INNER_L2_ETHER,/* LE */\n+\t\tRTE_PTYPE_INNER_L3_IPV4, /* LF */\n+\t\tRTE_PTYPE_INNER_L3_IPV6, /* LF */\n+\t\tRTE_PTYPE_INNER_L4_TCP,\t /* LG */\n+\t\tRTE_PTYPE_INNER_L4_UDP,  /* LG */\n+\t\tRTE_PTYPE_INNER_L4_SCTP, /* LG */\n+\t\tRTE_PTYPE_INNER_L4_ICMP, /* LG */\n+\t};\n+\n+\tif (dev->rx_offload_flags & NIX_RX_OFFLOAD_PTYPE_F)\n+\t\treturn ptypes;\n+\telse\n+\t\treturn NULL;\n+}\n+\n+/*\n+ * +------------------ +------------------ +\n+ * |  | IL4 | IL3| IL2 | TU | L4 | L3 | L2 |\n+ * +-------------------+-------------------+\n+ *\n+ * +-------------------+------------------ +\n+ * |  | LG | LF  | LE  | LD | LC | LB |    |\n+ * +-------------------+-------------------+\n+ *\n+ * ptype       [LD - LC - LB]  = TU  - L4 -  L3  - T2\n+ * ptype_tunnel[LG - LF - LE]  = IL4 - IL3 - IL2 - TU\n+ *\n+ */\n+static void\n+nix_create_non_tunnel_ptype_array(uint16_t *ptype)\n+{\n+\tuint8_t lb, lc, ld;\n+\tuint16_t idx, val;\n+\n+\tfor (idx = 0; idx < PTYPE_NON_TUNNEL_ARRAY_SZ; idx++) {\n+\t\tlb = idx & 0xF;\n+\t\tlc = (idx & 0xF0) >> 4;\n+\t\tld = (idx & 0xF00) >> 8;\n+\t\tval = RTE_PTYPE_UNKNOWN;\n+\n+\t\tswitch (lb) {\n+\t\tcase NPC_LT_LB_QINQ:\n+\t\t\tval |= RTE_PTYPE_L2_ETHER_QINQ;\n+\t\t\tbreak;\n+\t\tcase NPC_LT_LB_CTAG:\n+\t\t\tval |= RTE_PTYPE_L2_ETHER_VLAN;\n+\t\t\tbreak;\n+\t\t}\n+\n+\t\tswitch (lc) {\n+\t\tcase NPC_LT_LC_ARP:\n+\t\t\tval |= RTE_PTYPE_L2_ETHER_ARP;\n+\t\t\tbreak;\n+\t\tcase NPC_LT_LC_NSH:\n+\t\t\tval |= RTE_PTYPE_L2_ETHER_NSH;\n+\t\t\tbreak;\n+\t\tcase NPC_LT_LC_FCOE:\n+\t\t\tval |= RTE_PTYPE_L2_ETHER_FCOE;\n+\t\t\tbreak;\n+\t\tcase NPC_LT_LC_MPLS:\n+\t\t\tval |= RTE_PTYPE_L2_ETHER_MPLS;\n+\t\t\tbreak;\n+\t\tcase NPC_LT_LC_IP:\n+\t\t\tval |= RTE_PTYPE_L3_IPV4;\n+\t\t\tbreak;\n+\t\tcase NPC_LT_LC_IP_OPT:\n+\t\t\tval |= RTE_PTYPE_L3_IPV4_EXT;\n+\t\t\tbreak;\n+\t\tcase NPC_LT_LC_IP6:\n+\t\t\tval |= RTE_PTYPE_L3_IPV6;\n+\t\t\tbreak;\n+\t\tcase NPC_LT_LC_IP6_EXT:\n+\t\t\tval |= RTE_PTYPE_L3_IPV6_EXT;\n+\t\t\tbreak;\n+\t\tcase NPC_LT_LC_PTP:\n+\t\t\tval |= RTE_PTYPE_L2_ETHER_TIMESYNC;\n+\t\t\tbreak;\n+\t\t}\n+\n+\t\tswitch (ld) {\n+\t\tcase NPC_LT_LD_TCP:\n+\t\t\tval |= RTE_PTYPE_L4_TCP;\n+\t\t\tbreak;\n+\t\tcase NPC_LT_LD_UDP:\n+\t\t\tval |= RTE_PTYPE_L4_UDP;\n+\t\t\tbreak;\n+\t\tcase NPC_LT_LD_SCTP:\n+\t\t\tval |= RTE_PTYPE_L4_SCTP;\n+\t\t\tbreak;\n+\t\tcase NPC_LT_LD_ICMP:\n+\t\t\tval |= RTE_PTYPE_L4_ICMP;\n+\t\t\tbreak;\n+\t\tcase NPC_LT_LD_IGMP:\n+\t\t\tval |= RTE_PTYPE_L4_IGMP;\n+\t\t\tbreak;\n+\t\tcase NPC_LT_LD_GRE:\n+\t\t\tval |= RTE_PTYPE_TUNNEL_GRE;\n+\t\t\tbreak;\n+\t\tcase NPC_LT_LD_ESP:\n+\t\t\tval |= RTE_PTYPE_TUNNEL_ESP;\n+\t\t\tbreak;\n+\t\t}\n+\t\tptype[idx] = val;\n+\t}\n+}\n+\n+#define TU_SHIFT(x) ((x) >> PTYPE_WIDTH)\n+static void\n+nix_create_tunnel_ptype_array(uint16_t *ptype)\n+{\n+\tuint8_t le, lf, lg;\n+\tuint16_t idx, val;\n+\n+\t/* Skip non tunnel ptype array memory */\n+\tptype = ptype + PTYPE_NON_TUNNEL_ARRAY_SZ;\n+\n+\tfor (idx = 0; idx < PTYPE_TUNNEL_ARRAY_SZ; idx++) {\n+\t\tle = idx & 0xF;\n+\t\tlf = (idx & 0xF0) >> 4;\n+\t\tlg = (idx & 0xF00) >> 8;\n+\t\tval = RTE_PTYPE_UNKNOWN;\n+\n+\t\tswitch (le) {\n+\t\tcase NPC_LT_LE_TU_ETHER:\n+\t\t\tval |= TU_SHIFT(RTE_PTYPE_INNER_L2_ETHER);\n+\t\t\tbreak;\n+\t\t}\n+\t\tswitch (lf) {\n+\t\tcase NPC_LT_LF_TU_IP:\n+\t\t\tval |= TU_SHIFT(RTE_PTYPE_INNER_L3_IPV4);\n+\t\t\tbreak;\n+\t\tcase NPC_LT_LF_TU_IP6:\n+\t\t\tval |= TU_SHIFT(RTE_PTYPE_INNER_L3_IPV6);\n+\t\t\tbreak;\n+\t\t}\n+\t\tswitch (lg) {\n+\t\tcase NPC_LT_LG_TU_TCP:\n+\t\t\tval |= TU_SHIFT(RTE_PTYPE_INNER_L4_TCP);\n+\t\t\tbreak;\n+\t\tcase NPC_LT_LG_TU_UDP:\n+\t\t\tval |= TU_SHIFT(RTE_PTYPE_INNER_L4_UDP);\n+\t\t\tbreak;\n+\t\tcase NPC_LT_LG_TU_SCTP:\n+\t\t\tval |= TU_SHIFT(RTE_PTYPE_INNER_L4_SCTP);\n+\t\t\tbreak;\n+\t\tcase NPC_LT_LG_TU_ICMP:\n+\t\t\tval |= TU_SHIFT(RTE_PTYPE_INNER_L4_ICMP);\n+\t\t\tbreak;\n+\t\t}\n+\n+\t\tptype[idx] = val;\n+\t}\n+}\n+\n+static void\n+nix_create_rx_ol_flags_array(void *mem)\n+{\n+\tuint16_t idx, errcode, errlev;\n+\tuint32_t val, *ol_flags;\n+\n+\t/* Skip ptype array memory */\n+\tol_flags = (uint32_t *)((uint8_t *)mem + PTYPE_ARRAY_SZ);\n+\n+\tfor (idx = 0; idx < BIT(ERRCODE_ERRLEN_WIDTH); idx++) {\n+\t\terrlev = idx & 0xf;\n+\t\terrcode = (idx & 0xff0) >> 4;\n+\n+\t\tval = PKT_RX_IP_CKSUM_UNKNOWN;\n+\t\tval |= PKT_RX_L4_CKSUM_UNKNOWN;\n+\t\tval |= PKT_RX_OUTER_L4_CKSUM_UNKNOWN;\n+\n+\t\tswitch (errlev) {\n+\t\tcase NPC_ERRLEV_RE:\n+\t\t\t/* Mark all errors as BAD checksum errors */\n+\t\t\tif (errcode) {\n+\t\t\t\tval |= PKT_RX_IP_CKSUM_BAD;\n+\t\t\t\tval |= PKT_RX_L4_CKSUM_BAD;\n+\t\t\t} else {\n+\t\t\t\tval |= PKT_RX_IP_CKSUM_GOOD;\n+\t\t\t\tval |= PKT_RX_L4_CKSUM_GOOD;\n+\t\t\t}\n+\t\t\tbreak;\n+\t\tcase NPC_ERRLEV_LC:\n+\t\t\tif (errcode == NPC_EC_OIP4_CSUM ||\n+\t\t\t    errcode == NPC_EC_IP_FRAG_OFFSET_1) {\n+\t\t\t\tval |= PKT_RX_IP_CKSUM_BAD;\n+\t\t\t\tval |= PKT_RX_EIP_CKSUM_BAD;\n+\t\t\t} else {\n+\t\t\t\tval |= PKT_RX_IP_CKSUM_GOOD;\n+\t\t\t}\n+\t\t\tbreak;\n+\t\tcase NPC_ERRLEV_LF:\n+\t\t\tif (errcode == NPC_EC_IIP4_CSUM)\n+\t\t\t\tval |= PKT_RX_IP_CKSUM_BAD;\n+\t\t\telse\n+\t\t\t\tval |= PKT_RX_IP_CKSUM_GOOD;\n+\t\t\tbreak;\n+\t\tcase NPC_ERRLEV_NIX:\n+\t\t\tif (errcode == NIX_RX_PERRCODE_OL4_CHK) {\n+\t\t\t\tval |= PKT_RX_OUTER_L4_CKSUM_BAD;\n+\t\t\t\tval |= PKT_RX_L4_CKSUM_BAD;\n+\t\t\t} else if (errcode == NIX_RX_PERRCODE_IL4_CHK) {\n+\t\t\t\tval |= PKT_RX_L4_CKSUM_BAD;\n+\t\t\t} else {\n+\t\t\t\tval |= PKT_RX_IP_CKSUM_GOOD;\n+\t\t\t\tval |= PKT_RX_L4_CKSUM_GOOD;\n+\t\t\t}\n+\t\t\tbreak;\n+\t\t}\n+\n+\t\tol_flags[idx] = val;\n+\t}\n+}\n+\n+void *\n+otx2_nix_fastpath_lookup_mem_get(void)\n+{\n+\tconst char name[] = \"otx2_nix_fastpath_lookup_mem\";\n+\tconst struct rte_memzone *mz;\n+\tvoid *mem;\n+\n+\tmz = rte_memzone_lookup(name);\n+\tif (mz != NULL)\n+\t\treturn mz->addr;\n+\n+\t/* Request for the first time */\n+\tmz = rte_memzone_reserve_aligned(name, LOOKUP_ARRAY_SZ,\n+\t\t\t\t\t SOCKET_ID_ANY, 0, OTX2_ALIGN);\n+\tif (mz != NULL) {\n+\t\tmem = mz->addr;\n+\t\t/* Form the ptype array lookup memory */\n+\t\tnix_create_non_tunnel_ptype_array(mem);\n+\t\tnix_create_tunnel_ptype_array(mem);\n+\t\t/* Form the rx ol_flags based on errcode */\n+\t\tnix_create_rx_ol_flags_array(mem);\n+\t\treturn mem;\n+\t}\n+\treturn NULL;\n+}\ndiff --git a/drivers/net/octeontx2/otx2_rx.h b/drivers/net/octeontx2/otx2_rx.h\nindex 1749c43ff..1283fdf37 100644\n--- a/drivers/net/octeontx2/otx2_rx.h\n+++ b/drivers/net/octeontx2/otx2_rx.h\n@@ -5,6 +5,13 @@\n #ifndef __OTX2_RX_H__\n #define __OTX2_RX_H__\n \n+#define PTYPE_WIDTH 12\n+#define PTYPE_NON_TUNNEL_ARRAY_SZ\tBIT(PTYPE_WIDTH)\n+#define PTYPE_TUNNEL_ARRAY_SZ\t\tBIT(PTYPE_WIDTH)\n+#define PTYPE_ARRAY_SZ\t\t\t((PTYPE_NON_TUNNEL_ARRAY_SZ +\\\n+\t\t\t\t\t PTYPE_TUNNEL_ARRAY_SZ) *\\\n+\t\t\t\t\t sizeof(uint16_t))\n+\n #define NIX_RX_OFFLOAD_PTYPE_F         BIT(1)\n \n #endif /* __OTX2_RX_H__ */\ndiff --git a/drivers/net/octeontx2/rte_pmd_octeontx2_version.map b/drivers/net/octeontx2/rte_pmd_octeontx2_version.map\nindex fc8c95e91..3cfd37715 100644\n--- a/drivers/net/octeontx2/rte_pmd_octeontx2_version.map\n+++ b/drivers/net/octeontx2/rte_pmd_octeontx2_version.map\n@@ -1,4 +1,7 @@\n DPDK_19.05 {\n+\tglobal:\n+\n+\totx2_nix_fastpath_lookup_mem_get;\n \n \tlocal: *;\n };\n",
    "prefixes": [
        "v1",
        "25/58"
    ]
}