get:
Show a patch.

patch:
Update a patch.

put:
Update a patch.

GET /api/patches/54097/?format=api
HTTP 200 OK
Allow: GET, PUT, PATCH, HEAD, OPTIONS
Content-Type: application/json
Vary: Accept

{
    "id": 54097,
    "url": "http://patches.dpdk.org/api/patches/54097/?format=api",
    "web_url": "http://patches.dpdk.org/project/dpdk/patch/20190602152434.23996-58-jerinj@marvell.com/",
    "project": {
        "id": 1,
        "url": "http://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<20190602152434.23996-58-jerinj@marvell.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/20190602152434.23996-58-jerinj@marvell.com",
    "date": "2019-06-02T15:24:33",
    "name": "[v1,57/58] net/octeontx2: add MTU set operation",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": true,
    "hash": "733fab8cecd4cf06af07d13335babedbf651b7ff",
    "submitter": {
        "id": 1188,
        "url": "http://patches.dpdk.org/api/people/1188/?format=api",
        "name": "Jerin Jacob Kollanukkaran",
        "email": "jerinj@marvell.com"
    },
    "delegate": {
        "id": 319,
        "url": "http://patches.dpdk.org/api/users/319/?format=api",
        "username": "fyigit",
        "first_name": "Ferruh",
        "last_name": "Yigit",
        "email": "ferruh.yigit@amd.com"
    },
    "mbox": "http://patches.dpdk.org/project/dpdk/patch/20190602152434.23996-58-jerinj@marvell.com/mbox/",
    "series": [
        {
            "id": 4848,
            "url": "http://patches.dpdk.org/api/series/4848/?format=api",
            "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=4848",
            "date": "2019-06-02T15:23:36",
            "name": "OCTEON TX2 Ethdev driver",
            "version": 1,
            "mbox": "http://patches.dpdk.org/series/4848/mbox/"
        }
    ],
    "comments": "http://patches.dpdk.org/api/patches/54097/comments/",
    "check": "fail",
    "checks": "http://patches.dpdk.org/api/patches/54097/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@dpdk.org",
        "Delivered-To": "patchwork@dpdk.org",
        "Received": [
            "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 97CEF1BC1B;\n\tSun,  2 Jun 2019 17:27:34 +0200 (CEST)",
            "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n\t[67.231.156.173]) by dpdk.org (Postfix) with ESMTP id 2F45B1BC71\n\tfor <dev@dpdk.org>; Sun,  2 Jun 2019 17:27:33 +0200 (CEST)",
            "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n\tby mx0b-0016f401.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id\n\tx52FKKpJ020361; Sun, 2 Jun 2019 08:27:32 -0700",
            "from sc-exch04.marvell.com ([199.233.58.184])\n\tby mx0b-0016f401.pphosted.com with ESMTP id 2survk49au-1\n\t(version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); \n\tSun, 02 Jun 2019 08:27:32 -0700",
            "from SC-EXCH03.marvell.com (10.93.176.83) by SC-EXCH04.marvell.com\n\t(10.93.176.84) with Microsoft SMTP Server (TLS) id 15.0.1367.3;\n\tSun, 2 Jun 2019 08:27:31 -0700",
            "from maili.marvell.com (10.93.176.43) by SC-EXCH03.marvell.com\n\t(10.93.176.83) with Microsoft SMTP Server id 15.0.1367.3 via Frontend\n\tTransport; Sun, 2 Jun 2019 08:27:31 -0700",
            "from jerin-lab.marvell.com (jerin-lab.marvell.com [10.28.34.14])\n\tby maili.marvell.com (Postfix) with ESMTP id D61913F703F;\n\tSun,  2 Jun 2019 08:27:28 -0700 (PDT)"
        ],
        "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n\th=from : to : cc :\n\tsubject : date : message-id : in-reply-to : references : mime-version\n\t: content-transfer-encoding : content-type; s=pfpt0818;\n\tbh=I7lG+v8KhMdwuGlsn8g96AHyyufEkLaQdRNKvQyfMUo=;\n\tb=B1om2C/FgirL7ocLdqG2WN2Dci2uOeu0n1Kz5BUPYh92fv4E+xoxNAHiVsrabi5zYbp4\n\tEnPYEY6IsP+cQZe7qy+gM+TmZt6KnrDYV28WWdsrNzsEW+BjsxTV59t+4/tYr6idPxBP\n\t+adtGXxKJUrMWtfjQ5RDuFg3orNawP2SCxsqPwosaAxlpAM9qDc86MWQN8JR9MPOKkvw\n\tBM7Rk6WmdAWxA14RxZoSMRek/pa88eMnZSydfdf+oR1T3wm8dJdVHNQdeKtKF2IpLamM\n\txO1Rhe868woadPx7a+T1Uznzbrdt1n5zNGYUGczMwFjs2GBhPk5nhSy60IM9eptUqLU1\n\tAQ== ",
        "From": "<jerinj@marvell.com>",
        "To": "<dev@dpdk.org>, John McNamara <john.mcnamara@intel.com>, Marko Kovacevic\n\t<marko.kovacevic@intel.com>, Jerin Jacob <jerinj@marvell.com>, \"Nithin\n\tDabilpuram\" <ndabilpuram@marvell.com>, Kiran Kumar K\n\t<kirankumark@marvell.com>",
        "CC": "<ferruh.yigit@intel.com>, Vamsi Attunuru <vattunuru@marvell.com>, \"Sunil\n\tKumar Kori\" <skori@marvell.com>",
        "Date": "Sun, 2 Jun 2019 20:54:33 +0530",
        "Message-ID": "<20190602152434.23996-58-jerinj@marvell.com>",
        "X-Mailer": "git-send-email 2.21.0",
        "In-Reply-To": "<20190602152434.23996-1-jerinj@marvell.com>",
        "References": "<20190602152434.23996-1-jerinj@marvell.com>",
        "MIME-Version": "1.0",
        "Content-Transfer-Encoding": "8bit",
        "Content-Type": "text/plain",
        "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:, ,\n\tdefinitions=2019-06-02_09:, , signatures=0",
        "Subject": "[dpdk-dev]  [PATCH v1 57/58] net/octeontx2: add MTU set operation",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.15",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "From: Vamsi Attunuru <vattunuru@marvell.com>\n\nAdd MTU set operation and MTU update feature.\n\nSigned-off-by: Vamsi Attunuru <vattunuru@marvell.com>\nSigned-off-by: Sunil Kumar Kori <skori@marvell.com>\n---\n doc/guides/nics/features/octeontx2.ini     |  1 +\n doc/guides/nics/features/octeontx2_vec.ini |  1 +\n drivers/net/octeontx2/otx2_ethdev.c        |  7 ++\n drivers/net/octeontx2/otx2_ethdev.h        |  4 ++\n drivers/net/octeontx2/otx2_ethdev_ops.c    | 80 ++++++++++++++++++++++\n 5 files changed, 93 insertions(+)",
    "diff": "diff --git a/doc/guides/nics/features/octeontx2.ini b/doc/guides/nics/features/octeontx2.ini\nindex 396979451..e96c588fa 100644\n--- a/doc/guides/nics/features/octeontx2.ini\n+++ b/doc/guides/nics/features/octeontx2.ini\n@@ -15,6 +15,7 @@ Link status event    = Y\n Fast mbuf free       = Y\n Free Tx mbuf on demand = Y\n Queue start/stop     = Y\n+MTU update           = Y\n Promiscuous mode     = Y\n Allmulticast mode    = Y\n Unicast MAC filter   = Y\ndiff --git a/doc/guides/nics/features/octeontx2_vec.ini b/doc/guides/nics/features/octeontx2_vec.ini\nindex 1435fd91e..7ad097df4 100644\n--- a/doc/guides/nics/features/octeontx2_vec.ini\n+++ b/doc/guides/nics/features/octeontx2_vec.ini\n@@ -15,6 +15,7 @@ Link status event    = Y\n Fast mbuf free       = Y\n Free Tx mbuf on demand = Y\n Queue start/stop     = Y\n+MTU update           = Y\n Promiscuous mode     = Y\n Allmulticast mode    = Y\n Unicast MAC filter   = Y\ndiff --git a/drivers/net/octeontx2/otx2_ethdev.c b/drivers/net/octeontx2/otx2_ethdev.c\nindex 6c67cecd5..ddd924ce8 100644\n--- a/drivers/net/octeontx2/otx2_ethdev.c\n+++ b/drivers/net/octeontx2/otx2_ethdev.c\n@@ -1453,6 +1453,12 @@ otx2_nix_dev_start(struct rte_eth_dev *eth_dev)\n \tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n \tint rc, i;\n \n+\tif (eth_dev->data->nb_rx_queues != 0) {\n+\t\trc = otx2_nix_recalc_mtu(eth_dev);\n+\t\tif (rc)\n+\t\t\treturn rc;\n+\t}\n+\n \t/* Start rx queues */\n \tfor (i = 0; i < eth_dev->data->nb_rx_queues; i++) {\n \t\trc = otx2_nix_rx_queue_start(eth_dev, i);\n@@ -1525,6 +1531,7 @@ static const struct eth_dev_ops otx2_eth_dev_ops = {\n \t.stats_get                = otx2_nix_dev_stats_get,\n \t.stats_reset              = otx2_nix_dev_stats_reset,\n \t.get_reg                  = otx2_nix_dev_get_reg,\n+\t.mtu_set                  = otx2_nix_mtu_set,\n \t.mac_addr_add             = otx2_nix_mac_addr_add,\n \t.mac_addr_remove          = otx2_nix_mac_addr_del,\n \t.mac_addr_set             = otx2_nix_mac_addr_set,\ndiff --git a/drivers/net/octeontx2/otx2_ethdev.h b/drivers/net/octeontx2/otx2_ethdev.h\nindex dff4de250..862a1ccbb 100644\n--- a/drivers/net/octeontx2/otx2_ethdev.h\n+++ b/drivers/net/octeontx2/otx2_ethdev.h\n@@ -351,6 +351,10 @@ int otx2_nix_tx_queue_start(struct rte_eth_dev *eth_dev, uint16_t qidx);\n int otx2_nix_tx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t qidx);\n uint64_t otx2_nix_rxq_mbuf_setup(struct otx2_eth_dev *dev, uint16_t port_id);\n \n+/* MTU */\n+int otx2_nix_mtu_set(struct rte_eth_dev *eth_dev, uint16_t mtu);\n+int otx2_nix_recalc_mtu(struct rte_eth_dev *eth_dev);\n+\n /* Link */\n void otx2_nix_toggle_flag_link_cfg(struct otx2_eth_dev *dev, bool set);\n int otx2_nix_link_update(struct rte_eth_dev *eth_dev, int wait_to_complete);\ndiff --git a/drivers/net/octeontx2/otx2_ethdev_ops.c b/drivers/net/octeontx2/otx2_ethdev_ops.c\nindex d2cb5ba1c..e8959e179 100644\n--- a/drivers/net/octeontx2/otx2_ethdev_ops.c\n+++ b/drivers/net/octeontx2/otx2_ethdev_ops.c\n@@ -6,6 +6,86 @@\n \n #include \"otx2_ethdev.h\"\n \n+int\n+otx2_nix_mtu_set(struct rte_eth_dev *eth_dev, uint16_t mtu)\n+{\n+\tuint32_t buffsz, frame_size = mtu + NIX_HW_L2_OVERHEAD;\n+\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n+\tstruct rte_eth_dev_data *data = eth_dev->data;\n+\tstruct otx2_mbox *mbox = dev->mbox;\n+\tstruct nix_frs_cfg *req;\n+\tint rc;\n+\n+\t/* Check if MTU is within the allowed range */\n+\tif (frame_size < NIX_MIN_HW_FRS || frame_size > NIX_MAX_HW_FRS)\n+\t\treturn -EINVAL;\n+\n+\tbuffsz = data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM;\n+\n+\t/* Refuse MTU that requires the support of scattered packets\n+\t * when this feature has not been enabled before.\n+\t */\n+\tif (data->dev_started && frame_size > buffsz &&\n+\t    !(dev->rx_offloads & DEV_RX_OFFLOAD_SCATTER))\n+\t\treturn -EINVAL;\n+\n+\t/* Check <seg size> * <max_seg>  >= max_frame */\n+\tif ((dev->rx_offloads & DEV_RX_OFFLOAD_SCATTER)\t&&\n+\t    (frame_size > buffsz * NIX_RX_NB_SEG_MAX))\n+\t\treturn -EINVAL;\n+\n+\treq = otx2_mbox_alloc_msg_nix_set_hw_frs(mbox);\n+\treq->update_smq = true;\n+\treq->maxlen = frame_size;\n+\n+\trc = otx2_mbox_process(mbox);\n+\tif (rc)\n+\t\treturn rc;\n+\n+\tif (frame_size > RTE_ETHER_MAX_LEN)\n+\t\tdev->rx_offloads |= DEV_RX_OFFLOAD_JUMBO_FRAME;\n+\telse\n+\t\tdev->rx_offloads &= ~DEV_RX_OFFLOAD_JUMBO_FRAME;\n+\n+\t/* Update max_rx_pkt_len */\n+\tdata->dev_conf.rxmode.max_rx_pkt_len = frame_size;\n+\n+\treturn rc;\n+}\n+\n+int\n+otx2_nix_recalc_mtu(struct rte_eth_dev *eth_dev)\n+{\n+\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n+\tstruct rte_eth_dev_data *data = eth_dev->data;\n+\tstruct rte_pktmbuf_pool_private *mbp_priv;\n+\tstruct otx2_eth_rxq *rxq;\n+\tuint32_t buffsz;\n+\tuint16_t mtu;\n+\tint rc;\n+\n+\t/* Get rx buffer size */\n+\trxq = data->rx_queues[0];\n+\tmbp_priv = rte_mempool_get_priv(rxq->pool);\n+\tbuffsz = mbp_priv->mbuf_data_room_size - RTE_PKTMBUF_HEADROOM;\n+\n+\t/* Setup scatter mode if needed by jumbo */\n+\tif (data->dev_conf.rxmode.max_rx_pkt_len > buffsz)\n+\t\tdev->rx_offloads |= DEV_RX_OFFLOAD_SCATTER;\n+\n+\t/* Setup MTU based on max_rx_pkt_len or default */\n+\tmtu = ((dev->rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) ||\n+\t\t(data->dev_conf.rxmode.max_rx_pkt_len < RTE_ETHER_MAX_LEN)) ?\n+\t\tdata->dev_conf.rxmode.max_rx_pkt_len - NIX_HW_L2_OVERHEAD :\n+\t\tRTE_ETHER_MTU;\n+\n+\trc = otx2_nix_mtu_set(eth_dev, mtu);\n+\tif (rc)\n+\t\totx2_err(\"Failed to set default MTU size %d\", rc);\n+\n+\treturn rc;\n+}\n+\n static void\n nix_cgx_promisc_config(struct rte_eth_dev *eth_dev, int en)\n {\n",
    "prefixes": [
        "v1",
        "57/58"
    ]
}