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GET /api/patches/54092/?format=api
{ "id": 54092, "url": "http://patches.dpdk.org/api/patches/54092/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20190602152434.23996-50-jerinj@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20190602152434.23996-50-jerinj@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20190602152434.23996-50-jerinj@marvell.com", "date": "2019-06-02T15:24:25", "name": "[v1,49/58] net/octeontx2: add Rx burst support", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "c5f3de15a4f8add54c0448ec49d231625e8fbe9b", "submitter": { "id": 1188, "url": "http://patches.dpdk.org/api/people/1188/?format=api", "name": "Jerin Jacob Kollanukkaran", "email": "jerinj@marvell.com" }, "delegate": { "id": 319, "url": "http://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20190602152434.23996-50-jerinj@marvell.com/mbox/", "series": [ { "id": 4848, "url": "http://patches.dpdk.org/api/series/4848/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=4848", "date": "2019-06-02T15:23:36", "name": "OCTEON TX2 Ethdev driver", "version": 1, "mbox": "http://patches.dpdk.org/series/4848/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/54092/comments/", "check": "fail", "checks": "http://patches.dpdk.org/api/patches/54092/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 119FB1B9BC;\n\tSun, 2 Jun 2019 17:27:10 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n\t[67.231.156.173]) by dpdk.org (Postfix) with ESMTP id 64AE11B9EB\n\tfor <dev@dpdk.org>; Sun, 2 Jun 2019 17:27:08 +0200 (CEST)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n\tby mx0b-0016f401.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id\n\tx52FK6ke020260; Sun, 2 Jun 2019 08:27:07 -0700", "from sc-exch02.marvell.com ([199.233.58.182])\n\tby mx0b-0016f401.pphosted.com with ESMTP id 2survk499t-1\n\t(version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); \n\tSun, 02 Jun 2019 08:27:07 -0700", "from SC-EXCH03.marvell.com (10.93.176.83) by SC-EXCH02.marvell.com\n\t(10.93.176.82) with Microsoft SMTP Server (TLS) id 15.0.1367.3;\n\tSun, 2 Jun 2019 08:27:06 -0700", "from maili.marvell.com (10.93.176.43) by SC-EXCH03.marvell.com\n\t(10.93.176.83) with Microsoft SMTP Server id 15.0.1367.3 via Frontend\n\tTransport; Sun, 2 Jun 2019 08:27:06 -0700", "from jerin-lab.marvell.com (jerin-lab.marvell.com [10.28.34.14])\n\tby maili.marvell.com (Postfix) with ESMTP id 85D0B3F7040;\n\tSun, 2 Jun 2019 08:27:04 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n\th=from : to : cc :\n\tsubject : date : message-id : in-reply-to : references : mime-version\n\t: content-transfer-encoding : content-type; s=pfpt0818;\n\tbh=JMmwHsuWSsBgefd9k5yb9julsA9eb+Y2oaX1uHwQKqo=;\n\tb=ViLjmIc0jtW3/7cNhUmveAZIHpHq5oLw0WzQsLGWvbJki0GsUYSCjC+PSZYKH8cVCYGs\n\tKLtWkUgV7DWHNy2N50/Qw6zLKV5uW32QhdUSQuJV/5ZESMODkniWNh750dqNFZww/IIb\n\thh8iMD+JBI4wYHXfcOqcau8H64fD8VkuOt0gFvJo6/8Xqyt5IKrfdgc1fdCg23qwTEqf\n\tk4BgN5rkjFb1+UMZB5n4ObkV5acomcqRpnV/WkwOrooInPnE5nxU+R/AeCgKyMK2Fomc\n\tJBpVFWQJ5UhezDWUO6FgiAApW5zBaX1me4rzG5JVmBfNHM8GesdwTBIi0W9KRmhyHgvP\n\t3w== ", "From": "<jerinj@marvell.com>", "To": "<dev@dpdk.org>, Jerin Jacob <jerinj@marvell.com>, Nithin Dabilpuram\n\t<ndabilpuram@marvell.com>, Kiran Kumar K <kirankumark@marvell.com>", "CC": "<ferruh.yigit@intel.com>, Pavan Nikhilesh <pbhagavatula@marvell.com>,\n\tHarman Kalra <hkalra@marvell.com>", "Date": "Sun, 2 Jun 2019 20:54:25 +0530", "Message-ID": "<20190602152434.23996-50-jerinj@marvell.com>", "X-Mailer": "git-send-email 2.21.0", "In-Reply-To": "<20190602152434.23996-1-jerinj@marvell.com>", "References": "<20190602152434.23996-1-jerinj@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:, ,\n\tdefinitions=2019-06-02_09:, , signatures=0", "Subject": "[dpdk-dev] [PATCH v1 49/58] net/octeontx2: add Rx burst support", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Jerin Jacob <jerinj@marvell.com>\n\nAdd Rx burst support.\n\nSigned-off-by: Jerin Jacob <jerinj@marvell.com>\nSigned-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>\nSigned-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>\nSigned-off-by: Harman Kalra <hkalra@marvell.com>\n---\n drivers/net/octeontx2/Makefile | 1 +\n drivers/net/octeontx2/meson.build | 2 +-\n drivers/net/octeontx2/otx2_ethdev.c | 6 -\n drivers/net/octeontx2/otx2_ethdev.h | 2 +\n drivers/net/octeontx2/otx2_rx.c | 128 ++++++++++++++\n drivers/net/octeontx2/otx2_rx.h | 249 +++++++++++++++++++++++++++-\n 6 files changed, 380 insertions(+), 8 deletions(-)\n create mode 100644 drivers/net/octeontx2/otx2_rx.c", "diff": "diff --git a/drivers/net/octeontx2/Makefile b/drivers/net/octeontx2/Makefile\nindex b1cc6d83b..76847b2c2 100644\n--- a/drivers/net/octeontx2/Makefile\n+++ b/drivers/net/octeontx2/Makefile\n@@ -30,6 +30,7 @@ LIBABIVER := 1\n # all source are stored in SRCS-y\n #\n SRCS-$(CONFIG_RTE_LIBRTE_OCTEONTX2_PMD) += \\\n+\totx2_rx.c \t\\\n \totx2_tm.c\t\\\n \totx2_rss.c\t\\\n \totx2_mac.c\t\\\ndiff --git a/drivers/net/octeontx2/meson.build b/drivers/net/octeontx2/meson.build\nindex d5f272c8b..1361f1707 100644\n--- a/drivers/net/octeontx2/meson.build\n+++ b/drivers/net/octeontx2/meson.build\n@@ -2,7 +2,7 @@\n # Copyright(C) 2019 Marvell International Ltd.\n #\n \n-sources = files(\n+sources = files('otx2_rx.c',\n \t\t'otx2_tm.c',\n \t\t'otx2_rss.c',\n \t\t'otx2_mac.c',\ndiff --git a/drivers/net/octeontx2/otx2_ethdev.c b/drivers/net/octeontx2/otx2_ethdev.c\nindex b449bb032..9b55e757e 100644\n--- a/drivers/net/octeontx2/otx2_ethdev.c\n+++ b/drivers/net/octeontx2/otx2_ethdev.c\n@@ -14,12 +14,6 @@\n \n #include \"otx2_ethdev.h\"\n \n-static inline void\n-otx2_eth_set_rx_function(struct rte_eth_dev *eth_dev)\n-{\n-\tRTE_SET_USED(eth_dev);\n-}\n-\n static inline void\n otx2_eth_set_tx_function(struct rte_eth_dev *eth_dev)\n {\ndiff --git a/drivers/net/octeontx2/otx2_ethdev.h b/drivers/net/octeontx2/otx2_ethdev.h\nindex 7bb42be8d..3ba47f6ab 100644\n--- a/drivers/net/octeontx2/otx2_ethdev.h\n+++ b/drivers/net/octeontx2/otx2_ethdev.h\n@@ -259,6 +259,7 @@ struct otx2_eth_dev {\n \tstruct otx2_eth_qconf *tx_qconf;\n \tstruct otx2_eth_qconf *rx_qconf;\n \tstruct rte_eth_dev *eth_dev;\n+\teth_rx_burst_t rx_pkt_burst_no_offload;\n \t/* PTP counters */\n \tbool ptp_en;\n \tstruct otx2_timesync_info tstamp;\n@@ -451,6 +452,7 @@ int otx2_ethdev_parse_devargs(struct rte_devargs *devargs,\n \t\t\t struct otx2_eth_dev *dev);\n \n /* Rx and Tx routines */\n+void otx2_eth_set_rx_function(struct rte_eth_dev *eth_dev);\n void otx2_nix_form_default_desc(struct otx2_eth_txq *txq);\n \n /* Timesync - PTP routines */\ndiff --git a/drivers/net/octeontx2/otx2_rx.c b/drivers/net/octeontx2/otx2_rx.c\nnew file mode 100644\nindex 000000000..b4a3e9d55\n--- /dev/null\n+++ b/drivers/net/octeontx2/otx2_rx.c\n@@ -0,0 +1,128 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2019 Marvell International Ltd.\n+ */\n+\n+#include <rte_vect.h>\n+\n+#include \"otx2_ethdev.h\"\n+#include \"otx2_rx.h\"\n+\n+#define NIX_DESCS_PER_LOOP\t4\n+#define CQE_CAST(x)\t\t((struct nix_cqe_hdr_s *)(x))\n+#define CQE_SZ(x)\t\t((x) * NIX_CQ_ENTRY_SZ)\n+\n+static inline uint16_t\n+nix_rx_nb_pkts(struct otx2_eth_rxq *rxq, const uint64_t wdata,\n+\t const uint16_t pkts, const uint32_t qmask)\n+{\n+\tuint32_t available = rxq->available;\n+\n+\t/* Update the available count if cached value is not enough */\n+\tif (unlikely(available < pkts)) {\n+\t\tuint64_t reg, head, tail;\n+\n+\t\t/* Use LDADDA version to avoid reorder */\n+\t\treg = otx2_atomic64_add_sync(wdata, rxq->cq_status);\n+\t\t/* CQ_OP_STATUS operation error */\n+\t\tif (reg & BIT_ULL(CQ_OP_STAT_OP_ERR) ||\n+\t\t reg & BIT_ULL(CQ_OP_STAT_CQ_ERR))\n+\t\t\treturn 0;\n+\n+\t\ttail = reg & 0xFFFFF;\n+\t\thead = (reg >> 20) & 0xFFFFF;\n+\t\tif (tail < head)\n+\t\t\tavailable = tail - head + qmask + 1;\n+\t\telse\n+\t\t\tavailable = tail - head;\n+\n+\t\trxq->available = available;\n+\t}\n+\n+\treturn RTE_MIN(pkts, available);\n+}\n+\n+static __rte_always_inline uint16_t\n+nix_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,\n+\t uint16_t pkts, const uint16_t flags)\n+{\n+\tstruct otx2_eth_rxq *rxq = rx_queue;\n+\tconst uint64_t mbuf_init = rxq->mbuf_initializer;\n+\tconst void *lookup_mem = rxq->lookup_mem;\n+\tconst uint64_t data_off = rxq->data_off;\n+\tconst uintptr_t desc = rxq->desc;\n+\tconst uint64_t wdata = rxq->wdata;\n+\tconst uint32_t qmask = rxq->qmask;\n+\tuint16_t packets = 0, nb_pkts;\n+\tuint32_t head = rxq->head;\n+\tstruct nix_cqe_hdr_s *cq;\n+\tstruct rte_mbuf *mbuf;\n+\n+\tnb_pkts = nix_rx_nb_pkts(rxq, wdata, pkts, qmask);\n+\n+\twhile (packets < nb_pkts) {\n+\t\t/* Prefetch N desc ahead */\n+\t\trte_prefetch_non_temporal((void *)(desc + (CQE_SZ(head + 2))));\n+\t\tcq = (struct nix_cqe_hdr_s *)(desc + CQE_SZ(head));\n+\n+\t\tmbuf = nix_get_mbuf_from_cqe(cq, data_off);\n+\n+\t\totx2_nix_cqe_to_mbuf(cq, mbuf, lookup_mem, mbuf_init, flags);\n+\t\totx2_nix_mbuf_to_tstamp(mbuf, rxq->tstamp, flags);\n+\t\trx_pkts[packets++] = mbuf;\n+\t\totx2_prefetch_store_keep(mbuf);\n+\t\thead++;\n+\t\thead &= qmask;\n+\t}\n+\n+\trxq->head = head;\n+\trxq->available -= nb_pkts;\n+\n+\t/* Free all the CQs that we've processed */\n+\totx2_write64((wdata | nb_pkts), rxq->cq_door);\n+\n+\treturn nb_pkts;\n+}\n+\n+\n+#define R(name, f5, f4, f3, f2, f1, f0, flags)\t\t\t\t\\\n+static uint16_t __rte_noinline\t__hot\t\t\t\t\t \\\n+otx2_nix_recv_pkts_ ## name(void *rx_queue,\t\t\t\t \\\n+\t\t\tstruct rte_mbuf **rx_pkts, uint16_t pkts)\t \\\n+{\t\t\t\t\t\t\t\t\t \\\n+\treturn nix_recv_pkts(rx_queue, rx_pkts, pkts, (flags));\t\t \\\n+}\t\t\t\t\t\t\t\t\t \\\n+\n+NIX_RX_FASTPATH_MODES\n+#undef R\n+\n+static inline void\n+pick_rx_func(struct rte_eth_dev *eth_dev,\n+\t const eth_rx_burst_t rx_burst[2][2][2][2][2][2])\n+{\n+\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n+\n+\t/* [TSTMP] [MARK] [VLAN] [CKSUM] [PTYPE] [RSS] */\n+\teth_dev->rx_pkt_burst = rx_burst\n+\t\t[!!(dev->rx_offload_flags & NIX_RX_OFFLOAD_TSTAMP_F)]\n+\t\t[!!(dev->rx_offload_flags & NIX_RX_OFFLOAD_MARK_UPDATE_F)]\n+\t\t[!!(dev->rx_offload_flags & NIX_RX_OFFLOAD_VLAN_STRIP_F)]\n+\t\t[!!(dev->rx_offload_flags & NIX_RX_OFFLOAD_CHECKSUM_F)]\n+\t\t[!!(dev->rx_offload_flags & NIX_RX_OFFLOAD_PTYPE_F)]\n+\t\t[!!(dev->rx_offload_flags & NIX_RX_OFFLOAD_RSS_F)];\n+}\n+\n+void\n+otx2_eth_set_rx_function(struct rte_eth_dev *eth_dev)\n+{\n+\tconst eth_rx_burst_t nix_eth_rx_burst[2][2][2][2][2][2] = {\n+#define R(name, f5, f4, f3, f2, f1, f0, flags)\t\t\t\t\\\n+\t[f5][f4][f3][f2][f1][f0] = otx2_nix_recv_pkts_ ## name,\n+\n+NIX_RX_FASTPATH_MODES\n+#undef R\n+\t};\n+\n+\tpick_rx_func(eth_dev, nix_eth_rx_burst);\n+\n+\trte_mb();\n+}\ndiff --git a/drivers/net/octeontx2/otx2_rx.h b/drivers/net/octeontx2/otx2_rx.h\nindex 763dc402e..fc0e87d14 100644\n--- a/drivers/net/octeontx2/otx2_rx.h\n+++ b/drivers/net/octeontx2/otx2_rx.h\n@@ -15,10 +15,13 @@\n \t\t\t\t\t PTYPE_TUNNEL_ARRAY_SZ) *\\\n \t\t\t\t\t sizeof(uint16_t))\n \n+#define NIX_RX_OFFLOAD_NONE (0)\n+#define NIX_RX_OFFLOAD_RSS_F BIT(0)\n #define NIX_RX_OFFLOAD_PTYPE_F BIT(1)\n+#define NIX_RX_OFFLOAD_CHECKSUM_F BIT(2)\n #define NIX_RX_OFFLOAD_VLAN_STRIP_F BIT(3)\n-#define NIX_RX_OFFLOAD_TSTAMP_F BIT(5)\n #define NIX_RX_OFFLOAD_MARK_UPDATE_F BIT(4)\n+#define NIX_RX_OFFLOAD_TSTAMP_F BIT(5)\n \n #define NIX_TIMESYNC_RX_OFFSET\t\t8\n \n@@ -30,4 +33,248 @@ struct otx2_timesync_info {\n \tuint8_t\t\trx_ready;\n } __rte_cache_aligned;\n \n+union mbuf_initializer {\n+\tstruct {\n+\t\tuint16_t data_off;\n+\t\tuint16_t refcnt;\n+\t\tuint16_t nb_segs;\n+\t\tuint16_t port;\n+\t} fields;\n+\tuint64_t value;\n+};\n+\n+static __rte_always_inline void\n+otx2_nix_mbuf_to_tstamp(struct rte_mbuf *mbuf,\n+\t\t\tstruct otx2_timesync_info *tstamp, const uint16_t flag)\n+{\n+\tif ((flag & NIX_RX_OFFLOAD_TSTAMP_F) &&\n+\t mbuf->packet_type == RTE_PTYPE_L2_ETHER_TIMESYNC &&\n+\t (mbuf->data_off == RTE_PKTMBUF_HEADROOM +\n+\t NIX_TIMESYNC_RX_OFFSET)) {\n+\t\tuint64_t *tstamp_ptr;\n+\n+\t\t/* Deal with rx timestamp */\n+\t\ttstamp_ptr = rte_pktmbuf_mtod_offset(mbuf, uint64_t *,\n+\t\t\t\t\t\t -NIX_TIMESYNC_RX_OFFSET);\n+\t\tmbuf->timestamp = rte_be_to_cpu_64(*tstamp_ptr);\n+\t\ttstamp->rx_tstamp = mbuf->timestamp;\n+\t\ttstamp->rx_ready = 1;\n+\t\tmbuf->ol_flags |= PKT_RX_IEEE1588_PTP | PKT_RX_IEEE1588_TMST\n+\t\t\t| PKT_RX_TIMESTAMP;\n+\t}\n+}\n+\n+static __rte_always_inline uint64_t\n+nix_clear_data_off(uint64_t oldval)\n+{\n+\tunion mbuf_initializer mbuf_init = { .value = oldval };\n+\n+\tmbuf_init.fields.data_off = 0;\n+\treturn mbuf_init.value;\n+}\n+\n+static __rte_always_inline struct rte_mbuf *\n+nix_get_mbuf_from_cqe(void *cq, const uint64_t data_off)\n+{\n+\trte_iova_t buff;\n+\n+\t/* Skip CQE, NIX_RX_PARSE_S and SG HDR(9 DWORDs) and peek buff addr */\n+\tbuff = *((rte_iova_t *)((uint64_t *)cq + 9));\n+\treturn (struct rte_mbuf *)(buff - data_off);\n+}\n+\n+\n+static __rte_always_inline uint32_t\n+nix_ptype_get(const void * const lookup_mem, const uint64_t in)\n+{\n+\tconst uint16_t * const ptype = lookup_mem;\n+\tconst uint16_t lg_lf_le = (in & 0xFFF000000000000) >> 48;\n+\tconst uint16_t tu_l2 = ptype[(in & 0x000FFF000000000) >> 36];\n+\tconst uint16_t il4_tu = ptype[PTYPE_NON_TUNNEL_ARRAY_SZ + lg_lf_le];\n+\n+\treturn (il4_tu << PTYPE_WIDTH) | tu_l2;\n+}\n+\n+static __rte_always_inline uint32_t\n+nix_rx_olflags_get(const void * const lookup_mem, const uint64_t in)\n+{\n+\tconst uint32_t * const ol_flags = (const uint32_t * const)\n+\t\t\t((const uint8_t * const)lookup_mem + PTYPE_ARRAY_SZ);\n+\n+\treturn ol_flags[(in & 0xfff00000) >> 20];\n+}\n+\n+static inline uint64_t\n+nix_update_match_id(const uint16_t match_id, uint64_t ol_flags,\n+\t\t struct rte_mbuf *mbuf)\n+{\n+\t/* There is no separate bit to check match_id\n+\t * is valid or not? and no flag to identify it is an\n+\t * RTE_FLOW_ACTION_TYPE_FLAG vs RTE_FLOW_ACTION_TYPE_MARK\n+\t * action. The former case addressed through 0 being invalid\n+\t * value and inc/dec match_id pair when MARK is activated.\n+\t * The later case addressed through defining\n+\t * OTX2_FLOW_MARK_DEFAULT as value for\n+\t * RTE_FLOW_ACTION_TYPE_MARK.\n+\t * This would translate to not use\n+\t * OTX2_FLOW_ACTION_FLAG_DEFAULT - 1 and\n+\t * OTX2_FLOW_ACTION_FLAG_DEFAULT for match_id.\n+\t * i.e valid mark_id's are from\n+\t * 0 to OTX2_FLOW_ACTION_FLAG_DEFAULT - 2\n+\t */\n+\tif (likely(match_id)) {\n+\t\tol_flags |= PKT_RX_FDIR;\n+\t\tif (match_id != OTX2_FLOW_ACTION_FLAG_DEFAULT) {\n+\t\t\tol_flags |= PKT_RX_FDIR_ID;\n+\t\t\tmbuf->hash.fdir.hi = match_id - 1;\n+\t\t}\n+\t}\n+\n+\treturn ol_flags;\n+}\n+\n+static __rte_always_inline void\n+otx2_nix_cqe_to_mbuf(const struct nix_cqe_hdr_s *cq, struct rte_mbuf *mbuf,\n+\t\t const void *lookup_mem, const uint64_t val,\n+\t\t const uint16_t flag)\n+{\n+\tconst struct nix_rx_parse_s *rx =\n+\t\t (const struct nix_rx_parse_s *)((const uint64_t *)cq + 1);\n+\tconst uint64_t w1 = *(const uint64_t *)rx;\n+\tconst uint16_t len = rx->pkt_lenm1 + 1;\n+\tuint16_t ol_flags = 0;\n+\n+\t/* Mark mempool obj as \"get\" as it is alloc'ed by NIX */\n+\t__mempool_check_cookies(mbuf->pool, (void **)&mbuf, 1, 1);\n+\n+\tif (flag & NIX_RX_OFFLOAD_PTYPE_F)\n+\t\tmbuf->packet_type = nix_ptype_get(lookup_mem, w1);\n+\telse\n+\t\tmbuf->packet_type = 0;\n+\n+\tif (flag & NIX_RX_OFFLOAD_RSS_F) {\n+\t\tmbuf->hash.rss = cq->tag;\n+\t\tol_flags |= PKT_RX_RSS_HASH;\n+\t}\n+\n+\tif (flag & NIX_RX_OFFLOAD_CHECKSUM_F)\n+\t\tol_flags |= nix_rx_olflags_get(lookup_mem, w1);\n+\n+\tif (flag & NIX_RX_OFFLOAD_VLAN_STRIP_F) {\n+\t\tif (rx->vtag0_gone) {\n+\t\t\tol_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;\n+\t\t\tmbuf->vlan_tci = rx->vtag0_tci;\n+\t\t}\n+\t\tif (rx->vtag1_gone) {\n+\t\t\tol_flags |= PKT_RX_QINQ | PKT_RX_QINQ_STRIPPED;\n+\t\t\tmbuf->vlan_tci_outer = rx->vtag1_tci;\n+\t\t}\n+\t}\n+\n+\tif (flag & NIX_RX_OFFLOAD_MARK_UPDATE_F)\n+\t\tol_flags = nix_update_match_id(rx->match_id, ol_flags, mbuf);\n+\n+\tmbuf->ol_flags = ol_flags;\n+\t*(uint64_t *)(&mbuf->rearm_data) = val;\n+\tmbuf->pkt_len = len;\n+\n+\tmbuf->data_len = len;\n+}\n+\n+#define CKSUM_F NIX_RX_OFFLOAD_CHECKSUM_F\n+#define PTYPE_F NIX_RX_OFFLOAD_PTYPE_F\n+#define RSS_F\tNIX_RX_OFFLOAD_RSS_F\n+#define RX_VLAN_F NIX_RX_OFFLOAD_VLAN_STRIP_F\n+#define MARK_F NIX_RX_OFFLOAD_MARK_UPDATE_F\n+#define TS_F\tNIX_RX_OFFLOAD_TSTAMP_F\n+\n+/* [TSMP] [MARK] [VLAN] [CKSUM] [PTYPE] [RSS] */\n+#define NIX_RX_FASTPATH_MODES\t\t\t\t\t\t \\\n+R(no_offload,\t\t\t0, 0, 0, 0, 0, 0, NIX_RX_OFFLOAD_NONE)\t\\\n+R(rss,\t\t\t\t0, 0, 0, 0, 0, 1, RSS_F)\t\t\\\n+R(ptype,\t\t\t0, 0, 0, 0, 1, 0, PTYPE_F)\t\t\\\n+R(ptype_rss,\t\t\t0, 0, 0, 0, 1, 1, PTYPE_F | RSS_F)\t\\\n+R(cksum,\t\t\t0, 0, 0, 1, 0, 0, CKSUM_F)\t\t\\\n+R(cksum_rss,\t\t\t0, 0, 0, 1, 0, 1, CKSUM_F | RSS_F)\t\\\n+R(cksum_ptype,\t\t\t0, 0, 0, 1, 1, 0, CKSUM_F | PTYPE_F)\t\\\n+R(cksum_ptype_rss,\t\t0, 0, 0, 1, 1, 1, CKSUM_F | PTYPE_F | RSS_F)\\\n+R(vlan,\t\t\t\t0, 0, 1, 0, 0, 0, RX_VLAN_F)\t\t\\\n+R(vlan_rss,\t\t\t0, 0, 1, 0, 0, 1, RX_VLAN_F | RSS_F)\t\\\n+R(vlan_ptype,\t\t\t0, 0, 1, 0, 1, 0, RX_VLAN_F | PTYPE_F)\t\\\n+R(vlan_ptype_rss,\t\t0, 0, 1, 0, 1, 1, RX_VLAN_F | PTYPE_F | RSS_F)\\\n+R(vlan_cksum,\t\t\t0, 0, 1, 1, 0, 0, RX_VLAN_F | CKSUM_F)\t\\\n+R(vlan_cksum_rss,\t\t0, 0, 1, 1, 0, 1, RX_VLAN_F | CKSUM_F | RSS_F)\\\n+R(vlan_cksum_ptype,\t\t0, 0, 1, 1, 1, 0,\t\t\t\\\n+\t\t\tRX_VLAN_F | CKSUM_F | PTYPE_F)\t\t\t\\\n+R(vlan_cksum_ptype_rss,\t\t0, 0, 1, 1, 1, 1,\t\t\t\\\n+\t\t\tRX_VLAN_F | CKSUM_F | PTYPE_F | RSS_F)\t\t\\\n+R(mark,\t\t\t\t0, 1, 0, 0, 0, 0, MARK_F)\t\t\\\n+R(mark_rss,\t\t\t0, 1, 0, 0, 0, 1, MARK_F | RSS_F)\t\\\n+R(mark_ptype,\t\t\t0, 1, 0, 0, 1, 0, MARK_F | PTYPE_F)\t\\\n+R(mark_ptype_rss,\t\t0, 1, 0, 0, 1, 1, MARK_F | PTYPE_F | RSS_F)\\\n+R(mark_cksum,\t\t\t0, 1, 0, 1, 0, 0, MARK_F | CKSUM_F)\t\\\n+R(mark_cksum_rss,\t\t0, 1, 0, 1, 0, 1, MARK_F | CKSUM_F | RSS_F)\\\n+R(mark_cksum_ptype,\t\t0, 1, 0, 1, 1, 0, MARK_F | CKSUM_F | PTYPE_F)\\\n+R(mark_cksum_ptype_rss,\t\t0, 1, 0, 1, 1, 1,\t\t\t\\\n+\t\t\tMARK_F | CKSUM_F | PTYPE_F | RSS_F)\t\t\\\n+R(mark_vlan,\t\t\t0, 1, 1, 0, 0, 0, MARK_F | RX_VLAN_F)\t\\\n+R(mark_vlan_rss,\t\t0, 1, 1, 0, 0, 1, MARK_F | RX_VLAN_F | RSS_F)\\\n+R(mark_vlan_ptype,\t\t0, 1, 1, 0, 1, 0,\t\t\t\\\n+\t\t\tMARK_F | RX_VLAN_F | PTYPE_F)\t\t\t\\\n+R(mark_vlan_ptype_rss,\t\t0, 1, 1, 0, 1, 1,\t\t\t\\\n+\t\t\tMARK_F | RX_VLAN_F | PTYPE_F | RSS_F)\t\t\\\n+R(mark_vlan_cksum,\t\t0, 1, 1, 1, 0, 0,\t\t\t\\\n+\t\t\tMARK_F | RX_VLAN_F | CKSUM_F)\t\t\t\\\n+R(mark_vlan_cksum_rss,\t\t0, 1, 1, 1, 0, 1,\t\t\t\\\n+\t\t\tMARK_F | RX_VLAN_F | CKSUM_F | RSS_F)\t\t\\\n+R(mark_vlan_cksum_ptype,\t0, 1, 1, 1, 1, 0,\t\t\t\\\n+\t\t\tMARK_F | RX_VLAN_F | CKSUM_F | PTYPE_F)\t\t\\\n+R(mark_vlan_cksum_ptype_rss,\t0, 1, 1, 1, 1, 1,\t\t\t\\\n+\t\t\tMARK_F | RX_VLAN_F | CKSUM_F | PTYPE_F | RSS_F)\t\\\n+R(ts,\t\t\t\t1, 0, 0, 0, 0, 0, TS_F)\t\t\t\\\n+R(ts_rss,\t\t\t1, 0, 0, 0, 0, 1, TS_F | RSS_F)\t\t\\\n+R(ts_ptype,\t\t\t1, 0, 0, 0, 1, 0, TS_F | PTYPE_F)\t\\\n+R(ts_ptype_rss,\t\t\t1, 0, 0, 0, 1, 1, TS_F | PTYPE_F | RSS_F)\\\n+R(ts_cksum,\t\t\t1, 0, 0, 1, 0, 0, TS_F | CKSUM_F)\t\\\n+R(ts_cksum_rss,\t\t\t1, 0, 0, 1, 0, 1, TS_F | CKSUM_F | RSS_F)\\\n+R(ts_cksum_ptype,\t\t1, 0, 0, 1, 1, 0, TS_F | CKSUM_F | PTYPE_F)\\\n+R(ts_cksum_ptype_rss,\t\t1, 0, 0, 1, 1, 1,\t\t\t\\\n+\t\t\tTS_F | CKSUM_F | PTYPE_F | RSS_F)\t\t\\\n+R(ts_vlan,\t\t\t1, 0, 1, 0, 0, 0, TS_F | RX_VLAN_F)\t\\\n+R(ts_vlan_rss,\t\t\t1, 0, 1, 0, 0, 1, TS_F | RX_VLAN_F | RSS_F)\\\n+R(ts_vlan_ptype,\t\t1, 0, 1, 0, 1, 0, TS_F | RX_VLAN_F | PTYPE_F)\\\n+R(ts_vlan_ptype_rss,\t\t1, 0, 1, 0, 1, 1,\t\t\t\\\n+\t\t\tTS_F | RX_VLAN_F | PTYPE_F | RSS_F)\t\t\\\n+R(ts_vlan_cksum,\t\t1, 0, 1, 1, 0, 0,\t\t\t\\\n+\t\t\tTS_F | RX_VLAN_F | CKSUM_F)\t\t\t\\\n+R(ts_vlan_cksum_rss,\t\t1, 0, 1, 1, 0, 1,\t\t\t\\\n+\t\t\tMARK_F | RX_VLAN_F | CKSUM_F | RSS_F)\t\t\\\n+R(ts_vlan_cksum_ptype,\t\t1, 0, 1, 1, 1, 0,\t\t\t\\\n+\t\t\tTS_F | RX_VLAN_F | CKSUM_F | PTYPE_F)\t\t\\\n+R(ts_vlan_cksum_ptype_rss,\t1, 0, 1, 1, 1, 1,\t\t\t\\\n+\t\t\tTS_F | RX_VLAN_F | CKSUM_F | PTYPE_F | RSS_F)\t\\\n+R(ts_mark,\t\t\t1, 1, 0, 0, 0, 0, TS_F | MARK_F)\t\\\n+R(ts_mark_rss,\t\t\t1, 1, 0, 0, 0, 1, TS_F | MARK_F | RSS_F)\\\n+R(ts_mark_ptype,\t\t1, 1, 0, 0, 1, 0, TS_F | MARK_F | PTYPE_F)\\\n+R(ts_mark_ptype_rss,\t\t1, 1, 0, 0, 1, 1,\t\t\t\\\n+\t\t\tTS_F | MARK_F | PTYPE_F | RSS_F)\t\t\\\n+R(ts_mark_cksum,\t\t1, 1, 0, 1, 0, 0, TS_F | MARK_F | CKSUM_F)\\\n+R(ts_mark_cksum_rss,\t\t1, 1, 0, 1, 0, 1,\t\t\t\\\n+\t\t\tTS_F | MARK_F | CKSUM_F | RSS_F)\\\n+R(ts_mark_cksum_ptype,\t\t1, 1, 0, 1, 1, 0,\t\t\t\\\n+\t\t\tTS_F | MARK_F | CKSUM_F | PTYPE_F)\t\t\\\n+R(ts_mark_cksum_ptype_rss,\t1, 1, 0, 1, 1, 1,\t\t\t\\\n+\t\t\tTS_F | MARK_F | CKSUM_F | PTYPE_F | RSS_F)\t\\\n+R(ts_mark_vlan,\t\t\t1, 1, 1, 0, 0, 0, TS_F | MARK_F | RX_VLAN_F)\\\n+R(ts_mark_vlan_rss,\t\t1, 1, 1, 0, 0, 1,\t\t\t\\\n+\t\t\tTS_F | MARK_F | RX_VLAN_F | RSS_F)\\\n+R(ts_mark_vlan_ptype,\t\t1, 1, 1, 0, 1, 0,\t\t\t\\\n+\t\t\tTS_F | MARK_F | RX_VLAN_F | PTYPE_F)\t\t\\\n+R(ts_mark_vlan_ptype_rss,\t1, 1, 1, 0, 1, 1,\t\t\t\\\n+\t\t\tTS_F | MARK_F | RX_VLAN_F | PTYPE_F | RSS_F)\t\\\n+R(ts_mark_vlan_cksum_ptype,\t1, 1, 1, 1, 1, 0,\t\t\t\\\n+\t\t\tTS_F | MARK_F | RX_VLAN_F | CKSUM_F | PTYPE_F)\t\\\n+R(ts_mark_vlan_cksum_ptype_rss,\t1, 1, 1, 1, 1, 1,\t\t\t\\\n+\t\t\tTS_F | MARK_F | RX_VLAN_F | CKSUM_F | PTYPE_F | RSS_F)\n+\n #endif /* __OTX2_RX_H__ */\n", "prefixes": [ "v1", "49/58" ] }