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GET /api/patches/54082/?format=api
{ "id": 54082, "url": "http://patches.dpdk.org/api/patches/54082/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20190602152434.23996-39-jerinj@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20190602152434.23996-39-jerinj@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20190602152434.23996-39-jerinj@marvell.com", "date": "2019-06-02T15:24:14", "name": "[v1,38/58] net/octeontx2: adding flow parsing for inner layers", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "ce1aec9e65b178431df5d32d1bd2b5652c8aa98c", "submitter": { "id": 1188, "url": "http://patches.dpdk.org/api/people/1188/?format=api", "name": "Jerin Jacob Kollanukkaran", "email": "jerinj@marvell.com" }, "delegate": { "id": 319, "url": "http://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20190602152434.23996-39-jerinj@marvell.com/mbox/", "series": [ { "id": 4848, "url": "http://patches.dpdk.org/api/series/4848/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=4848", "date": "2019-06-02T15:23:36", "name": "OCTEON TX2 Ethdev driver", "version": 1, "mbox": "http://patches.dpdk.org/series/4848/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/54082/comments/", "check": "fail", "checks": "http://patches.dpdk.org/api/patches/54082/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 234641BBD2;\n\tSun, 2 Jun 2019 17:26:38 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n\t[67.231.156.173]) by dpdk.org (Postfix) with ESMTP id BD5981B9A8\n\tfor <dev@dpdk.org>; Sun, 2 Jun 2019 17:26:33 +0200 (CEST)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n\tby mx0b-0016f401.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id\n\tx52FK7HB020263; Sun, 2 Jun 2019 08:26:33 -0700", "from sc-exch01.marvell.com ([199.233.58.181])\n\tby mx0b-0016f401.pphosted.com with ESMTP id 2survk4983-1\n\t(version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); \n\tSun, 02 Jun 2019 08:26:33 -0700", "from SC-EXCH01.marvell.com (10.93.176.81) by SC-EXCH01.marvell.com\n\t(10.93.176.81) with Microsoft SMTP Server (TLS) id 15.0.1367.3;\n\tSun, 2 Jun 2019 08:26:31 -0700", "from maili.marvell.com (10.93.176.43) by SC-EXCH01.marvell.com\n\t(10.93.176.81) with Microsoft SMTP Server id 15.0.1367.3 via Frontend\n\tTransport; Sun, 2 Jun 2019 08:26:31 -0700", "from jerin-lab.marvell.com (jerin-lab.marvell.com [10.28.34.14])\n\tby maili.marvell.com (Postfix) with ESMTP id 7879F3F703F;\n\tSun, 2 Jun 2019 08:26:30 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n\th=from : to : cc :\n\tsubject : date : message-id : in-reply-to : references : mime-version\n\t: content-transfer-encoding : content-type; s=pfpt0818;\n\tbh=dnzZsBI9vJWMbOAHEAGkKq5mg2VB0v4wv+6lG/2/aqE=;\n\tb=EB2a1vpEuporo46gjYDLwRwiJaqwUv1GBbAyCrFRN4yZPXkItCQzdyBmOj4c816oVHEE\n\tnRUVAqpM0Kl8U92FCoMbf/Z4e0YVrj9GTjHfOOsmlKehfdZ0mdUtVwwNze7yoB0wlImT\n\tk+5ALmucyUJ0cSCAinFLhP1zSp/a0JQctphG307FlVC+l6PMvWWznwHHQzdFWWKZaeWV\n\tgViwvoDy2DUY1w1q8hunLzm/o9XHxfp9CVhSsLJsRu6BieFmIqg2GbCvtoElh2qg6xWr\n\txRCsqagU7dDfwV8c4MgYzaQ8lwR3WmI6uJlpwPXIpmmnDaaSnK+gp6AZPHqM//kUAL32\n\tJw== ", "From": "<jerinj@marvell.com>", "To": "<dev@dpdk.org>, Jerin Jacob <jerinj@marvell.com>, Nithin Dabilpuram\n\t<ndabilpuram@marvell.com>, Kiran Kumar K <kirankumark@marvell.com>", "CC": "<ferruh.yigit@intel.com>", "Date": "Sun, 2 Jun 2019 20:54:14 +0530", "Message-ID": "<20190602152434.23996-39-jerinj@marvell.com>", "X-Mailer": "git-send-email 2.21.0", "In-Reply-To": "<20190602152434.23996-1-jerinj@marvell.com>", "References": "<20190602152434.23996-1-jerinj@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:, ,\n\tdefinitions=2019-06-02_09:, , signatures=0", "Subject": "[dpdk-dev] [PATCH v1 38/58] net/octeontx2: adding flow parsing for\n\tinner layers", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Kiran Kumar K <kirankumark@marvell.com>\n\nAdding functionality to parse inner layers from la to lc.\nThese will be used to parse inner layers L2, L3, L4 types.\n\nSigned-off-by: Kiran Kumar K <kirankumark@marvell.com>\n---\n drivers/net/octeontx2/otx2_flow_parse.c | 202 ++++++++++++++++++++++++\n 1 file changed, 202 insertions(+)", "diff": "diff --git a/drivers/net/octeontx2/otx2_flow_parse.c b/drivers/net/octeontx2/otx2_flow_parse.c\nindex 2d0fa439a..1351dff4c 100644\n--- a/drivers/net/octeontx2/otx2_flow_parse.c\n+++ b/drivers/net/octeontx2/otx2_flow_parse.c\n@@ -461,3 +461,205 @@ otx2_flow_parse_ld(struct otx2_parse_state *pst)\n \n \treturn otx2_flow_update_parse_state(pst, &info, lid, lt, lflags);\n }\n+\n+static inline void\n+flow_check_lc_ip_tunnel(struct otx2_parse_state *pst)\n+{\n+\tconst struct rte_flow_item *pattern = pst->pattern + 1;\n+\n+\tpattern = otx2_flow_skip_void_and_any_items(pattern);\n+\tif (pattern->type == RTE_FLOW_ITEM_TYPE_MPLS ||\n+\t pattern->type == RTE_FLOW_ITEM_TYPE_IPV4 ||\n+\t pattern->type == RTE_FLOW_ITEM_TYPE_IPV6)\n+\t\tpst->tunnel = 1;\n+}\n+\n+/* Outer IPv4, Outer IPv6, MPLS, ARP */\n+int\n+otx2_flow_parse_lc(struct otx2_parse_state *pst)\n+{\n+\tuint8_t hw_mask[NPC_MAX_EXTRACT_DATA_LEN];\n+\tstruct otx2_flow_item_info info;\n+\tint lid, lt;\n+\tint rc;\n+\n+\tif (pst->pattern->type == RTE_FLOW_ITEM_TYPE_MPLS)\n+\t\treturn otx2_flow_parse_lc_ld_mpls(pst, NPC_LID_LC);\n+\n+\tinfo.hw_mask = &hw_mask;\n+\tinfo.spec = NULL;\n+\tinfo.mask = NULL;\n+\tlid = NPC_LID_LC;\n+\n+\tswitch (pst->pattern->type) {\n+\tcase RTE_FLOW_ITEM_TYPE_IPV4:\n+\t\tlt = NPC_LT_LC_IP;\n+\t\tinfo.def_mask = &rte_flow_item_ipv4_mask;\n+\t\tinfo.len = sizeof(struct rte_flow_item_ipv4);\n+\t\tbreak;\n+\tcase RTE_FLOW_ITEM_TYPE_IPV6:\n+\t\tlid = NPC_LID_LC;\n+\t\tlt = NPC_LT_LC_IP6;\n+\t\tinfo.def_mask = &rte_flow_item_ipv6_mask;\n+\t\tinfo.len = sizeof(struct rte_flow_item_ipv6);\n+\t\tbreak;\n+\tcase RTE_FLOW_ITEM_TYPE_ARP_ETH_IPV4:\n+\t\tlt = NPC_LT_LC_ARP;\n+\t\tinfo.def_mask = &rte_flow_item_arp_eth_ipv4_mask;\n+\t\tinfo.len = sizeof(struct rte_flow_item_arp_eth_ipv4);\n+\t\tbreak;\n+\tdefault:\n+\t\t/* No match at this layer */\n+\t\treturn 0;\n+\t}\n+\n+\t/* Identify if IP tunnels MPLS or IPv4/v6 */\n+\tflow_check_lc_ip_tunnel(pst);\n+\n+\totx2_flow_get_hw_supp_mask(pst, &info, lid, lt);\n+\trc = otx2_flow_parse_item_basic(pst->pattern, &info, pst->error);\n+\tif (rc != 0)\n+\t\treturn rc;\n+\n+\treturn otx2_flow_update_parse_state(pst, &info, lid, lt, 0);\n+}\n+\n+/* VLAN, ETAG */\n+int\n+otx2_flow_parse_lb(struct otx2_parse_state *pst)\n+{\n+\tconst struct rte_flow_item *pattern = pst->pattern;\n+\tconst struct rte_flow_item *last_pattern;\n+\tchar hw_mask[NPC_MAX_EXTRACT_DATA_LEN];\n+\tstruct otx2_flow_item_info info;\n+\tint lid, lt, lflags;\n+\tint nr_vlans = 0;\n+\tint rc;\n+\n+\tinfo.spec = NULL;\n+\tinfo.mask = NULL;\n+\n+\tlid = NPC_LID_LB;\n+\tlflags = 0;\n+\tlast_pattern = pattern;\n+\n+\tif (pst->pattern->type == RTE_FLOW_ITEM_TYPE_VLAN) {\n+\t\t/* RTE vlan is either 802.1q or 802.1ad,\n+\t\t * this maps to either CTAG/STAG. We need to decide\n+\t\t * based on number of VLANS present. Matching is\n+\t\t * supported on first tag only.\n+\t\t */\n+\t\tinfo.def_mask = &rte_flow_item_vlan_mask;\n+\t\tinfo.hw_mask = NULL;\n+\t\tinfo.len = sizeof(struct rte_flow_item_vlan);\n+\n+\t\tpattern = pst->pattern;\n+\t\twhile (pattern->type == RTE_FLOW_ITEM_TYPE_VLAN) {\n+\t\t\tnr_vlans++;\n+\n+\t\t\t/* Basic validation of 2nd/3rd vlan item */\n+\t\t\tif (nr_vlans > 1) {\n+\t\t\t\totx2_npc_dbg(\"Vlans = %d\", nr_vlans);\n+\t\t\t\trc = otx2_flow_parse_item_basic(pattern, &info,\n+\t\t\t\t\t\t\t\tpst->error);\n+\t\t\t\tif (rc != 0)\n+\t\t\t\t\treturn rc;\n+\t\t\t}\n+\t\t\tlast_pattern = pattern;\n+\t\t\tpattern++;\n+\t\t\tpattern = otx2_flow_skip_void_and_any_items(pattern);\n+\t\t}\n+\n+\t\tswitch (nr_vlans) {\n+\t\tcase 1:\n+\t\t\tlt = NPC_LT_LB_CTAG;\n+\t\t\tbreak;\n+\t\tcase 2:\n+\t\t\tlt = NPC_LT_LB_STAG;\n+\t\t\tlflags = NPC_F_STAG_CTAG;\n+\t\t\tbreak;\n+\t\tcase 3:\n+\t\t\tlt = NPC_LT_LB_STAG;\n+\t\t\tlflags = NPC_F_STAG_STAG_CTAG;\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\trte_flow_error_set(pst->error, ENOTSUP,\n+\t\t\t\t\t RTE_FLOW_ERROR_TYPE_ITEM,\n+\t\t\t\t\t last_pattern,\n+\t\t\t\t\t \"more than 3 vlans not supported\");\n+\t\t\treturn -rte_errno;\n+\t\t}\n+\t} else if (pst->pattern->type == RTE_FLOW_ITEM_TYPE_E_TAG) {\n+\t\t/* we can support ETAG and match a subsequent CTAG\n+\t\t * without any matching support.\n+\t\t */\n+\t\tlt = NPC_LT_LB_ETAG;\n+\t\tlflags = 0;\n+\n+\t\tlast_pattern = pst->pattern;\n+\t\tpattern = otx2_flow_skip_void_and_any_items(pst->pattern + 1);\n+\t\tif (pattern->type == RTE_FLOW_ITEM_TYPE_VLAN) {\n+\t\t\tinfo.def_mask = &rte_flow_item_vlan_mask;\n+\t\t\t/* set supported mask to NULL for vlan tag */\n+\t\t\tinfo.hw_mask = NULL;\n+\t\t\tinfo.len = sizeof(struct rte_flow_item_vlan);\n+\t\t\trc = otx2_flow_parse_item_basic(pattern, &info,\n+\t\t\t\t\t\t\tpst->error);\n+\t\t\tif (rc != 0)\n+\t\t\t\treturn rc;\n+\n+\t\t\tlflags = NPC_F_ETAG_CTAG;\n+\t\t\tlast_pattern = pattern;\n+\t\t}\n+\n+\t\tinfo.def_mask = &rte_flow_item_e_tag_mask;\n+\t\tinfo.len = sizeof(struct rte_flow_item_e_tag);\n+\t} else {\n+\t\treturn 0;\n+\t}\n+\n+\tinfo.hw_mask = &hw_mask;\n+\tinfo.spec = NULL;\n+\tinfo.mask = NULL;\n+\totx2_flow_get_hw_supp_mask(pst, &info, lid, lt);\n+\n+\trc = otx2_flow_parse_item_basic(pst->pattern, &info, pst->error);\n+\tif (rc != 0)\n+\t\treturn rc;\n+\n+\t/* Point pattern to last item consumed */\n+\tpst->pattern = last_pattern;\n+\treturn otx2_flow_update_parse_state(pst, &info, lid, lt, lflags);\n+}\n+\n+int\n+otx2_flow_parse_la(struct otx2_parse_state *pst)\n+{\n+\tstruct rte_flow_item_eth hw_mask;\n+\tstruct otx2_flow_item_info info;\n+\tint lid, lt;\n+\tint rc;\n+\n+\t/* Identify the pattern type into lid, lt */\n+\tif (pst->pattern->type != RTE_FLOW_ITEM_TYPE_ETH)\n+\t\treturn 0;\n+\n+\tlid = NPC_LID_LA;\n+\tlt = NPC_LT_LA_ETHER;\n+\n+\t/* Prepare for parsing the item */\n+\tinfo.def_mask = &rte_flow_item_eth_mask;\n+\tinfo.hw_mask = &hw_mask;\n+\tinfo.len = sizeof(struct rte_flow_item_eth);\n+\totx2_flow_get_hw_supp_mask(pst, &info, lid, lt);\n+\tinfo.spec = NULL;\n+\tinfo.mask = NULL;\n+\n+\t/* Basic validation of item parameters */\n+\trc = otx2_flow_parse_item_basic(pst->pattern, &info, pst->error);\n+\tif (rc)\n+\t\treturn rc;\n+\n+\t/* Update pst if not validate only? clash check? */\n+\treturn otx2_flow_update_parse_state(pst, &info, lid, lt, 0);\n+}\n", "prefixes": [ "v1", "38/58" ] }