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GET /api/patches/54079/?format=api
{ "id": 54079, "url": "http://patches.dpdk.org/api/patches/54079/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20190602152434.23996-24-jerinj@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20190602152434.23996-24-jerinj@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20190602152434.23996-24-jerinj@marvell.com", "date": "2019-06-02T15:23:59", "name": "[v1,23/58] net/octeontx2: configure TM HW resources", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "9c792bd88eb47046bf7d0ce05b99707245ee8926", "submitter": { "id": 1188, "url": "http://patches.dpdk.org/api/people/1188/?format=api", "name": "Jerin Jacob Kollanukkaran", "email": "jerinj@marvell.com" }, "delegate": { "id": 319, "url": "http://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20190602152434.23996-24-jerinj@marvell.com/mbox/", "series": [ { "id": 4848, "url": "http://patches.dpdk.org/api/series/4848/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=4848", "date": "2019-06-02T15:23:36", "name": "OCTEON TX2 Ethdev driver", "version": 1, "mbox": "http://patches.dpdk.org/series/4848/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/54079/comments/", "check": "fail", "checks": "http://patches.dpdk.org/api/patches/54079/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 7BFC21B9F5;\n\tSun, 2 Jun 2019 17:25:49 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n\t[67.231.148.174]) by dpdk.org (Postfix) with ESMTP id D10751B9F4\n\tfor <dev@dpdk.org>; Sun, 2 Jun 2019 17:25:47 +0200 (CEST)", "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n\tby mx0a-0016f401.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id\n\tx52FJmwN021277; Sun, 2 Jun 2019 08:25:47 -0700", "from sc-exch04.marvell.com ([199.233.58.184])\n\tby mx0a-0016f401.pphosted.com with ESMTP id 2supqkvqgk-1\n\t(version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); \n\tSun, 02 Jun 2019 08:25:46 -0700", "from SC-EXCH03.marvell.com (10.93.176.83) by SC-EXCH04.marvell.com\n\t(10.93.176.84) with Microsoft SMTP Server (TLS) id 15.0.1367.3;\n\tSun, 2 Jun 2019 08:25:46 -0700", "from maili.marvell.com (10.93.176.43) by SC-EXCH03.marvell.com\n\t(10.93.176.83) with Microsoft SMTP Server id 15.0.1367.3 via Frontend\n\tTransport; Sun, 2 Jun 2019 08:25:46 -0700", "from jerin-lab.marvell.com (jerin-lab.marvell.com [10.28.34.14])\n\tby maili.marvell.com (Postfix) with ESMTP id A03CA3F703F;\n\tSun, 2 Jun 2019 08:25:44 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n\th=from : to : cc :\n\tsubject : date : message-id : in-reply-to : references : mime-version\n\t: content-transfer-encoding : content-type; s=pfpt0818;\n\tbh=7wEtV/VJ5MBWwSqspU14lupfJwTjPkQFX/L7glJlQog=;\n\tb=lHv4sh8Jp/Nsu1vTN8yGOmLtsdFZMz02nCm0QKXg4M4kCFBNY1mSLOyJAefrYVbZvt4h\n\t7oP1FtYF3mxEOe2P36mf6yb/N21sUuJhI8B+cLOZ1lV/fwUW1eUipr8k2v4jZ1KNyho7\n\tlkqz9AkesdttLMLXRVGYa56b4XWx+PNLZN9sT/qFgbMY13aElDsx0gNEHggCJs+5oRJ1\n\t8Qn6XiaCCm+ood0TKNIi1V9PdnzcA5ooTLUJHbar6QaS9E1O6GwM8IvDnqZDMF85T7EF\n\tniuTELSLHHAVPC9jufkZxnshJA6WvVxqXhHgFVo5N2AexonJWtiDwHIrHqNXGX7hhikK\n\tKg== ", "From": "<jerinj@marvell.com>", "To": "<dev@dpdk.org>, Jerin Jacob <jerinj@marvell.com>, Nithin Dabilpuram\n\t<ndabilpuram@marvell.com>, Kiran Kumar K <kirankumark@marvell.com>", "CC": "<ferruh.yigit@intel.com>, Krzysztof Kanas <kkanas@marvell.com>", "Date": "Sun, 2 Jun 2019 20:53:59 +0530", "Message-ID": "<20190602152434.23996-24-jerinj@marvell.com>", "X-Mailer": "git-send-email 2.21.0", "In-Reply-To": "<20190602152434.23996-1-jerinj@marvell.com>", "References": "<20190602152434.23996-1-jerinj@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:, ,\n\tdefinitions=2019-06-02_09:, , signatures=0", "Subject": "[dpdk-dev] [PATCH v1 23/58] net/octeontx2: configure TM HW resources", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Nithin Dabilpuram <ndabilpuram@marvell.com>\n\nThis patch sets up and configure hierarchy in hw\nnodes. Since all the registers are with RVU AF,\nregister configuration is also done using mbox\ncommunication.\n\nSigned-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>\nSigned-off-by: Krzysztof Kanas <kkanas@marvell.com>\n---\n drivers/net/octeontx2/otx2_tm.c | 504 ++++++++++++++++++++++++++++++++\n drivers/net/octeontx2/otx2_tm.h | 82 ++++++\n 2 files changed, 586 insertions(+)", "diff": "diff --git a/drivers/net/octeontx2/otx2_tm.c b/drivers/net/octeontx2/otx2_tm.c\nindex 91f31df05..463f90acd 100644\n--- a/drivers/net/octeontx2/otx2_tm.c\n+++ b/drivers/net/octeontx2/otx2_tm.c\n@@ -20,6 +20,41 @@ enum otx2_tm_node_level {\n \tOTX2_TM_LVL_MAX,\n };\n \n+static inline\n+uint64_t shaper2regval(struct shaper_params *shaper)\n+{\n+\treturn (shaper->burst_exponent << 37) | (shaper->burst_mantissa << 29) |\n+\t\t(shaper->div_exp << 13) | (shaper->exponent << 9) |\n+\t\t(shaper->mantissa << 1);\n+}\n+\n+static int\n+nix_get_link(struct otx2_eth_dev *dev)\n+{\n+\tint link = 13 /* SDP */;\n+\tuint16_t lmac_chan;\n+\tuint16_t map;\n+\n+\tlmac_chan = dev->tx_chan_base;\n+\n+\t/* CGX lmac link */\n+\tif (lmac_chan >= 0x800) {\n+\t\tmap = lmac_chan & 0x7FF;\n+\t\tlink = 4 * ((map >> 8) & 0xF) + ((map >> 4) & 0xF);\n+\t} else if (lmac_chan < 0x700) {\n+\t\t/* LBK channel */\n+\t\tlink = 12;\n+\t}\n+\n+\treturn link;\n+}\n+\n+static uint8_t\n+nix_get_relchan(struct otx2_eth_dev *dev)\n+{\n+\treturn dev->tx_chan_base & 0xff;\n+}\n+\n static bool\n nix_tm_have_tl1_access(struct otx2_eth_dev *dev)\n {\n@@ -28,6 +63,24 @@ nix_tm_have_tl1_access(struct otx2_eth_dev *dev)\n \t\t!is_lbk && !dev->maxvf;\n }\n \n+static int\n+find_prio_anchor(struct otx2_eth_dev *dev, uint32_t node_id)\n+{\n+\tstruct otx2_nix_tm_node *child_node;\n+\n+\tTAILQ_FOREACH(child_node, &dev->node_list, node) {\n+\t\tif (!child_node->parent)\n+\t\t\tcontinue;\n+\t\tif (!(child_node->parent->id == node_id))\n+\t\t\tcontinue;\n+\t\tif (child_node->priority == child_node->parent->rr_prio)\n+\t\t\tcontinue;\n+\t\treturn child_node->hw_id - child_node->priority;\n+\t}\n+\treturn 0;\n+}\n+\n+\n static struct otx2_nix_tm_shaper_profile *\n nix_tm_shaper_profile_search(struct otx2_eth_dev *dev, uint32_t shaper_id)\n {\n@@ -40,6 +93,451 @@ nix_tm_shaper_profile_search(struct otx2_eth_dev *dev, uint32_t shaper_id)\n \treturn NULL;\n }\n \n+static inline uint64_t\n+shaper_rate_to_nix(uint64_t cclk_hz, uint64_t cclk_ticks,\n+\t\t uint64_t value, uint64_t *exponent_p,\n+\t\t uint64_t *mantissa_p, uint64_t *div_exp_p)\n+{\n+\tuint64_t div_exp, exponent, mantissa;\n+\n+\t/* Boundary checks */\n+\tif (value < MIN_SHAPER_RATE(cclk_hz, cclk_ticks) ||\n+\t value > MAX_SHAPER_RATE(cclk_hz, cclk_ticks))\n+\t\treturn 0;\n+\n+\tif (value <= SHAPER_RATE(cclk_hz, cclk_ticks, 0, 0, 0)) {\n+\t\t/* Calculate rate div_exp and mantissa using\n+\t\t * the following formula:\n+\t\t *\n+\t\t * value = (cclk_hz * (256 + mantissa)\n+\t\t * / ((cclk_ticks << div_exp) * 256)\n+\t\t */\n+\t\tdiv_exp = 0;\n+\t\texponent = 0;\n+\t\tmantissa = MAX_RATE_MANTISSA;\n+\n+\t\twhile (value < (cclk_hz / (cclk_ticks << div_exp)))\n+\t\t\tdiv_exp += 1;\n+\n+\t\twhile (value <\n+\t\t ((cclk_hz * (256 + mantissa)) /\n+\t\t\t((cclk_ticks << div_exp) * 256)))\n+\t\t\tmantissa -= 1;\n+\t} else {\n+\t\t/* Calculate rate exponent and mantissa using\n+\t\t * the following formula:\n+\t\t *\n+\t\t * value = (cclk_hz * ((256 + mantissa) << exponent)\n+\t\t * / (cclk_ticks * 256)\n+\t\t *\n+\t\t */\n+\t\tdiv_exp = 0;\n+\t\texponent = MAX_RATE_EXPONENT;\n+\t\tmantissa = MAX_RATE_MANTISSA;\n+\n+\t\twhile (value < (cclk_hz * (1 << exponent)) / cclk_ticks)\n+\t\t\texponent -= 1;\n+\n+\t\twhile (value < (cclk_hz * ((256 + mantissa) << exponent)) /\n+\t\t (cclk_ticks * 256))\n+\t\t\tmantissa -= 1;\n+\t}\n+\n+\tif (div_exp > MAX_RATE_DIV_EXP ||\n+\t exponent > MAX_RATE_EXPONENT || mantissa > MAX_RATE_MANTISSA)\n+\t\treturn 0;\n+\n+\tif (div_exp_p)\n+\t\t*div_exp_p = div_exp;\n+\tif (exponent_p)\n+\t\t*exponent_p = exponent;\n+\tif (mantissa_p)\n+\t\t*mantissa_p = mantissa;\n+\n+\t/* Calculate real rate value */\n+\treturn SHAPER_RATE(cclk_hz, cclk_ticks, exponent, mantissa, div_exp);\n+}\n+\n+static inline uint64_t\n+lx_shaper_rate_to_nix(uint64_t cclk_hz, uint32_t hw_lvl,\n+\t\t uint64_t value, uint64_t *exponent,\n+\t\t uint64_t *mantissa, uint64_t *div_exp)\n+{\n+\tif (hw_lvl == NIX_TXSCH_LVL_TL1)\n+\t\treturn shaper_rate_to_nix(cclk_hz, L1_TIME_WHEEL_CCLK_TICKS,\n+\t\t\t\t\t value, exponent, mantissa, div_exp);\n+\telse\n+\t\treturn shaper_rate_to_nix(cclk_hz, LX_TIME_WHEEL_CCLK_TICKS,\n+\t\t\t\t\t value, exponent, mantissa, div_exp);\n+}\n+\n+static inline uint64_t\n+shaper_burst_to_nix(uint64_t value, uint64_t *exponent_p,\n+\t\t uint64_t *mantissa_p)\n+{\n+\tuint64_t exponent, mantissa;\n+\n+\tif (value < MIN_SHAPER_BURST || value > MAX_SHAPER_BURST)\n+\t\treturn 0;\n+\n+\t/* Calculate burst exponent and mantissa using\n+\t * the following formula:\n+\t *\n+\t * value = (((256 + mantissa) << (exponent + 1)\n+\t / 256)\n+\t *\n+\t */\n+\texponent = MAX_BURST_EXPONENT;\n+\tmantissa = MAX_BURST_MANTISSA;\n+\n+\twhile (value < (1ull << (exponent + 1)))\n+\t\texponent -= 1;\n+\n+\twhile (value < ((256 + mantissa) << (exponent + 1)) / 256)\n+\t\tmantissa -= 1;\n+\n+\tif (exponent > MAX_BURST_EXPONENT || mantissa > MAX_BURST_MANTISSA)\n+\t\treturn 0;\n+\n+\tif (exponent_p)\n+\t\t*exponent_p = exponent;\n+\tif (mantissa_p)\n+\t\t*mantissa_p = mantissa;\n+\n+\treturn SHAPER_BURST(exponent, mantissa);\n+}\n+\n+static int\n+configure_shaper_cir_pir_reg(struct otx2_eth_dev *dev,\n+\t\t\t struct otx2_nix_tm_node *tm_node,\n+\t\t\t struct shaper_params *cir,\n+\t\t\t struct shaper_params *pir)\n+{\n+\tuint32_t shaper_profile_id = RTE_TM_SHAPER_PROFILE_ID_NONE;\n+\tstruct otx2_nix_tm_shaper_profile *shaper_profile = NULL;\n+\tstruct rte_tm_shaper_params *param;\n+\n+\tshaper_profile_id = tm_node->params.shaper_profile_id;\n+\n+\tshaper_profile = nix_tm_shaper_profile_search(dev, shaper_profile_id);\n+\tif (shaper_profile) {\n+\t\tparam = &shaper_profile->profile;\n+\t\t/* Calculate CIR exponent and mantissa */\n+\t\tif (param->committed.rate)\n+\t\t\tcir->rate = lx_shaper_rate_to_nix(CCLK_HZ,\n+\t\t\t\t\t\t\t tm_node->hw_lvl_id,\n+\t\t\t\t\t\t\t param->committed.rate,\n+\t\t\t\t\t\t\t &cir->exponent,\n+\t\t\t\t\t\t\t &cir->mantissa,\n+\t\t\t\t\t\t\t &cir->div_exp);\n+\n+\t\t/* Calculate PIR exponent and mantissa */\n+\t\tif (param->peak.rate)\n+\t\t\tpir->rate = lx_shaper_rate_to_nix(CCLK_HZ,\n+\t\t\t\t\t\t\t tm_node->hw_lvl_id,\n+\t\t\t\t\t\t\t param->peak.rate,\n+\t\t\t\t\t\t\t &pir->exponent,\n+\t\t\t\t\t\t\t &pir->mantissa,\n+\t\t\t\t\t\t\t &pir->div_exp);\n+\n+\t\t/* Calculate CIR burst exponent and mantissa */\n+\t\tif (param->committed.size)\n+\t\t\tcir->burst = shaper_burst_to_nix(param->committed.size,\n+\t\t\t\t\t\t\t &cir->burst_exponent,\n+\t\t\t\t\t\t\t &cir->burst_mantissa);\n+\n+\t\t/* Calculate PIR burst exponent and mantissa */\n+\t\tif (param->peak.size)\n+\t\t\tpir->burst = shaper_burst_to_nix(param->peak.size,\n+\t\t\t\t\t\t\t &pir->burst_exponent,\n+\t\t\t\t\t\t\t &pir->burst_mantissa);\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int\n+send_tm_reqval(struct otx2_mbox *mbox, struct nix_txschq_config *req)\n+{\n+\tint rc;\n+\n+\tif (req->num_regs > MAX_REGS_PER_MBOX_MSG)\n+\t\treturn -ERANGE;\n+\n+\trc = otx2_mbox_process(mbox);\n+\tif (rc)\n+\t\treturn rc;\n+\n+\treq->num_regs = 0;\n+\treturn 0;\n+}\n+\n+static int\n+populate_tm_registers(struct otx2_eth_dev *dev,\n+\t\t struct otx2_nix_tm_node *tm_node)\n+{\n+\tuint64_t strict_schedul_prio, rr_prio;\n+\tstruct otx2_mbox *mbox = dev->mbox;\n+\tvolatile uint64_t *reg, *regval;\n+\tuint64_t parent = 0, child = 0;\n+\tstruct shaper_params cir, pir;\n+\tstruct nix_txschq_config *req;\n+\tuint64_t rr_quantum;\n+\tuint32_t hw_lvl;\n+\tuint32_t schq;\n+\tint rc;\n+\n+\tmemset(&cir, 0, sizeof(cir));\n+\tmemset(&pir, 0, sizeof(pir));\n+\n+\t/* Skip leaf nodes */\n+\tif (tm_node->hw_lvl_id == NIX_TXSCH_LVL_CNT)\n+\t\treturn 0;\n+\n+\t/* Root node will not have a parent node */\n+\tif (tm_node->hw_lvl_id == dev->otx2_tm_root_lvl)\n+\t\tparent = tm_node->parent_hw_id;\n+\telse\n+\t\tparent = tm_node->parent->hw_id;\n+\n+\t/* Do we need this trigger to configure TL1 */\n+\tif (dev->otx2_tm_root_lvl == NIX_TXSCH_LVL_TL2 &&\n+\t tm_node->hw_lvl_id == dev->otx2_tm_root_lvl) {\n+\t\tschq = parent;\n+\t\t/*\n+\t\t * Default config for TL1.\n+\t\t * For VF this is always ignored.\n+\t\t */\n+\n+\t\treq = otx2_mbox_alloc_msg_nix_txschq_cfg(mbox);\n+\t\treq->lvl = NIX_TXSCH_LVL_TL1;\n+\n+\t\t/* Set DWRR quantum */\n+\t\treq->reg[0] = NIX_AF_TL1X_SCHEDULE(schq);\n+\t\treq->regval[0] = TXSCH_TL1_DFLT_RR_QTM;\n+\t\treq->num_regs++;\n+\n+\t\treq->reg[1] = NIX_AF_TL1X_TOPOLOGY(schq);\n+\t\treq->regval[1] = (TXSCH_TL1_DFLT_RR_PRIO << 1);\n+\t\treq->num_regs++;\n+\n+\t\treq->reg[2] = NIX_AF_TL1X_CIR(schq);\n+\t\treq->regval[2] = 0;\n+\t\treq->num_regs++;\n+\n+\t\trc = send_tm_reqval(mbox, req);\n+\t\tif (rc)\n+\t\t\tgoto error;\n+\t}\n+\n+\tif (tm_node->hw_lvl_id != NIX_TXSCH_LVL_SMQ)\n+\t\tchild = find_prio_anchor(dev, tm_node->id);\n+\n+\trr_prio = tm_node->rr_prio;\n+\thw_lvl = tm_node->hw_lvl_id;\n+\tstrict_schedul_prio = tm_node->priority;\n+\tschq = tm_node->hw_id;\n+\trr_quantum = (tm_node->weight * NIX_TM_RR_QUANTUM_MAX) /\n+\t\tMAX_SCHED_WEIGHT;\n+\n+\tconfigure_shaper_cir_pir_reg(dev, tm_node, &cir, &pir);\n+\n+\totx2_tm_dbg(\"Configure node %p, lvl %u hw_lvl %u, id %u, hw_id %u,\"\n+\t\t \"parent_hw_id %\" PRIx64 \", pir %\" PRIx64 \", cir %\" PRIx64,\n+\t\t tm_node, tm_node->level_id, hw_lvl,\n+\t\t tm_node->id, schq, parent, pir.rate, cir.rate);\n+\n+\trc = -EFAULT;\n+\n+\tswitch (hw_lvl) {\n+\tcase NIX_TXSCH_LVL_SMQ:\n+\t\treq = otx2_mbox_alloc_msg_nix_txschq_cfg(mbox);\n+\t\treq->lvl = hw_lvl;\n+\t\treg = req->reg;\n+\t\tregval = req->regval;\n+\t\treq->num_regs = 0;\n+\n+\t\t/* Set xoff which will be cleared later */\n+\t\t*reg++ = NIX_AF_SMQX_CFG(schq);\n+\t\t*regval++ = BIT_ULL(50) |\n+\t\t\t\t(NIX_MAX_HW_FRS << 8) | NIX_MIN_HW_FRS;\n+\t\treq->num_regs++;\n+\t\t*reg++ = NIX_AF_MDQX_PARENT(schq);\n+\t\t*regval++ = parent << 16;\n+\t\treq->num_regs++;\n+\t\t*reg++ = NIX_AF_MDQX_SCHEDULE(schq);\n+\t\t*regval++ = (strict_schedul_prio << 24) | rr_quantum;\n+\t\treq->num_regs++;\n+\t\tif (pir.rate && pir.burst) {\n+\t\t\t*reg++ = NIX_AF_MDQX_PIR(schq);\n+\t\t\t*regval++ = shaper2regval(&pir) | 1;\n+\t\t\treq->num_regs++;\n+\t\t}\n+\n+\t\tif (cir.rate && cir.burst) {\n+\t\t\t*reg++ = NIX_AF_MDQX_CIR(schq);\n+\t\t\t*regval++ = shaper2regval(&cir) | 1;\n+\t\t\treq->num_regs++;\n+\t\t}\n+\n+\t\trc = send_tm_reqval(mbox, req);\n+\t\tif (rc)\n+\t\t\tgoto error;\n+\t\tbreak;\n+\tcase NIX_TXSCH_LVL_TL4:\n+\t\treq = otx2_mbox_alloc_msg_nix_txschq_cfg(mbox);\n+\t\treq->lvl = hw_lvl;\n+\t\treq->num_regs = 0;\n+\t\treg = req->reg;\n+\t\tregval = req->regval;\n+\n+\t\t*reg++ = NIX_AF_TL4X_PARENT(schq);\n+\t\t*regval++ = parent << 16;\n+\t\treq->num_regs++;\n+\t\t*reg++ = NIX_AF_TL4X_TOPOLOGY(schq);\n+\t\t*regval++ = (child << 32) | (rr_prio << 1);\n+\t\treq->num_regs++;\n+\t\t*reg++ = NIX_AF_TL4X_SCHEDULE(schq);\n+\t\t*regval++ = (strict_schedul_prio << 24) | rr_quantum;\n+\t\treq->num_regs++;\n+\t\tif (pir.rate && pir.burst) {\n+\t\t\t*reg++ = NIX_AF_TL4X_PIR(schq);\n+\t\t\t*regval++ = shaper2regval(&pir) | 1;\n+\t\t\treq->num_regs++;\n+\t\t}\n+\t\tif (cir.rate && cir.burst) {\n+\t\t\t*reg++ = NIX_AF_TL4X_CIR(schq);\n+\t\t\t*regval++ = shaper2regval(&cir) | 1;\n+\t\t\treq->num_regs++;\n+\t\t}\n+\n+\t\trc = send_tm_reqval(mbox, req);\n+\t\tif (rc)\n+\t\t\tgoto error;\n+\t\tbreak;\n+\tcase NIX_TXSCH_LVL_TL3:\n+\t\treq = otx2_mbox_alloc_msg_nix_txschq_cfg(mbox);\n+\t\treq->lvl = hw_lvl;\n+\t\treq->num_regs = 0;\n+\t\treg = req->reg;\n+\t\tregval = req->regval;\n+\n+\t\t*reg++ = NIX_AF_TL3X_PARENT(schq);\n+\t\t*regval++ = parent << 16;\n+\t\treq->num_regs++;\n+\t\t*reg++ = NIX_AF_TL3X_TOPOLOGY(schq);\n+\t\t*regval++ = (child << 32) | (rr_prio << 1);\n+\t\treq->num_regs++;\n+\t\t*reg++ = NIX_AF_TL3X_SCHEDULE(schq);\n+\t\t*regval++ = (strict_schedul_prio << 24) | rr_quantum;\n+\t\treq->num_regs++;\n+\t\tif (pir.rate && pir.burst) {\n+\t\t\t*reg++ = NIX_AF_TL3X_PIR(schq);\n+\t\t\t*regval++ = shaper2regval(&pir) | 1;\n+\t\t\treq->num_regs++;\n+\t\t}\n+\t\tif (cir.rate && cir.burst) {\n+\t\t\t*reg++ = NIX_AF_TL3X_CIR(schq);\n+\t\t\t*regval++ = shaper2regval(&cir) | 1;\n+\t\t\treq->num_regs++;\n+\t\t}\n+\n+\t\trc = send_tm_reqval(mbox, req);\n+\t\tif (rc)\n+\t\t\tgoto error;\n+\t\tbreak;\n+\tcase NIX_TXSCH_LVL_TL2:\n+\t\treq = otx2_mbox_alloc_msg_nix_txschq_cfg(mbox);\n+\t\treq->lvl = hw_lvl;\n+\t\treq->num_regs = 0;\n+\t\treg = req->reg;\n+\t\tregval = req->regval;\n+\n+\t\t*reg++ = NIX_AF_TL2X_PARENT(schq);\n+\t\t*regval++ = parent << 16;\n+\t\treq->num_regs++;\n+\t\t*reg++ = NIX_AF_TL2X_TOPOLOGY(schq);\n+\t\t*regval++ = (child << 32) | (rr_prio << 1);\n+\t\treq->num_regs++;\n+\t\t*reg++ = NIX_AF_TL2X_SCHEDULE(schq);\n+\t\tif (dev->otx2_tm_root_lvl == NIX_TXSCH_LVL_TL2)\n+\t\t\t*regval++ = (1 << 24) | rr_quantum;\n+\t\telse\n+\t\t\t*regval++ = (strict_schedul_prio << 24) | rr_quantum;\n+\t\treq->num_regs++;\n+\t\t*reg++ = NIX_AF_TL3_TL2X_LINKX_CFG(schq, nix_get_link(dev));\n+\t\t*regval++ = BIT_ULL(12) | nix_get_relchan(dev);\n+\t\treq->num_regs++;\n+\t\tif (pir.rate && pir.burst) {\n+\t\t\t*reg++ = NIX_AF_TL2X_PIR(schq);\n+\t\t\t*regval++ = shaper2regval(&pir) | 1;\n+\t\t\treq->num_regs++;\n+\t\t}\n+\t\tif (cir.rate && cir.burst) {\n+\t\t\t*reg++ = NIX_AF_TL2X_CIR(schq);\n+\t\t\t*regval++ = shaper2regval(&cir) | 1;\n+\t\t\treq->num_regs++;\n+\t\t}\n+\n+\t\trc = send_tm_reqval(mbox, req);\n+\t\tif (rc)\n+\t\t\tgoto error;\n+\t\tbreak;\n+\tcase NIX_TXSCH_LVL_TL1:\n+\t\treq = otx2_mbox_alloc_msg_nix_txschq_cfg(mbox);\n+\t\treq->lvl = hw_lvl;\n+\t\treq->num_regs = 0;\n+\t\treg = req->reg;\n+\t\tregval = req->regval;\n+\n+\t\t*reg++ = NIX_AF_TL1X_SCHEDULE(schq);\n+\t\t*regval++ = rr_quantum;\n+\t\treq->num_regs++;\n+\t\t*reg++ = NIX_AF_TL1X_TOPOLOGY(schq);\n+\t\t*regval++ = (child << 32) | (rr_prio << 1 /*RR_PRIO*/);\n+\t\treq->num_regs++;\n+\t\tif (cir.rate && cir.burst) {\n+\t\t\t*reg++ = NIX_AF_TL1X_CIR(schq);\n+\t\t\t*regval++ = shaper2regval(&cir) | 1;\n+\t\t\treq->num_regs++;\n+\t\t}\n+\n+\t\trc = send_tm_reqval(mbox, req);\n+\t\tif (rc)\n+\t\t\tgoto error;\n+\t\tbreak;\n+\t}\n+\n+\treturn 0;\n+error:\n+\totx2_err(\"Txschq cfg request failed for node %p, rc=%d\", tm_node, rc);\n+\treturn rc;\n+}\n+\n+\n+static int\n+nix_tm_txsch_reg_config(struct otx2_eth_dev *dev)\n+{\n+\tstruct otx2_nix_tm_node *tm_node;\n+\tuint32_t lvl;\n+\tint rc = 0;\n+\n+\tif (nix_get_link(dev) == 13)\n+\t\treturn -EPERM;\n+\n+\tfor (lvl = 0; lvl < (uint32_t)dev->otx2_tm_root_lvl + 1; lvl++) {\n+\t\tTAILQ_FOREACH(tm_node, &dev->node_list, node) {\n+\t\t\tif (tm_node->hw_lvl_id == lvl) {\n+\t\t\t\trc = populate_tm_registers(dev, tm_node);\n+\t\t\t\tif (rc)\n+\t\t\t\t\tgoto exit;\n+\t\t\t}\n+\t\t}\n+\t}\n+exit:\n+\treturn rc;\n+}\n+\n static struct otx2_nix_tm_node *\n nix_tm_node_search(struct otx2_eth_dev *dev,\n \t\t uint32_t node_id, bool user)\n@@ -443,6 +941,12 @@ nix_tm_alloc_resources(struct rte_eth_dev *eth_dev, bool xmit_enable)\n \t\treturn rc;\n \t}\n \n+\trc = nix_tm_txsch_reg_config(dev);\n+\tif (rc) {\n+\t\totx2_err(\"TM failed to configure sched registers=%d\", rc);\n+\t\treturn rc;\n+\t}\n+\n \treturn 0;\n }\n \ndiff --git a/drivers/net/octeontx2/otx2_tm.h b/drivers/net/octeontx2/otx2_tm.h\nindex 94023fa99..af1bb1862 100644\n--- a/drivers/net/octeontx2/otx2_tm.h\n+++ b/drivers/net/octeontx2/otx2_tm.h\n@@ -64,4 +64,86 @@ TAILQ_HEAD(otx2_nix_tm_shaper_profile_list, otx2_nix_tm_shaper_profile);\n /* = NIX_MAX_HW_MTU */\n #define DEFAULT_RR_WEIGHT 71\n \n+/** NIX rate limits */\n+#define MAX_RATE_DIV_EXP 12\n+#define MAX_RATE_EXPONENT 0xf\n+#define MAX_RATE_MANTISSA 0xff\n+\n+/** NIX rate limiter time-wheel resolution */\n+#define L1_TIME_WHEEL_CCLK_TICKS 240\n+#define LX_TIME_WHEEL_CCLK_TICKS 860\n+\n+#define CCLK_HZ 1000000000\n+\n+/* NIX rate calculation\n+ *\tCCLK = coprocessor-clock frequency in MHz\n+ *\tCCLK_TICKS = rate limiter time-wheel resolution\n+ *\n+ *\tPIR_ADD = ((256 + NIX_*_PIR[RATE_MANTISSA])\n+ *\t\t<< NIX_*_PIR[RATE_EXPONENT]) / 256\n+ *\tPIR = (CCLK / (CCLK_TICKS << NIX_*_PIR[RATE_DIVIDER_EXPONENT]))\n+ *\t\t* PIR_ADD\n+ *\n+ *\tCIR_ADD = ((256 + NIX_*_CIR[RATE_MANTISSA])\n+ *\t\t<< NIX_*_CIR[RATE_EXPONENT]) / 256\n+ *\tCIR = (CCLK / (CCLK_TICKS << NIX_*_CIR[RATE_DIVIDER_EXPONENT]))\n+ *\t\t* CIR_ADD\n+ */\n+#define SHAPER_RATE(cclk_hz, cclk_ticks, \\\n+\t\t\texponent, mantissa, div_exp) \\\n+\t(((uint64_t)(cclk_hz) * ((256 + (mantissa)) << (exponent))) \\\n+\t\t/ (((cclk_ticks) << (div_exp)) * 256))\n+\n+#define L1_SHAPER_RATE(cclk_hz, exponent, mantissa, div_exp) \\\n+\tSHAPER_RATE(cclk_hz, L1_TIME_WHEEL_CCLK_TICKS, \\\n+\t\t\texponent, mantissa, div_exp)\n+\n+#define LX_SHAPER_RATE(cclk_hz, exponent, mantissa, div_exp) \\\n+\tSHAPER_RATE(cclk_hz, LX_TIME_WHEEL_CCLK_TICKS, \\\n+\t\t\texponent, mantissa, div_exp)\n+\n+/* Shaper rate limits */\n+#define MIN_SHAPER_RATE(cclk_hz, cclk_ticks) \\\n+\tSHAPER_RATE(cclk_hz, cclk_ticks, 0, 0, MAX_RATE_DIV_EXP)\n+\n+#define MAX_SHAPER_RATE(cclk_hz, cclk_ticks) \\\n+\tSHAPER_RATE(cclk_hz, cclk_ticks, MAX_RATE_EXPONENT, \\\n+\t\t\tMAX_RATE_MANTISSA, 0)\n+\n+#define MIN_L1_SHAPER_RATE(cclk_hz) \\\n+\tMIN_SHAPER_RATE(cclk_hz, L1_TIME_WHEEL_CCLK_TICKS)\n+\n+#define MAX_L1_SHAPER_RATE(cclk_hz) \\\n+\tMAX_SHAPER_RATE(cclk_hz, L1_TIME_WHEEL_CCLK_TICKS)\n+\n+/** TM Shaper - low level operations */\n+\n+/** NIX burst limits */\n+#define MAX_BURST_EXPONENT 0xf\n+#define MAX_BURST_MANTISSA 0xff\n+\n+/* NIX burst calculation\n+ *\tPIR_BURST = ((256 + NIX_*_PIR[BURST_MANTISSA])\n+ *\t\t<< (NIX_*_PIR[BURST_EXPONENT] + 1))\n+ *\t\t\t/ 256\n+ *\n+ *\tCIR_BURST = ((256 + NIX_*_CIR[BURST_MANTISSA])\n+ *\t\t<< (NIX_*_CIR[BURST_EXPONENT] + 1))\n+ *\t\t\t/ 256\n+ */\n+#define SHAPER_BURST(exponent, mantissa) \\\n+\t(((256 + (mantissa)) << ((exponent) + 1)) / 256)\n+\n+/** Shaper burst limits */\n+#define MIN_SHAPER_BURST \\\n+\tSHAPER_BURST(0, 0)\n+\n+#define MAX_SHAPER_BURST \\\n+\tSHAPER_BURST(MAX_BURST_EXPONENT,\\\n+\t\tMAX_BURST_MANTISSA)\n+\n+/* Default TL1 priority and Quantum from AF */\n+#define TXSCH_TL1_DFLT_RR_QTM ((1 << 24) - 1)\n+#define TXSCH_TL1_DFLT_RR_PRIO 1\n+\n #endif /* __OTX2_TM_H__ */\n", "prefixes": [ "v1", "23/58" ] }