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GET /api/patches/54077/?format=api
{ "id": 54077, "url": "http://patches.dpdk.org/api/patches/54077/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20190602152434.23996-22-jerinj@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20190602152434.23996-22-jerinj@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20190602152434.23996-22-jerinj@marvell.com", "date": "2019-06-02T15:23:57", "name": "[v1,21/58] net/octeontx2: introduce traffic manager", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "0270f25bf5b5980e49210fe78cde376b7b48a2cd", "submitter": { "id": 1188, "url": "http://patches.dpdk.org/api/people/1188/?format=api", "name": "Jerin Jacob Kollanukkaran", "email": "jerinj@marvell.com" }, "delegate": { "id": 319, "url": "http://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20190602152434.23996-22-jerinj@marvell.com/mbox/", "series": [ { "id": 4848, "url": "http://patches.dpdk.org/api/series/4848/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=4848", "date": "2019-06-02T15:23:36", "name": "OCTEON TX2 Ethdev driver", "version": 1, "mbox": "http://patches.dpdk.org/series/4848/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/54077/comments/", "check": "fail", "checks": "http://patches.dpdk.org/api/patches/54077/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id A02331B970;\n\tSun, 2 Jun 2019 17:25:43 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n\t[67.231.148.174]) by dpdk.org (Postfix) with ESMTP id 0FF531B945\n\tfor <dev@dpdk.org>; Sun, 2 Jun 2019 17:25:41 +0200 (CEST)", "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n\tby mx0a-0016f401.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id\n\tx52FJtoJ021289; Sun, 2 Jun 2019 08:25:41 -0700", "from sc-exch03.marvell.com ([199.233.58.183])\n\tby mx0a-0016f401.pphosted.com with ESMTP id 2supqkvqg5-1\n\t(version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); \n\tSun, 02 Jun 2019 08:25:41 -0700", "from SC-EXCH03.marvell.com (10.93.176.83) by SC-EXCH03.marvell.com\n\t(10.93.176.83) with Microsoft SMTP Server (TLS) id 15.0.1367.3;\n\tSun, 2 Jun 2019 08:25:40 -0700", "from maili.marvell.com (10.93.176.43) by SC-EXCH03.marvell.com\n\t(10.93.176.83) with Microsoft SMTP Server id 15.0.1367.3 via Frontend\n\tTransport; Sun, 2 Jun 2019 08:25:40 -0700", "from jerin-lab.marvell.com (jerin-lab.marvell.com [10.28.34.14])\n\tby maili.marvell.com (Postfix) with ESMTP id CA7CA3F703F;\n\tSun, 2 Jun 2019 08:25:38 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n\th=from : to : cc :\n\tsubject : date : message-id : in-reply-to : references : mime-version\n\t: content-transfer-encoding : content-type; s=pfpt0818;\n\tbh=U23Ew+HiV3Hdkb+3wPeEsfC1ErY0GFP8NQWJ0T/YcEY=;\n\tb=yZzIvbZemveyU3c00P46alHCkQ/AOxvdnIKnl4jRMuYdMmsK8e41FqK+1GarrLFVXqYB\n\tF8SvsVPl+h0OKNU7RHLuvH8Pwoekz0WvjJCX2l6DGJWiLEO93/mtoyxXgZZYZAPvDpLL\n\tr0oLjXFXHcOBPvQIqeuOAfUv6nGfpHA4yRu5VmnyOUaWfTbQfQ+L9BqMV98jL+d1s/mW\n\ttIbgl8xK+Hor5Mly0df84yVhOucvy61UsadTU6m/z4oR++4onAA/FHScgzpoTztms5e4\n\tbhYJz6xI0MY9I7aQrxQzQVoMpBc3pLk2J82nWBXOXCZYFgkRMC9rdJRzQIFuyCz+QSqN\n\tcA== ", "From": "<jerinj@marvell.com>", "To": "<dev@dpdk.org>, Jerin Jacob <jerinj@marvell.com>, Nithin Dabilpuram\n\t<ndabilpuram@marvell.com>, Kiran Kumar K <kirankumark@marvell.com>", "CC": "<ferruh.yigit@intel.com>, Krzysztof Kanas <kkanas@marvell.com>", "Date": "Sun, 2 Jun 2019 20:53:57 +0530", "Message-ID": "<20190602152434.23996-22-jerinj@marvell.com>", "X-Mailer": "git-send-email 2.21.0", "In-Reply-To": "<20190602152434.23996-1-jerinj@marvell.com>", "References": "<20190602152434.23996-1-jerinj@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:, ,\n\tdefinitions=2019-06-02_09:, , signatures=0", "Subject": "[dpdk-dev] [PATCH v1 21/58] net/octeontx2: introduce traffic manager", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Nithin Dabilpuram <ndabilpuram@marvell.com>\n\nIntroduce traffic manager infra and default hierarchy\ncreation.\n\nUpon ethdev configure, a default hierarchy is\ncreated with one-to-one mapped tm nodes. This topology\nwill be overridden when user explicitly creates and commits\na new hierarchy using rte_tm interface.\n\nSigned-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>\nSigned-off-by: Krzysztof Kanas <kkanas@marvell.com>\n---\n drivers/net/octeontx2/Makefile | 1 +\n drivers/net/octeontx2/meson.build | 1 +\n drivers/net/octeontx2/otx2_ethdev.c | 16 ++\n drivers/net/octeontx2/otx2_ethdev.h | 14 ++\n drivers/net/octeontx2/otx2_tm.c | 252 ++++++++++++++++++++++++++++\n drivers/net/octeontx2/otx2_tm.h | 67 ++++++++\n 6 files changed, 351 insertions(+)\n create mode 100644 drivers/net/octeontx2/otx2_tm.c\n create mode 100644 drivers/net/octeontx2/otx2_tm.h", "diff": "diff --git a/drivers/net/octeontx2/Makefile b/drivers/net/octeontx2/Makefile\nindex 67352ec81..cf2ba0e0e 100644\n--- a/drivers/net/octeontx2/Makefile\n+++ b/drivers/net/octeontx2/Makefile\n@@ -30,6 +30,7 @@ LIBABIVER := 1\n # all source are stored in SRCS-y\n #\n SRCS-$(CONFIG_RTE_LIBRTE_OCTEONTX2_PMD) += \\\n+\totx2_tm.c\t\\\n \totx2_rss.c\t\\\n \totx2_mac.c\t\\\n \totx2_link.c\t\\\ndiff --git a/drivers/net/octeontx2/meson.build b/drivers/net/octeontx2/meson.build\nindex b7e56e2ca..14e8e78f8 100644\n--- a/drivers/net/octeontx2/meson.build\n+++ b/drivers/net/octeontx2/meson.build\n@@ -3,6 +3,7 @@\n #\n \n sources = files(\n+\t\t'otx2_tm.c',\n \t\t'otx2_rss.c',\n \t\t'otx2_mac.c',\n \t\t'otx2_link.c',\ndiff --git a/drivers/net/octeontx2/otx2_ethdev.c b/drivers/net/octeontx2/otx2_ethdev.c\nindex 04a953441..2808058a8 100644\n--- a/drivers/net/octeontx2/otx2_ethdev.c\n+++ b/drivers/net/octeontx2/otx2_ethdev.c\n@@ -1033,6 +1033,7 @@ otx2_nix_configure(struct rte_eth_dev *eth_dev)\n \t\trc = nix_store_queue_cfg_and_then_release(eth_dev);\n \t\tif (rc)\n \t\t\tgoto fail;\n+\t\totx2_nix_tm_fini(eth_dev);\n \t\tnix_lf_free(dev);\n \t}\n \n@@ -1066,6 +1067,13 @@ otx2_nix_configure(struct rte_eth_dev *eth_dev)\n \t\tgoto free_nix_lf;\n \t}\n \n+\t/* Init the default TM scheduler hierarchy */\n+\trc = otx2_nix_tm_init_default(eth_dev);\n+\tif (rc) {\n+\t\totx2_err(\"Failed to init traffic manager rc=%d\", rc);\n+\t\tgoto free_nix_lf;\n+\t}\n+\n \t/* Register queue IRQs */\n \trc = oxt2_nix_register_queue_irqs(eth_dev);\n \tif (rc) {\n@@ -1368,6 +1376,9 @@ otx2_eth_dev_init(struct rte_eth_dev *eth_dev)\n \t/* Also sync same MAC address to CGX table */\n \totx2_cgx_mac_addr_set(eth_dev, ð_dev->data->mac_addrs[0]);\n \n+\t/* Initialize the tm data structures */\n+\totx2_nix_tm_conf_init(eth_dev);\n+\n \tdev->tx_offload_capa = nix_get_tx_offload_capa(dev);\n \tdev->rx_offload_capa = nix_get_rx_offload_capa(dev);\n \n@@ -1423,6 +1434,11 @@ otx2_eth_dev_uninit(struct rte_eth_dev *eth_dev, bool mbox_close)\n \t}\n \teth_dev->data->nb_rx_queues = 0;\n \n+\t/* Free tm resources */\n+\trc = otx2_nix_tm_fini(eth_dev);\n+\tif (rc)\n+\t\totx2_err(\"Failed to cleanup tm, rc=%d\", rc);\n+\n \t/* Unregister queue irqs */\n \toxt2_nix_unregister_queue_irqs(eth_dev);\n \ndiff --git a/drivers/net/octeontx2/otx2_ethdev.h b/drivers/net/octeontx2/otx2_ethdev.h\nindex 7b8c7e1e5..b2b7d4186 100644\n--- a/drivers/net/octeontx2/otx2_ethdev.h\n+++ b/drivers/net/octeontx2/otx2_ethdev.h\n@@ -19,6 +19,7 @@\n #include \"otx2_irq.h\"\n #include \"otx2_mempool.h\"\n #include \"otx2_rx.h\"\n+#include \"otx2_tm.h\"\n #include \"otx2_tx.h\"\n \n #define OTX2_ETH_DEV_PMD_VERSION\t\"1.0\"\n@@ -181,6 +182,19 @@ struct otx2_eth_dev {\n \tuint64_t rx_offload_capa;\n \tuint64_t tx_offload_capa;\n \tstruct otx2_qint qints_mem[RTE_MAX_QUEUES_PER_PORT];\n+\tuint16_t txschq[NIX_TXSCH_LVL_CNT];\n+\tuint16_t txschq_contig[NIX_TXSCH_LVL_CNT];\n+\tuint16_t txschq_index[NIX_TXSCH_LVL_CNT];\n+\tuint16_t txschq_contig_index[NIX_TXSCH_LVL_CNT];\n+\t/* Dis-contiguous queues */\n+\tuint16_t txschq_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC];\n+\t/* Contiguous queues */\n+\tuint16_t txschq_contig_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC];\n+\tuint16_t otx2_tm_root_lvl;\n+\tuint16_t tm_flags;\n+\tuint16_t tm_leaf_cnt;\n+\tstruct otx2_nix_tm_node_list node_list;\n+\tstruct otx2_nix_tm_shaper_profile_list shaper_profile_list;\n \tstruct otx2_rss_info rss_info;\n \tuint32_t txmap[RTE_ETHDEV_QUEUE_STAT_CNTRS];\n \tuint32_t rxmap[RTE_ETHDEV_QUEUE_STAT_CNTRS];\ndiff --git a/drivers/net/octeontx2/otx2_tm.c b/drivers/net/octeontx2/otx2_tm.c\nnew file mode 100644\nindex 000000000..bc0474242\n--- /dev/null\n+++ b/drivers/net/octeontx2/otx2_tm.c\n@@ -0,0 +1,252 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2019 Marvell International Ltd.\n+ */\n+\n+#include <rte_malloc.h>\n+\n+#include \"otx2_ethdev.h\"\n+#include \"otx2_tm.h\"\n+\n+/* Use last LVL_CNT nodes as default nodes */\n+#define NIX_DEFAULT_NODE_ID_START (RTE_TM_NODE_ID_NULL - NIX_TXSCH_LVL_CNT)\n+\n+enum otx2_tm_node_level {\n+\tOTX2_TM_LVL_ROOT = 0,\n+\tOTX2_TM_LVL_SCH1,\n+\tOTX2_TM_LVL_SCH2,\n+\tOTX2_TM_LVL_SCH3,\n+\tOTX2_TM_LVL_SCH4,\n+\tOTX2_TM_LVL_QUEUE,\n+\tOTX2_TM_LVL_MAX,\n+};\n+\n+static bool\n+nix_tm_have_tl1_access(struct otx2_eth_dev *dev)\n+{\n+\tbool is_lbk = otx2_dev_is_lbk(dev);\n+\treturn otx2_dev_is_pf(dev) && !otx2_dev_is_A0(dev) &&\n+\t\t!is_lbk && !dev->maxvf;\n+}\n+\n+static struct otx2_nix_tm_shaper_profile *\n+nix_tm_shaper_profile_search(struct otx2_eth_dev *dev, uint32_t shaper_id)\n+{\n+\tstruct otx2_nix_tm_shaper_profile *tm_shaper_profile;\n+\n+\tTAILQ_FOREACH(tm_shaper_profile, &dev->shaper_profile_list, shaper) {\n+\t\tif (tm_shaper_profile->shaper_profile_id == shaper_id)\n+\t\t\treturn tm_shaper_profile;\n+\t}\n+\treturn NULL;\n+}\n+\n+static struct otx2_nix_tm_node *\n+nix_tm_node_search(struct otx2_eth_dev *dev,\n+\t\t uint32_t node_id, bool user)\n+{\n+\tstruct otx2_nix_tm_node *tm_node;\n+\n+\tTAILQ_FOREACH(tm_node, &dev->node_list, node) {\n+\t\tif (tm_node->id == node_id &&\n+\t\t (user == !!(tm_node->flags & NIX_TM_NODE_USER)))\n+\t\t\treturn tm_node;\n+\t}\n+\treturn NULL;\n+}\n+\n+static int\n+nix_tm_node_add_to_list(struct otx2_eth_dev *dev, uint32_t node_id,\n+\t\t\tuint32_t parent_node_id, uint32_t priority,\n+\t\t\tuint32_t weight, uint16_t hw_lvl_id,\n+\t\t\tuint16_t level_id, bool user,\n+\t\t\tstruct rte_tm_node_params *params)\n+{\n+\tstruct otx2_nix_tm_shaper_profile *shaper_profile;\n+\tstruct otx2_nix_tm_node *tm_node, *parent_node;\n+\tuint32_t shaper_profile_id;\n+\n+\tshaper_profile_id = params->shaper_profile_id;\n+\tshaper_profile = nix_tm_shaper_profile_search(dev, shaper_profile_id);\n+\n+\tparent_node = nix_tm_node_search(dev, parent_node_id, user);\n+\n+\ttm_node = rte_zmalloc(\"otx2_nix_tm_node\",\n+\t\t\t sizeof(struct otx2_nix_tm_node), 0);\n+\tif (!tm_node)\n+\t\treturn -ENOMEM;\n+\n+\ttm_node->level_id = level_id;\n+\ttm_node->hw_lvl_id = hw_lvl_id;\n+\n+\ttm_node->id = node_id;\n+\ttm_node->priority = priority;\n+\ttm_node->weight = weight;\n+\ttm_node->rr_prio = 0xf;\n+\ttm_node->max_prio = UINT32_MAX;\n+\ttm_node->hw_id = UINT32_MAX;\n+\ttm_node->flags = 0;\n+\tif (user)\n+\t\ttm_node->flags = NIX_TM_NODE_USER;\n+\trte_memcpy(&tm_node->params, params, sizeof(struct rte_tm_node_params));\n+\n+\tif (shaper_profile)\n+\t\tshaper_profile->reference_count++;\n+\ttm_node->parent = parent_node;\n+\ttm_node->parent_hw_id = UINT32_MAX;\n+\n+\tTAILQ_INSERT_TAIL(&dev->node_list, tm_node, node);\n+\n+\treturn 0;\n+}\n+\n+static int\n+nix_tm_clear_shaper_profiles(struct otx2_eth_dev *dev)\n+{\n+\tstruct otx2_nix_tm_shaper_profile *shaper_profile;\n+\n+\twhile ((shaper_profile = TAILQ_FIRST(&dev->shaper_profile_list))) {\n+\t\tif (shaper_profile->reference_count)\n+\t\t\totx2_tm_dbg(\"Shaper profile %u has non zero references\",\n+\t\t\t\t shaper_profile->shaper_profile_id);\n+\t\tTAILQ_REMOVE(&dev->shaper_profile_list, shaper_profile, shaper);\n+\t\trte_free(shaper_profile);\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int\n+nix_tm_prepare_default_tree(struct rte_eth_dev *eth_dev)\n+{\n+\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n+\tuint32_t def = eth_dev->data->nb_tx_queues;\n+\tstruct rte_tm_node_params params;\n+\tuint32_t leaf_parent, i;\n+\tint rc = 0;\n+\n+\t/* Default params */\n+\tmemset(¶ms, 0, sizeof(params));\n+\tparams.shaper_profile_id = RTE_TM_SHAPER_PROFILE_ID_NONE;\n+\n+\tif (nix_tm_have_tl1_access(dev)) {\n+\t\tdev->otx2_tm_root_lvl = NIX_TXSCH_LVL_TL1;\n+\t\trc = nix_tm_node_add_to_list(dev, def, RTE_TM_NODE_ID_NULL, 0,\n+\t\t\t\t\t DEFAULT_RR_WEIGHT,\n+\t\t\t\t\t NIX_TXSCH_LVL_TL1,\n+\t\t\t\t\t OTX2_TM_LVL_ROOT, false, ¶ms);\n+\t\tif (rc)\n+\t\t\tgoto exit;\n+\t\trc = nix_tm_node_add_to_list(dev, def + 1, def, 0,\n+\t\t\t\t\t DEFAULT_RR_WEIGHT,\n+\t\t\t\t\t NIX_TXSCH_LVL_TL2,\n+\t\t\t\t\t OTX2_TM_LVL_SCH1, false, ¶ms);\n+\t\tif (rc)\n+\t\t\tgoto exit;\n+\n+\t\trc = nix_tm_node_add_to_list(dev, def + 2, def + 1, 0,\n+\t\t\t\t\t DEFAULT_RR_WEIGHT,\n+\t\t\t\t\t NIX_TXSCH_LVL_TL3,\n+\t\t\t\t\t OTX2_TM_LVL_SCH2, false, ¶ms);\n+\t\tif (rc)\n+\t\t\tgoto exit;\n+\n+\t\trc = nix_tm_node_add_to_list(dev, def + 3, def + 2, 0,\n+\t\t\t\t\t DEFAULT_RR_WEIGHT,\n+\t\t\t\t\t NIX_TXSCH_LVL_TL4,\n+\t\t\t\t\t OTX2_TM_LVL_SCH3, false, ¶ms);\n+\t\tif (rc)\n+\t\t\tgoto exit;\n+\n+\t\trc = nix_tm_node_add_to_list(dev, def + 4, def + 3, 0,\n+\t\t\t\t\t DEFAULT_RR_WEIGHT,\n+\t\t\t\t\t NIX_TXSCH_LVL_SMQ,\n+\t\t\t\t\t OTX2_TM_LVL_SCH4, false, ¶ms);\n+\t\tif (rc)\n+\t\t\tgoto exit;\n+\n+\t\tleaf_parent = def + 4;\n+\t} else {\n+\t\tdev->otx2_tm_root_lvl = NIX_TXSCH_LVL_TL2;\n+\t\trc = nix_tm_node_add_to_list(dev, def, RTE_TM_NODE_ID_NULL, 0,\n+\t\t\t\t\t DEFAULT_RR_WEIGHT,\n+\t\t\t\t\t NIX_TXSCH_LVL_TL2,\n+\t\t\t\t\t OTX2_TM_LVL_ROOT, false, ¶ms);\n+\t\tif (rc)\n+\t\t\tgoto exit;\n+\n+\t\trc = nix_tm_node_add_to_list(dev, def + 1, def, 0,\n+\t\t\t\t\t DEFAULT_RR_WEIGHT,\n+\t\t\t\t\t NIX_TXSCH_LVL_TL3,\n+\t\t\t\t\t OTX2_TM_LVL_SCH1, false, ¶ms);\n+\t\tif (rc)\n+\t\t\tgoto exit;\n+\n+\t\trc = nix_tm_node_add_to_list(dev, def + 2, def + 1, 0,\n+\t\t\t\t\t DEFAULT_RR_WEIGHT,\n+\t\t\t\t\t NIX_TXSCH_LVL_TL4,\n+\t\t\t\t\t OTX2_TM_LVL_SCH2, false, ¶ms);\n+\t\tif (rc)\n+\t\t\tgoto exit;\n+\n+\t\trc = nix_tm_node_add_to_list(dev, def + 3, def + 2, 0,\n+\t\t\t\t\t DEFAULT_RR_WEIGHT,\n+\t\t\t\t\t NIX_TXSCH_LVL_SMQ,\n+\t\t\t\t\t OTX2_TM_LVL_SCH3, false, ¶ms);\n+\t\tif (rc)\n+\t\t\tgoto exit;\n+\n+\t\tleaf_parent = def + 3;\n+\t}\n+\n+\t/* Add leaf nodes */\n+\tfor (i = 0; i < eth_dev->data->nb_tx_queues; i++) {\n+\t\trc = nix_tm_node_add_to_list(dev, i, leaf_parent, 0,\n+\t\t\t\t\t DEFAULT_RR_WEIGHT,\n+\t\t\t\t\t NIX_TXSCH_LVL_CNT,\n+\t\t\t\t\t OTX2_TM_LVL_QUEUE, false, ¶ms);\n+\t\tif (rc)\n+\t\t\tbreak;\n+\t}\n+\n+exit:\n+\treturn rc;\n+}\n+\n+void otx2_nix_tm_conf_init(struct rte_eth_dev *eth_dev)\n+{\n+\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n+\n+\tTAILQ_INIT(&dev->node_list);\n+\tTAILQ_INIT(&dev->shaper_profile_list);\n+}\n+\n+int otx2_nix_tm_init_default(struct rte_eth_dev *eth_dev)\n+{\n+\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n+\tuint16_t sq_cnt = eth_dev->data->nb_tx_queues;\n+\tint rc;\n+\n+\t/* Clear shaper profiles */\n+\tnix_tm_clear_shaper_profiles(dev);\n+\tdev->tm_flags = NIX_TM_DEFAULT_TREE;\n+\n+\trc = nix_tm_prepare_default_tree(eth_dev);\n+\tif (rc != 0)\n+\t\treturn rc;\n+\n+\tdev->tm_leaf_cnt = sq_cnt;\n+\n+\treturn 0;\n+}\n+\n+int\n+otx2_nix_tm_fini(struct rte_eth_dev *eth_dev)\n+{\n+\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n+\n+\t/* Clear shaper profiles */\n+\tnix_tm_clear_shaper_profiles(dev);\n+\n+\tdev->tm_flags = 0;\n+\treturn 0;\n+}\ndiff --git a/drivers/net/octeontx2/otx2_tm.h b/drivers/net/octeontx2/otx2_tm.h\nnew file mode 100644\nindex 000000000..94023fa99\n--- /dev/null\n+++ b/drivers/net/octeontx2/otx2_tm.h\n@@ -0,0 +1,67 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2019 Marvell International Ltd.\n+ */\n+\n+#ifndef __OTX2_TM_H__\n+#define __OTX2_TM_H__\n+\n+#include <stdbool.h>\n+\n+#include <rte_tm_driver.h>\n+\n+#define NIX_TM_DEFAULT_TREE\tBIT_ULL(0)\n+\n+struct otx2_eth_dev;\n+\n+void otx2_nix_tm_conf_init(struct rte_eth_dev *eth_dev);\n+int otx2_nix_tm_init_default(struct rte_eth_dev *eth_dev);\n+int otx2_nix_tm_fini(struct rte_eth_dev *eth_dev);\n+\n+struct otx2_nix_tm_node {\n+\tTAILQ_ENTRY(otx2_nix_tm_node) node;\n+\tuint32_t id;\n+\tuint32_t hw_id;\n+\tuint32_t priority;\n+\tuint32_t weight;\n+\tuint16_t level_id;\n+\tuint16_t hw_lvl_id;\n+\tuint32_t rr_prio;\n+\tuint32_t rr_num;\n+\tuint32_t max_prio;\n+\tuint32_t parent_hw_id;\n+\tuint32_t flags;\n+#define NIX_TM_NODE_HWRES\tBIT_ULL(0)\n+#define NIX_TM_NODE_ENABLED\tBIT_ULL(1)\n+#define NIX_TM_NODE_USER\tBIT_ULL(2)\n+\tstruct otx2_nix_tm_node *parent;\n+\tstruct rte_tm_node_params params;\n+};\n+\n+struct otx2_nix_tm_shaper_profile {\n+\tTAILQ_ENTRY(otx2_nix_tm_shaper_profile) shaper;\n+\tuint32_t shaper_profile_id;\n+\tuint32_t reference_count;\n+\tstruct rte_tm_shaper_params profile;\n+};\n+\n+struct shaper_params {\n+\tuint64_t burst_exponent;\n+\tuint64_t burst_mantissa;\n+\tuint64_t div_exp;\n+\tuint64_t exponent;\n+\tuint64_t mantissa;\n+\tuint64_t burst;\n+\tuint64_t rate;\n+};\n+\n+TAILQ_HEAD(otx2_nix_tm_node_list, otx2_nix_tm_node);\n+TAILQ_HEAD(otx2_nix_tm_shaper_profile_list, otx2_nix_tm_shaper_profile);\n+\n+#define MAX_SCHED_WEIGHT ((uint8_t)~0)\n+#define NIX_TM_RR_QUANTUM_MAX ((1 << 24) - 1)\n+\n+/* DEFAULT_RR_WEIGHT * NIX_TM_RR_QUANTUM_MAX / MAX_SCHED_WEIGHT */\n+/* = NIX_MAX_HW_MTU */\n+#define DEFAULT_RR_WEIGHT 71\n+\n+#endif /* __OTX2_TM_H__ */\n", "prefixes": [ "v1", "21/58" ] }