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GET /api/patches/54072/?format=api
HTTP 200 OK
Allow: GET, PUT, PATCH, HEAD, OPTIONS
Content-Type: application/json
Vary: Accept

{
    "id": 54072,
    "url": "http://patches.dpdk.org/api/patches/54072/?format=api",
    "web_url": "http://patches.dpdk.org/project/dpdk/patch/20190602152434.23996-17-jerinj@marvell.com/",
    "project": {
        "id": 1,
        "url": "http://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<20190602152434.23996-17-jerinj@marvell.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/20190602152434.23996-17-jerinj@marvell.com",
    "date": "2019-06-02T15:23:52",
    "name": "[v1,16/58] net/octeontx2: add RSS support",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": true,
    "hash": "8634b3d440c3a948b1431e1a5a1c291b99592165",
    "submitter": {
        "id": 1188,
        "url": "http://patches.dpdk.org/api/people/1188/?format=api",
        "name": "Jerin Jacob Kollanukkaran",
        "email": "jerinj@marvell.com"
    },
    "delegate": {
        "id": 319,
        "url": "http://patches.dpdk.org/api/users/319/?format=api",
        "username": "fyigit",
        "first_name": "Ferruh",
        "last_name": "Yigit",
        "email": "ferruh.yigit@amd.com"
    },
    "mbox": "http://patches.dpdk.org/project/dpdk/patch/20190602152434.23996-17-jerinj@marvell.com/mbox/",
    "series": [
        {
            "id": 4848,
            "url": "http://patches.dpdk.org/api/series/4848/?format=api",
            "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=4848",
            "date": "2019-06-02T15:23:36",
            "name": "OCTEON TX2 Ethdev driver",
            "version": 1,
            "mbox": "http://patches.dpdk.org/series/4848/mbox/"
        }
    ],
    "comments": "http://patches.dpdk.org/api/patches/54072/comments/",
    "check": "fail",
    "checks": "http://patches.dpdk.org/api/patches/54072/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@dpdk.org",
        "Delivered-To": "patchwork@dpdk.org",
        "Received": [
            "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id DF38E1B9CA;\n\tSun,  2 Jun 2019 17:25:28 +0200 (CEST)",
            "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n\t[67.231.156.173]) by dpdk.org (Postfix) with ESMTP id 5AA4E1B9C9\n\tfor <dev@dpdk.org>; Sun,  2 Jun 2019 17:25:28 +0200 (CEST)",
            "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n\tby mx0b-0016f401.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id\n\tx52FKPIG020378; Sun, 2 Jun 2019 08:25:27 -0700",
            "from sc-exch04.marvell.com ([199.233.58.184])\n\tby mx0b-0016f401.pphosted.com with ESMTP id 2survk493n-1\n\t(version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); \n\tSun, 02 Jun 2019 08:25:27 -0700",
            "from SC-EXCH01.marvell.com (10.93.176.81) by SC-EXCH04.marvell.com\n\t(10.93.176.84) with Microsoft SMTP Server (TLS) id 15.0.1367.3;\n\tSun, 2 Jun 2019 08:25:26 -0700",
            "from maili.marvell.com (10.93.176.43) by SC-EXCH01.marvell.com\n\t(10.93.176.81) with Microsoft SMTP Server id 15.0.1367.3 via Frontend\n\tTransport; Sun, 2 Jun 2019 08:25:26 -0700",
            "from jerin-lab.marvell.com (jerin-lab.marvell.com [10.28.34.14])\n\tby maili.marvell.com (Postfix) with ESMTP id 380033F7040;\n\tSun,  2 Jun 2019 08:25:24 -0700 (PDT)"
        ],
        "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n\th=from : to : cc :\n\tsubject : date : message-id : in-reply-to : references : mime-version\n\t: content-transfer-encoding : content-type; s=pfpt0818;\n\tbh=hwf5kRqYT0WTUf3eBx006rkXpAOT5u9mNmpOZEiawjY=;\n\tb=a/gkQF3vJ6lGnHk24kaJGs6tjFrp4KFNr5tnCO81usIUWYHYb76Cx7QbGs4dBiTqRiok\n\tuJMr3lwnW+oEThgBlEX4sCiaAtXfxK40gLq1JKgozipgyZF41ZQ+Z+4shkk6bbDzsCrJ\n\te5Mvv9aXK6+3l0vFzwhTfzdrmGRgpzwHg1+ce2BrOAEmIkoCQpbntKujpVa7fueR9vyS\n\tet38CxTLp1AodSIHGws1FL/ArGE6BKMrceV9w+891UeJX/D1zAERHIWJi7NasM9XdXtj\n\t+Na75yKvwY88lulx/CCzfX0YxLF2XzqB+A+rEaPnE8B7NtQosGs8YHJQ8xPMbhClYkDq\n\tJg== ",
        "From": "<jerinj@marvell.com>",
        "To": "<dev@dpdk.org>, John McNamara <john.mcnamara@intel.com>, Marko Kovacevic\n\t<marko.kovacevic@intel.com>, Jerin Jacob <jerinj@marvell.com>, \"Nithin\n\tDabilpuram\" <ndabilpuram@marvell.com>, Kiran Kumar K\n\t<kirankumark@marvell.com>",
        "CC": "<ferruh.yigit@intel.com>, Vamsi Attunuru <vattunuru@marvell.com>",
        "Date": "Sun, 2 Jun 2019 20:53:52 +0530",
        "Message-ID": "<20190602152434.23996-17-jerinj@marvell.com>",
        "X-Mailer": "git-send-email 2.21.0",
        "In-Reply-To": "<20190602152434.23996-1-jerinj@marvell.com>",
        "References": "<20190602152434.23996-1-jerinj@marvell.com>",
        "MIME-Version": "1.0",
        "Content-Transfer-Encoding": "8bit",
        "Content-Type": "text/plain",
        "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:, ,\n\tdefinitions=2019-06-02_09:, , signatures=0",
        "Subject": "[dpdk-dev]  [PATCH v1 16/58] net/octeontx2: add RSS support",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.15",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "From: Vamsi Attunuru <vattunuru@marvell.com>\n\nAdd RSS support and expose RSS related functions\nto implement RSS action for rte_flow driver.\n\nSigned-off-by: Vamsi Attunuru <vattunuru@marvell.com>\nSigned-off-by: Kiran Kumar K <kirankumark@marvell.com>\n---\n doc/guides/nics/features/octeontx2.ini     |   4 +\n doc/guides/nics/features/octeontx2_vec.ini |   4 +\n doc/guides/nics/features/octeontx2_vf.ini  |   4 +\n drivers/net/octeontx2/Makefile             |   1 +\n drivers/net/octeontx2/meson.build          |   1 +\n drivers/net/octeontx2/otx2_ethdev.c        |  11 +\n drivers/net/octeontx2/otx2_ethdev.h        |  35 ++\n drivers/net/octeontx2/otx2_rss.c           | 378 +++++++++++++++++++++\n 8 files changed, 438 insertions(+)\n create mode 100644 drivers/net/octeontx2/otx2_rss.c",
    "diff": "diff --git a/doc/guides/nics/features/octeontx2.ini b/doc/guides/nics/features/octeontx2.ini\nindex cb77ab0fc..48ac58b3a 100644\n--- a/doc/guides/nics/features/octeontx2.ini\n+++ b/doc/guides/nics/features/octeontx2.ini\n@@ -15,6 +15,10 @@ Link status event    = Y\n Promiscuous mode     = Y\n Allmulticast mode    = Y\n Unicast MAC filter   = Y\n+RSS hash             = Y\n+RSS key update       = Y\n+RSS reta update      = Y\n+Inner RSS            = Y\n Basic stats          = Y\n Stats per queue      = Y\n Extended stats       = Y\ndiff --git a/doc/guides/nics/features/octeontx2_vec.ini b/doc/guides/nics/features/octeontx2_vec.ini\nindex a51291158..6fc647af4 100644\n--- a/doc/guides/nics/features/octeontx2_vec.ini\n+++ b/doc/guides/nics/features/octeontx2_vec.ini\n@@ -15,6 +15,10 @@ Link status event    = Y\n Promiscuous mode     = Y\n Allmulticast mode    = Y\n Unicast MAC filter   = Y\n+RSS hash             = Y\n+RSS key update       = Y\n+RSS reta update      = Y\n+Inner RSS            = Y\n Basic stats          = Y\n Extended stats       = Y\n Stats per queue      = Y\ndiff --git a/doc/guides/nics/features/octeontx2_vf.ini b/doc/guides/nics/features/octeontx2_vf.ini\nindex 89df760b3..af3c70269 100644\n--- a/doc/guides/nics/features/octeontx2_vf.ini\n+++ b/doc/guides/nics/features/octeontx2_vf.ini\n@@ -11,6 +11,10 @@ Lock-free Tx queue   = Y\n Multiprocess aware   = Y\n Link status          = Y\n Link status event    = Y\n+RSS hash             = Y\n+RSS key update       = Y\n+RSS reta update      = Y\n+Inner RSS            = Y\n Basic stats          = Y\n Extended stats       = Y\n Stats per queue      = Y\ndiff --git a/drivers/net/octeontx2/Makefile b/drivers/net/octeontx2/Makefile\nindex dcd692b7b..67352ec81 100644\n--- a/drivers/net/octeontx2/Makefile\n+++ b/drivers/net/octeontx2/Makefile\n@@ -30,6 +30,7 @@ LIBABIVER := 1\n # all source are stored in SRCS-y\n #\n SRCS-$(CONFIG_RTE_LIBRTE_OCTEONTX2_PMD) += \\\n+\totx2_rss.c\t\\\n \totx2_mac.c\t\\\n \totx2_link.c\t\\\n \totx2_stats.c\t\\\ndiff --git a/drivers/net/octeontx2/meson.build b/drivers/net/octeontx2/meson.build\nindex 384237104..b7e56e2ca 100644\n--- a/drivers/net/octeontx2/meson.build\n+++ b/drivers/net/octeontx2/meson.build\n@@ -3,6 +3,7 @@\n #\n \n sources = files(\n+\t\t'otx2_rss.c',\n \t\t'otx2_mac.c',\n \t\t'otx2_link.c',\n \t\t'otx2_stats.c',\ndiff --git a/drivers/net/octeontx2/otx2_ethdev.c b/drivers/net/octeontx2/otx2_ethdev.c\nindex a72c901f4..5289c79e8 100644\n--- a/drivers/net/octeontx2/otx2_ethdev.c\n+++ b/drivers/net/octeontx2/otx2_ethdev.c\n@@ -195,6 +195,13 @@ otx2_nix_configure(struct rte_eth_dev *eth_dev)\n \t\tgoto fail;\n \t}\n \n+\t/* Configure RSS */\n+\trc = otx2_nix_rss_config(eth_dev);\n+\tif (rc) {\n+\t\totx2_err(\"Failed to configure rss rc=%d\", rc);\n+\t\tgoto free_nix_lf;\n+\t}\n+\n \t/* Register queue IRQs */\n \trc = oxt2_nix_register_queue_irqs(eth_dev);\n \tif (rc) {\n@@ -245,6 +252,10 @@ static const struct eth_dev_ops otx2_eth_dev_ops = {\n \t.allmulticast_enable      = otx2_nix_allmulticast_enable,\n \t.allmulticast_disable     = otx2_nix_allmulticast_disable,\n \t.queue_stats_mapping_set  = otx2_nix_queue_stats_mapping,\n+\t.reta_update              = otx2_nix_dev_reta_update,\n+\t.reta_query               = otx2_nix_dev_reta_query,\n+\t.rss_hash_update          = otx2_nix_rss_hash_update,\n+\t.rss_hash_conf_get        = otx2_nix_rss_hash_conf_get,\n \t.xstats_get               = otx2_nix_xstats_get,\n \t.xstats_get_names         = otx2_nix_xstats_get_names,\n \t.xstats_reset             = otx2_nix_xstats_reset,\ndiff --git a/drivers/net/octeontx2/otx2_ethdev.h b/drivers/net/octeontx2/otx2_ethdev.h\nindex 8d0147afb..67b164740 100644\n--- a/drivers/net/octeontx2/otx2_ethdev.h\n+++ b/drivers/net/octeontx2/otx2_ethdev.h\n@@ -39,6 +39,9 @@\n #define NIX_MAX_HW_MTU\t\t\t9190\n #define NIX_MAX_HW_FRS\t\t\t(NIX_MAX_HW_MTU + NIX_HW_L2_OVERHEAD)\n #define NIX_MIN_HW_FRS\t\t\t60\n+#define NIX_MIN_SQB\t\t\t512\n+#define NIX_SQB_LIST_SPACE\t\t2\n+#define NIX_RSS_RETA_SIZE_MAX\t\t256\n /* Group 0 will be used for RSS, 1 -7 will be used for rte_flow RSS action*/\n #define NIX_RSS_GRPS\t\t\t8\n #define NIX_HASH_KEY_SIZE\t\t48 /* 352 Bits */\n@@ -92,14 +95,22 @@\n \tDEV_RX_OFFLOAD_QINQ_STRIP | \\\n \tDEV_RX_OFFLOAD_TIMESTAMP)\n \n+#define NIX_DEFAULT_RSS_CTX_GROUP  0\n+#define NIX_DEFAULT_RSS_MCAM_IDX  -1\n+\n struct otx2_qint {\n \tstruct rte_eth_dev *eth_dev;\n \tuint8_t qintx;\n };\n \n struct otx2_rss_info {\n+\tuint64_t nix_rss;\n+\tuint32_t flowkey_cfg;\n \tuint16_t rss_size;\n \tuint8_t rss_grps;\n+\tuint8_t alg_idx; /* Selected algo index */\n+\tuint16_t ind_tbl[NIX_RSS_RETA_SIZE_MAX];\n+\tuint8_t key[NIX_HASH_KEY_SIZE];\n };\n \n struct otx2_npc_flow_info {\n@@ -204,6 +215,30 @@ int otx2_nix_xstats_get_names_by_id(struct rte_eth_dev *eth_dev,\n \t\t\t\t    struct rte_eth_xstat_name *xstats_names,\n \t\t\t\t    const uint64_t *ids, unsigned int limit);\n \n+/* RSS */\n+void otx2_nix_rss_set_key(struct otx2_eth_dev *dev,\n+\t\t\t  uint8_t *key, uint32_t key_len);\n+uint32_t otx2_rss_ethdev_to_nix(struct otx2_eth_dev *dev,\n+\t\t\t\tuint64_t ethdev_rss, uint8_t rss_level);\n+int otx2_rss_set_hf(struct otx2_eth_dev *dev,\n+\t\t    uint32_t flowkey_cfg, uint8_t *alg_idx,\n+\t\t    uint8_t group, int mcam_index);\n+int otx2_nix_rss_tbl_init(struct otx2_eth_dev *dev, uint8_t group,\n+\t\t\t  uint16_t *ind_tbl);\n+int otx2_nix_rss_config(struct rte_eth_dev *eth_dev);\n+\n+int otx2_nix_dev_reta_update(struct rte_eth_dev *eth_dev,\n+\t\t\t     struct rte_eth_rss_reta_entry64 *reta_conf,\n+\t\t\t     uint16_t reta_size);\n+int otx2_nix_dev_reta_query(struct rte_eth_dev *eth_dev,\n+\t\t\t    struct rte_eth_rss_reta_entry64 *reta_conf,\n+\t\t\t    uint16_t reta_size);\n+int otx2_nix_rss_hash_update(struct rte_eth_dev *eth_dev,\n+\t\t\t     struct rte_eth_rss_conf *rss_conf);\n+\n+int otx2_nix_rss_hash_conf_get(struct rte_eth_dev *eth_dev,\n+\t\t\t       struct rte_eth_rss_conf *rss_conf);\n+\n /* CGX */\n int otx2_cgx_rxtx_start(struct otx2_eth_dev *dev);\n int otx2_cgx_rxtx_stop(struct otx2_eth_dev *dev);\ndiff --git a/drivers/net/octeontx2/otx2_rss.c b/drivers/net/octeontx2/otx2_rss.c\nnew file mode 100644\nindex 000000000..089846da7\n--- /dev/null\n+++ b/drivers/net/octeontx2/otx2_rss.c\n@@ -0,0 +1,378 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2019 Marvell International Ltd.\n+ */\n+\n+#include \"otx2_ethdev.h\"\n+\n+int\n+otx2_nix_rss_tbl_init(struct otx2_eth_dev *dev,\n+\t\t      uint8_t group, uint16_t *ind_tbl)\n+{\n+\tstruct otx2_rss_info *rss = &dev->rss_info;\n+\tstruct otx2_mbox *mbox = dev->mbox;\n+\tstruct nix_aq_enq_req *req;\n+\tint rc, idx;\n+\n+\tfor (idx = 0; idx < rss->rss_size; idx++) {\n+\t\treq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);\n+\t\tif (!req) {\n+\t\t\t/* The shared memory buffer can be full.\n+\t\t\t * Flush it and retry\n+\t\t\t */\n+\t\t\totx2_mbox_msg_send(mbox, 0);\n+\t\t\trc = otx2_mbox_wait_for_rsp(mbox, 0);\n+\t\t\tif (rc < 0)\n+\t\t\t\treturn rc;\n+\n+\t\t\treq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);\n+\t\t\tif (!req)\n+\t\t\t\treturn -ENOMEM;\n+\t\t}\n+\t\treq->rss.rq = ind_tbl[idx];\n+\t\t/* Fill AQ info */\n+\t\treq->qidx = (group * rss->rss_size) + idx;\n+\t\treq->ctype = NIX_AQ_CTYPE_RSS;\n+\t\treq->op = NIX_AQ_INSTOP_INIT;\n+\t}\n+\n+\totx2_mbox_msg_send(mbox, 0);\n+\trc = otx2_mbox_wait_for_rsp(mbox, 0);\n+\tif (rc < 0)\n+\t\treturn rc;\n+\n+\treturn 0;\n+}\n+\n+int\n+otx2_nix_dev_reta_update(struct rte_eth_dev *eth_dev,\n+\t\t\t struct rte_eth_rss_reta_entry64 *reta_conf,\n+\t\t\t uint16_t reta_size)\n+{\n+\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n+\tstruct otx2_rss_info *rss = &dev->rss_info;\n+\tint rc, i, j;\n+\tint idx = 0;\n+\n+\trc = -EINVAL;\n+\tif (reta_size != dev->rss_info.rss_size) {\n+\t\totx2_err(\"Size of hash lookup table configured \"\n+\t\t\"(%d) doesn't match the number hardware can supported \"\n+\t\t\"(%d)\", reta_size, dev->rss_info.rss_size);\n+\t\tgoto fail;\n+\t}\n+\n+\t/* Copy RETA table */\n+\tfor (i = 0; i < (dev->rss_info.rss_size / RTE_RETA_GROUP_SIZE); i++) {\n+\t\tfor (j = 0; j < RTE_RETA_GROUP_SIZE; j++) {\n+\t\t\tif ((reta_conf[i].mask >> j) & 0x01)\n+\t\t\t\trss->ind_tbl[idx] = reta_conf[i].reta[j];\n+\t\t\tidx++;\n+\t\t}\n+\t}\n+\n+\treturn otx2_nix_rss_tbl_init(dev, 0, dev->rss_info.ind_tbl);\n+\n+fail:\n+\treturn rc;\n+}\n+\n+int\n+otx2_nix_dev_reta_query(struct rte_eth_dev *eth_dev,\n+\t\t\tstruct rte_eth_rss_reta_entry64 *reta_conf,\n+\t\t\tuint16_t reta_size)\n+{\n+\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n+\tstruct otx2_rss_info *rss = &dev->rss_info;\n+\tint rc, i, j;\n+\n+\trc = -EINVAL;\n+\n+\tif (reta_size != dev->rss_info.rss_size) {\n+\t\totx2_err(\"Size of hash lookup table configured \"\n+\t\t\t\"(%d) doesn't match the number hardware can supported \"\n+\t\t\t\"(%d)\", reta_size, dev->rss_info.rss_size);\n+\t\tgoto fail;\n+\t}\n+\n+\t/* Copy RETA table */\n+\tfor (i = 0; i < (dev->rss_info.rss_size / RTE_RETA_GROUP_SIZE); i++) {\n+\t\tfor (j = 0; j < RTE_RETA_GROUP_SIZE; j++)\n+\t\t\tif ((reta_conf[i].mask >> j) & 0x01)\n+\t\t\t\treta_conf[i].reta[j] = rss->ind_tbl[j];\n+\t}\n+\n+\treturn 0;\n+\n+fail:\n+\treturn rc;\n+}\n+\n+void\n+otx2_nix_rss_set_key(struct otx2_eth_dev *dev, uint8_t *key,\n+\t\t     uint32_t key_len)\n+{\n+\tconst uint8_t default_key[NIX_HASH_KEY_SIZE] = {\n+\t\t0xFE, 0xED, 0x0B, 0xAD, 0xFE, 0xED, 0x0B, 0xAD,\n+\t\t0xFE, 0xED, 0x0B, 0xAD, 0xFE, 0xED, 0x0B, 0xAD,\n+\t\t0xFE, 0xED, 0x0B, 0xAD, 0xFE, 0xED, 0x0B, 0xAD,\n+\t\t0xFE, 0xED, 0x0B, 0xAD, 0xFE, 0xED, 0x0B, 0xAD,\n+\t\t0xFE, 0xED, 0x0B, 0xAD, 0xFE, 0xED, 0x0B, 0xAD,\n+\t\t0xFE, 0xED, 0x0B, 0xAD, 0xFE, 0xED, 0x0B, 0xAD\n+\t};\n+\tstruct otx2_rss_info *rss = &dev->rss_info;\n+\tuint64_t *keyptr;\n+\tuint64_t val;\n+\tuint32_t idx;\n+\n+\tif (key == NULL || key == 0) {\n+\t\tkeyptr = (uint64_t *)(uintptr_t)default_key;\n+\t\tkey_len = NIX_HASH_KEY_SIZE;\n+\t\tmemset(rss->key, 0, key_len);\n+\t} else {\n+\t\tmemcpy(rss->key, key, key_len);\n+\t\tkeyptr = (uint64_t *)rss->key;\n+\t}\n+\n+\tfor (idx = 0; idx < (key_len >> 3); idx++) {\n+\t\tval = rte_cpu_to_be_64(*keyptr);\n+\t\totx2_write64(val, dev->base + NIX_LF_RX_SECRETX(idx));\n+\t\tkeyptr++;\n+\t}\n+}\n+\n+static void\n+rss_get_key(struct otx2_eth_dev *dev, uint8_t *key)\n+{\n+\tuint64_t *keyptr = (uint64_t *)key;\n+\tuint64_t val;\n+\tint idx;\n+\n+\tfor (idx = 0; idx < (NIX_HASH_KEY_SIZE >> 3); idx++) {\n+\t\tval = otx2_read64(dev->base + NIX_LF_RX_SECRETX(idx));\n+\t\t*keyptr = rte_be_to_cpu_64(val);\n+\t\tkeyptr++;\n+\t}\n+}\n+\n+#define RSS_IPV4_ENABLE ( \\\n+\t\t\t  ETH_RSS_IPV4 | \\\n+\t\t\t  ETH_RSS_FRAG_IPV4 | \\\n+\t\t\t  ETH_RSS_NONFRAG_IPV4_UDP | \\\n+\t\t\t  ETH_RSS_NONFRAG_IPV4_TCP | \\\n+\t\t\t  ETH_RSS_NONFRAG_IPV4_SCTP)\n+\n+#define RSS_IPV6_ENABLE ( \\\n+\t\t\t  ETH_RSS_IPV6 | \\\n+\t\t\t  ETH_RSS_FRAG_IPV6 | \\\n+\t\t\t  ETH_RSS_NONFRAG_IPV6_UDP | \\\n+\t\t\t  ETH_RSS_NONFRAG_IPV6_TCP | \\\n+\t\t\t  ETH_RSS_NONFRAG_IPV6_SCTP)\n+\n+#define RSS_IPV6_EX_ENABLE ( \\\n+\t\t\t     ETH_RSS_IPV6_EX | \\\n+\t\t\t     ETH_RSS_IPV6_TCP_EX | \\\n+\t\t\t     ETH_RSS_IPV6_UDP_EX)\n+\n+#define RSS_MAX_LEVELS   3\n+\n+#define RSS_IPV4_INDEX   0\n+#define RSS_IPV6_INDEX   1\n+#define RSS_TCP_INDEX    2\n+#define RSS_UDP_INDEX    3\n+#define RSS_SCTP_INDEX   4\n+#define RSS_DMAC_INDEX   5\n+\n+uint32_t\n+otx2_rss_ethdev_to_nix(struct otx2_eth_dev *dev, uint64_t ethdev_rss,\n+\t\t       uint8_t rss_level)\n+{\n+\tuint32_t flow_key_type[RSS_MAX_LEVELS][6] = {\n+\t\t{\n+\t\t\tFLOW_KEY_TYPE_IPV4, FLOW_KEY_TYPE_IPV6,\n+\t\t\tFLOW_KEY_TYPE_TCP, FLOW_KEY_TYPE_UDP,\n+\t\t\tFLOW_KEY_TYPE_SCTP, FLOW_KEY_TYPE_ETH_DMAC\n+\t\t},\n+\t\t{\n+\t\t\tFLOW_KEY_TYPE_INNR_IPV4, FLOW_KEY_TYPE_INNR_IPV6,\n+\t\t\tFLOW_KEY_TYPE_INNR_TCP, FLOW_KEY_TYPE_INNR_UDP,\n+\t\t\tFLOW_KEY_TYPE_INNR_SCTP, FLOW_KEY_TYPE_INNR_ETH_DMAC\n+\t\t},\n+\t\t{\n+\t\t\tFLOW_KEY_TYPE_IPV4 | FLOW_KEY_TYPE_INNR_IPV4,\n+\t\t\tFLOW_KEY_TYPE_IPV6 | FLOW_KEY_TYPE_INNR_IPV6,\n+\t\t\tFLOW_KEY_TYPE_TCP | FLOW_KEY_TYPE_INNR_TCP,\n+\t\t\tFLOW_KEY_TYPE_UDP | FLOW_KEY_TYPE_INNR_UDP,\n+\t\t\tFLOW_KEY_TYPE_SCTP | FLOW_KEY_TYPE_INNR_SCTP,\n+\t\t\tFLOW_KEY_TYPE_ETH_DMAC | FLOW_KEY_TYPE_INNR_ETH_DMAC\n+\t\t}\n+\t};\n+\tuint32_t flowkey_cfg = 0;\n+\n+\tdev->rss_info.nix_rss = ethdev_rss;\n+\n+\tif (ethdev_rss & RSS_IPV4_ENABLE)\n+\t\tflowkey_cfg |= flow_key_type[rss_level][RSS_IPV4_INDEX];\n+\n+\tif (ethdev_rss & RSS_IPV6_ENABLE)\n+\t\tflowkey_cfg |= flow_key_type[rss_level][RSS_IPV6_INDEX];\n+\n+\tif (ethdev_rss & ETH_RSS_TCP)\n+\t\tflowkey_cfg |= flow_key_type[rss_level][RSS_TCP_INDEX];\n+\n+\tif (ethdev_rss & ETH_RSS_UDP)\n+\t\tflowkey_cfg |= flow_key_type[rss_level][RSS_UDP_INDEX];\n+\n+\tif (ethdev_rss & ETH_RSS_SCTP)\n+\t\tflowkey_cfg |= flow_key_type[rss_level][RSS_SCTP_INDEX];\n+\n+\tif (ethdev_rss & ETH_RSS_L2_PAYLOAD)\n+\t\tflowkey_cfg |= flow_key_type[rss_level][RSS_DMAC_INDEX];\n+\n+\tif (ethdev_rss & RSS_IPV6_EX_ENABLE)\n+\t\tflowkey_cfg |= FLOW_KEY_TYPE_IPV6_EXT;\n+\n+\tif (ethdev_rss & ETH_RSS_PORT)\n+\t\tflowkey_cfg |= FLOW_KEY_TYPE_PORT;\n+\n+\tif (ethdev_rss & ETH_RSS_NVGRE)\n+\t\tflowkey_cfg |= FLOW_KEY_TYPE_NVGRE;\n+\n+\tif (ethdev_rss & ETH_RSS_VXLAN) {\n+\t\tflowkey_cfg |= FLOW_KEY_TYPE_VXLAN;\n+\t\tif (flowkey_cfg & FLOW_KEY_TYPE_UDP)\n+\t\t\tflowkey_cfg |= FLOW_KEY_TYPE_UDP_VXLAN;\n+\t}\n+\n+\tif (ethdev_rss & ETH_RSS_GENEVE) {\n+\t\tflowkey_cfg |= FLOW_KEY_TYPE_GENEVE;\n+\t\tif (flowkey_cfg & FLOW_KEY_TYPE_UDP)\n+\t\t\tflowkey_cfg |= FLOW_KEY_TYPE_UDP_GENEVE;\n+\t}\n+\n+\treturn flowkey_cfg;\n+}\n+\n+int\n+otx2_rss_set_hf(struct otx2_eth_dev *dev, uint32_t flowkey_cfg,\n+\t\tuint8_t *alg_idx, uint8_t group, int mcam_index)\n+{\n+\tstruct nix_rss_flowkey_cfg_rsp *rss_rsp;\n+\tstruct otx2_mbox *mbox = dev->mbox;\n+\tstruct nix_rss_flowkey_cfg *cfg;\n+\tint rc;\n+\n+\trc = -EINVAL;\n+\n+\tdev->rss_info.flowkey_cfg = flowkey_cfg;\n+\n+\tcfg = otx2_mbox_alloc_msg_nix_rss_flowkey_cfg(mbox);\n+\n+\tcfg->flowkey_cfg = flowkey_cfg;\n+\tcfg->mcam_index = mcam_index; /* -1 indicates default group */\n+\tcfg->group = group; /* 0 is default group */\n+\n+\trc = otx2_mbox_process_msg(mbox, (void *)&rss_rsp);\n+\tif (rc)\n+\t\treturn rc;\n+\n+\tif (alg_idx)\n+\t\t*alg_idx = rss_rsp->alg_idx;\n+\n+\treturn rc;\n+}\n+\n+int\n+otx2_nix_rss_hash_update(struct rte_eth_dev *eth_dev,\n+\t\t\t struct rte_eth_rss_conf *rss_conf)\n+{\n+\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n+\tuint32_t flowkey_cfg;\n+\tuint8_t alg_idx;\n+\tint rc;\n+\n+\trc = -EINVAL;\n+\n+\tif (rss_conf->rss_key && rss_conf->rss_key_len != NIX_HASH_KEY_SIZE) {\n+\t\totx2_err(\"Hash key size mismatch %d vs %d\",\n+\t\t\t rss_conf->rss_key_len, NIX_HASH_KEY_SIZE);\n+\t\tgoto fail;\n+\t}\n+\n+\tif (rss_conf->rss_key)\n+\t\totx2_nix_rss_set_key(dev, rss_conf->rss_key,\n+\t\t\t\t     (uint32_t)rss_conf->rss_key_len);\n+\n+\tflowkey_cfg = otx2_rss_ethdev_to_nix(dev, rss_conf->rss_hf, 0);\n+\n+\trc = otx2_rss_set_hf(dev, flowkey_cfg, &alg_idx,\n+\t\t\t     NIX_DEFAULT_RSS_CTX_GROUP,\n+\t\t\t     NIX_DEFAULT_RSS_MCAM_IDX);\n+\tif (rc) {\n+\t\totx2_err(\"Failed to set RSS hash function rc=%d\", rc);\n+\t\treturn rc;\n+\t}\n+\n+\tdev->rss_info.alg_idx = alg_idx;\n+\n+fail:\n+\treturn rc;\n+}\n+\n+int\n+otx2_nix_rss_hash_conf_get(struct rte_eth_dev *eth_dev,\n+\t\t\t   struct rte_eth_rss_conf *rss_conf)\n+{\n+\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n+\n+\tif (rss_conf->rss_key)\n+\t\trss_get_key(dev, rss_conf->rss_key);\n+\n+\trss_conf->rss_key_len = NIX_HASH_KEY_SIZE;\n+\trss_conf->rss_hf = dev->rss_info.nix_rss;\n+\n+\treturn 0;\n+}\n+\n+int\n+otx2_nix_rss_config(struct rte_eth_dev *eth_dev)\n+{\n+\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n+\tuint32_t idx, qcnt = eth_dev->data->nb_rx_queues;\n+\tuint32_t flowkey_cfg;\n+\tuint64_t rss_hf;\n+\tuint8_t alg_idx;\n+\tint rc;\n+\n+\t/* Skip further configuration if selected mode is not RSS */\n+\tif (eth_dev->data->dev_conf.rxmode.mq_mode != ETH_MQ_RX_RSS)\n+\t\treturn 0;\n+\n+\t/* Update default RSS key and cfg */\n+\totx2_nix_rss_set_key(dev, NULL, 0);\n+\n+\t/* Update default RSS RETA */\n+\tfor (idx = 0; idx < dev->rss_info.rss_size; idx++)\n+\t\tdev->rss_info.ind_tbl[idx] = idx % qcnt;\n+\n+\t/* Init RSS table context */\n+\trc = otx2_nix_rss_tbl_init(dev, 0, dev->rss_info.ind_tbl);\n+\tif (rc) {\n+\t\totx2_err(\"Failed to init RSS table rc=%d\", rc);\n+\t\treturn rc;\n+\t}\n+\n+\trss_hf = eth_dev->data->dev_conf.rx_adv_conf.rss_conf.rss_hf;\n+\tflowkey_cfg = otx2_rss_ethdev_to_nix(dev, rss_hf, 0);\n+\n+\trc = otx2_rss_set_hf(dev, flowkey_cfg, &alg_idx,\n+\t\t\t     NIX_DEFAULT_RSS_CTX_GROUP,\n+\t\t\t     NIX_DEFAULT_RSS_MCAM_IDX);\n+\tif (rc) {\n+\t\totx2_err(\"Failed to set RSS hash function rc=%d\", rc);\n+\t\treturn rc;\n+\t}\n+\n+\tdev->rss_info.alg_idx = alg_idx;\n+\n+\treturn 0;\n+}\n",
    "prefixes": [
        "v1",
        "16/58"
    ]
}