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GET /api/patches/54069/?format=api
{ "id": 54069, "url": "http://patches.dpdk.org/api/patches/54069/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20190602152434.23996-14-jerinj@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20190602152434.23996-14-jerinj@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20190602152434.23996-14-jerinj@marvell.com", "date": "2019-06-02T15:23:49", "name": "[v1,13/58] net/octeontx2: add extended stats operations", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "532426dc56c3e6779370fd03dc51a9216f4dc6d3", "submitter": { "id": 1188, "url": "http://patches.dpdk.org/api/people/1188/?format=api", "name": "Jerin Jacob Kollanukkaran", "email": "jerinj@marvell.com" }, "delegate": { "id": 319, "url": "http://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20190602152434.23996-14-jerinj@marvell.com/mbox/", "series": [ { "id": 4848, "url": "http://patches.dpdk.org/api/series/4848/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=4848", "date": "2019-06-02T15:23:36", "name": "OCTEON TX2 Ethdev driver", "version": 1, "mbox": "http://patches.dpdk.org/series/4848/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/54069/comments/", "check": "fail", "checks": "http://patches.dpdk.org/api/patches/54069/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id DDA121B956;\n\tSun, 2 Jun 2019 17:25:19 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n\t[67.231.156.173]) by dpdk.org (Postfix) with ESMTP id BBFD51B956\n\tfor <dev@dpdk.org>; Sun, 2 Jun 2019 17:25:18 +0200 (CEST)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n\tby mx0b-0016f401.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id\n\tx52FLOCS021032; Sun, 2 Jun 2019 08:25:18 -0700", "from sc-exch01.marvell.com ([199.233.58.181])\n\tby mx0b-0016f401.pphosted.com with ESMTP id 2survk492x-1\n\t(version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); \n\tSun, 02 Jun 2019 08:25:18 -0700", "from SC-EXCH01.marvell.com (10.93.176.81) by SC-EXCH01.marvell.com\n\t(10.93.176.81) with Microsoft SMTP Server (TLS) id 15.0.1367.3;\n\tSun, 2 Jun 2019 08:25:16 -0700", "from maili.marvell.com (10.93.176.43) by SC-EXCH01.marvell.com\n\t(10.93.176.81) with Microsoft SMTP Server id 15.0.1367.3 via Frontend\n\tTransport; Sun, 2 Jun 2019 08:25:16 -0700", "from jerin-lab.marvell.com (jerin-lab.marvell.com [10.28.34.14])\n\tby maili.marvell.com (Postfix) with ESMTP id 4BC2B3F7040;\n\tSun, 2 Jun 2019 08:25:14 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n\th=from : to : cc :\n\tsubject : date : message-id : in-reply-to : references : mime-version\n\t: content-transfer-encoding : content-type; s=pfpt0818;\n\tbh=lxc6PC4TyuWV/HS4BW2ZzYwqA/xjR9gK9Cd4+C7wIOQ=;\n\tb=pkGPjr+BJRJ+tVwS+sw7vaTXSwZD+pvE/vM6PsJqejLTw6Zet4logSLHWg7VRk6T3P8j\n\tWHZGIb4aFX3onpXO+6VngdScd/czoGS2TQoLR9v6LV0Wyiuk/1ytohPwv4SFXwq7Dwmu\n\tlexaC2ddvjPyK4aVcbTdW1OqqeMr7+XBx/iPgWGyceYXRY4m3DBD6OsxoRHTcJJRjQ7A\n\t4a67lmS5nDnhNEK6RGoRpMjlrLijCNR2SP5f/dy1FZnivjGCshr+kd3dppGWQvT2Og3w\n\t0B7uvB2HX33ohkIZ7pSKLVckiALRBfdneumxtueJAIvyr8G+jU2IOF4p+Z/I82jyhH5y\n\tOA== ", "From": "<jerinj@marvell.com>", "To": "<dev@dpdk.org>, John McNamara <john.mcnamara@intel.com>, Marko Kovacevic\n\t<marko.kovacevic@intel.com>, Jerin Jacob <jerinj@marvell.com>, \"Nithin\n\tDabilpuram\" <ndabilpuram@marvell.com>, Kiran Kumar K\n\t<kirankumark@marvell.com>", "CC": "<ferruh.yigit@intel.com>, Vamsi Attunuru <vattunuru@marvell.com>", "Date": "Sun, 2 Jun 2019 20:53:49 +0530", "Message-ID": "<20190602152434.23996-14-jerinj@marvell.com>", "X-Mailer": "git-send-email 2.21.0", "In-Reply-To": "<20190602152434.23996-1-jerinj@marvell.com>", "References": "<20190602152434.23996-1-jerinj@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:, ,\n\tdefinitions=2019-06-02_09:, , signatures=0", "Subject": "[dpdk-dev] [PATCH v1 13/58] net/octeontx2: add extended stats\n\toperations", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Kiran Kumar K <kirankumark@marvell.com>\n\nAdd extended operations and updated the feature list.\n\nSigned-off-by: Kiran Kumar K <kirankumark@marvell.com>\nSigned-off-by: Vamsi Attunuru <vattunuru@marvell.com>\n---\n doc/guides/nics/features/octeontx2.ini | 1 +\n doc/guides/nics/features/octeontx2_vec.ini | 1 +\n doc/guides/nics/features/octeontx2_vf.ini | 1 +\n drivers/net/octeontx2/otx2_ethdev.c | 5 +\n drivers/net/octeontx2/otx2_ethdev.h | 13 +\n drivers/net/octeontx2/otx2_stats.c | 270 +++++++++++++++++++++\n 6 files changed, 291 insertions(+)", "diff": "diff --git a/doc/guides/nics/features/octeontx2.ini b/doc/guides/nics/features/octeontx2.ini\nindex 72336ae15..3835b5069 100644\n--- a/doc/guides/nics/features/octeontx2.ini\n+++ b/doc/guides/nics/features/octeontx2.ini\n@@ -14,4 +14,5 @@ Link status = Y\n Link status event = Y\n Basic stats = Y\n Stats per queue = Y\n+Extended stats = Y\n Registers dump = Y\ndiff --git a/doc/guides/nics/features/octeontx2_vec.ini b/doc/guides/nics/features/octeontx2_vec.ini\nindex 0f3850188..e18443742 100644\n--- a/doc/guides/nics/features/octeontx2_vec.ini\n+++ b/doc/guides/nics/features/octeontx2_vec.ini\n@@ -13,5 +13,6 @@ Multiprocess aware = Y\n Link status = Y\n Link status event = Y\n Basic stats = Y\n+Extended stats = Y\n Stats per queue = Y\n Registers dump = Y\ndiff --git a/doc/guides/nics/features/octeontx2_vf.ini b/doc/guides/nics/features/octeontx2_vf.ini\nindex 8bc72c4fb..89df760b3 100644\n--- a/doc/guides/nics/features/octeontx2_vf.ini\n+++ b/doc/guides/nics/features/octeontx2_vf.ini\n@@ -12,5 +12,6 @@ Multiprocess aware = Y\n Link status = Y\n Link status event = Y\n Basic stats = Y\n+Extended stats = Y\n Stats per queue = Y\n Registers dump = Y\ndiff --git a/drivers/net/octeontx2/otx2_ethdev.c b/drivers/net/octeontx2/otx2_ethdev.c\nindex 5787029d9..937ba6399 100644\n--- a/drivers/net/octeontx2/otx2_ethdev.c\n+++ b/drivers/net/octeontx2/otx2_ethdev.c\n@@ -238,6 +238,11 @@ static const struct eth_dev_ops otx2_eth_dev_ops = {\n \t.stats_reset = otx2_nix_dev_stats_reset,\n \t.get_reg = otx2_nix_dev_get_reg,\n \t.queue_stats_mapping_set = otx2_nix_queue_stats_mapping,\n+\t.xstats_get = otx2_nix_xstats_get,\n+\t.xstats_get_names = otx2_nix_xstats_get_names,\n+\t.xstats_reset = otx2_nix_xstats_reset,\n+\t.xstats_get_by_id = otx2_nix_xstats_get_by_id,\n+\t.xstats_get_names_by_id = otx2_nix_xstats_get_names_by_id,\n };\n \n static inline int\ndiff --git a/drivers/net/octeontx2/otx2_ethdev.h b/drivers/net/octeontx2/otx2_ethdev.h\nindex c9366a9ed..223dd5a5a 100644\n--- a/drivers/net/octeontx2/otx2_ethdev.h\n+++ b/drivers/net/octeontx2/otx2_ethdev.h\n@@ -184,6 +184,19 @@ void otx2_nix_dev_stats_reset(struct rte_eth_dev *eth_dev);\n int otx2_nix_queue_stats_mapping(struct rte_eth_dev *dev,\n \t\t\t\t uint16_t queue_id, uint8_t stat_idx,\n \t\t\t\t uint8_t is_rx);\n+int otx2_nix_xstats_get(struct rte_eth_dev *eth_dev,\n+\t\t\tstruct rte_eth_xstat *xstats, unsigned int n);\n+int otx2_nix_xstats_get_names(struct rte_eth_dev *eth_dev,\n+\t\t\t struct rte_eth_xstat_name *xstats_names,\n+\t\t\t unsigned int limit);\n+void otx2_nix_xstats_reset(struct rte_eth_dev *eth_dev);\n+\n+int otx2_nix_xstats_get_by_id(struct rte_eth_dev *eth_dev,\n+\t\t\t const uint64_t *ids,\n+\t\t\t uint64_t *values, unsigned int n);\n+int otx2_nix_xstats_get_names_by_id(struct rte_eth_dev *eth_dev,\n+\t\t\t\t struct rte_eth_xstat_name *xstats_names,\n+\t\t\t\t const uint64_t *ids, unsigned int limit);\n \n /* CGX */\n int otx2_cgx_rxtx_start(struct otx2_eth_dev *dev);\ndiff --git a/drivers/net/octeontx2/otx2_stats.c b/drivers/net/octeontx2/otx2_stats.c\nindex ade0f6ad6..deb83b704 100644\n--- a/drivers/net/octeontx2/otx2_stats.c\n+++ b/drivers/net/octeontx2/otx2_stats.c\n@@ -6,6 +6,45 @@\n \n #include \"otx2_ethdev.h\"\n \n+struct otx2_nix_xstats_name {\n+\tchar name[RTE_ETH_XSTATS_NAME_SIZE];\n+\tuint32_t offset;\n+};\n+\n+static const struct otx2_nix_xstats_name nix_tx_xstats[] = {\n+\t{\"tx_ucast\", NIX_STAT_LF_TX_TX_UCAST},\n+\t{\"tx_bcast\", NIX_STAT_LF_TX_TX_BCAST},\n+\t{\"tx_mcast\", NIX_STAT_LF_TX_TX_MCAST},\n+\t{\"tx_drop\", NIX_STAT_LF_TX_TX_DROP},\n+\t{\"tx_octs\", NIX_STAT_LF_TX_TX_OCTS},\n+};\n+\n+static const struct otx2_nix_xstats_name nix_rx_xstats[] = {\n+\t{\"rx_octs\", NIX_STAT_LF_RX_RX_OCTS},\n+\t{\"rx_ucast\", NIX_STAT_LF_RX_RX_UCAST},\n+\t{\"rx_bcast\", NIX_STAT_LF_RX_RX_BCAST},\n+\t{\"rx_mcast\", NIX_STAT_LF_RX_RX_MCAST},\n+\t{\"rx_drop\", NIX_STAT_LF_RX_RX_DROP},\n+\t{\"rx_drop_octs\", NIX_STAT_LF_RX_RX_DROP_OCTS},\n+\t{\"rx_fcs\", NIX_STAT_LF_RX_RX_FCS},\n+\t{\"rx_err\", NIX_STAT_LF_RX_RX_ERR},\n+\t{\"rx_drp_bcast\", NIX_STAT_LF_RX_RX_DRP_BCAST},\n+\t{\"rx_drp_mcast\", NIX_STAT_LF_RX_RX_DRP_MCAST},\n+\t{\"rx_drp_l3bcast\", NIX_STAT_LF_RX_RX_DRP_L3BCAST},\n+\t{\"rx_drp_l3mcast\", NIX_STAT_LF_RX_RX_DRP_L3MCAST},\n+};\n+\n+static const struct otx2_nix_xstats_name nix_q_xstats[] = {\n+\t{\"rq_op_re_pkts\", NIX_LF_RQ_OP_RE_PKTS},\n+};\n+\n+#define OTX2_NIX_NUM_RX_XSTATS RTE_DIM(nix_rx_xstats)\n+#define OTX2_NIX_NUM_TX_XSTATS RTE_DIM(nix_tx_xstats)\n+#define OTX2_NIX_NUM_QUEUE_XSTATS RTE_DIM(nix_q_xstats)\n+\n+#define OTX2_NIX_NUM_XSTATS_REG (OTX2_NIX_NUM_RX_XSTATS + \\\n+\t\tOTX2_NIX_NUM_TX_XSTATS + OTX2_NIX_NUM_QUEUE_XSTATS)\n+\n int\n otx2_nix_dev_stats_get(struct rte_eth_dev *eth_dev,\n \t\t struct rte_eth_stats *stats)\n@@ -115,3 +154,234 @@ otx2_nix_queue_stats_mapping(struct rte_eth_dev *eth_dev, uint16_t queue_id,\n \n \treturn 0;\n }\n+\n+int\n+otx2_nix_xstats_get(struct rte_eth_dev *eth_dev,\n+\t\t struct rte_eth_xstat *xstats,\n+\t\t unsigned int n)\n+{\n+\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n+\tunsigned int i, count = 0;\n+\tuint64_t reg, val;\n+\n+\tif (n < OTX2_NIX_NUM_XSTATS_REG)\n+\t\treturn OTX2_NIX_NUM_XSTATS_REG;\n+\n+\tif (xstats == NULL)\n+\t\treturn 0;\n+\n+\tfor (i = 0; i < OTX2_NIX_NUM_TX_XSTATS; i++) {\n+\t\txstats[count].value = otx2_read64(dev->base +\n+\t\tNIX_LF_TX_STATX(nix_tx_xstats[i].offset));\n+\t\txstats[count].id = count;\n+\t\tcount++;\n+\t}\n+\n+\tfor (i = 0; i < OTX2_NIX_NUM_RX_XSTATS; i++) {\n+\t\txstats[count].value = otx2_read64(dev->base +\n+\t\tNIX_LF_RX_STATX(nix_rx_xstats[i].offset));\n+\t\txstats[count].id = count;\n+\t\tcount++;\n+\t}\n+\n+\tfor (i = 0; i < eth_dev->data->nb_rx_queues; i++) {\n+\t\treg = (((uint64_t)i) << 32);\n+\t\tval = otx2_atomic64_add_nosync(reg, (int64_t *)(dev->base +\n+\t\t\t\t\t nix_q_xstats[0].offset));\n+\t\tif (val & OP_ERR)\n+\t\t\tval = 0;\n+\t\txstats[count].value += val;\n+\t}\n+\txstats[count].id = count;\n+\tcount++;\n+\n+\treturn count;\n+}\n+\n+int\n+otx2_nix_xstats_get_names(struct rte_eth_dev *eth_dev,\n+\t\t\t struct rte_eth_xstat_name *xstats_names,\n+\t\t\t unsigned int limit)\n+{\n+\tunsigned int i, count = 0;\n+\n+\tRTE_SET_USED(eth_dev);\n+\n+\tif (limit < OTX2_NIX_NUM_XSTATS_REG && xstats_names != NULL)\n+\t\treturn -ENOMEM;\n+\n+\tif (xstats_names) {\n+\t\tfor (i = 0; i < OTX2_NIX_NUM_TX_XSTATS; i++) {\n+\t\t\tsnprintf(xstats_names[count].name,\n+\t\t\t\t sizeof(xstats_names[count].name),\n+\t\t\t\t \"%s\", nix_tx_xstats[i].name);\n+\t\t\tcount++;\n+\t\t}\n+\n+\t\tfor (i = 0; i < OTX2_NIX_NUM_RX_XSTATS; i++) {\n+\t\t\tsnprintf(xstats_names[count].name,\n+\t\t\t\t sizeof(xstats_names[count].name),\n+\t\t\t\t \"%s\", nix_rx_xstats[i].name);\n+\t\t\tcount++;\n+\t\t}\n+\n+\t\tfor (i = 0; i < OTX2_NIX_NUM_QUEUE_XSTATS; i++) {\n+\t\t\tsnprintf(xstats_names[count].name,\n+\t\t\t\t sizeof(xstats_names[count].name),\n+\t\t\t\t \"%s\", nix_q_xstats[i].name);\n+\t\t\tcount++;\n+\t\t}\n+\t}\n+\n+\treturn OTX2_NIX_NUM_XSTATS_REG;\n+}\n+\n+int\n+otx2_nix_xstats_get_names_by_id(struct rte_eth_dev *eth_dev,\n+\t\t\t\tstruct rte_eth_xstat_name *xstats_names,\n+\t\t\t\tconst uint64_t *ids, unsigned int limit)\n+{\n+\tstruct rte_eth_xstat_name xstats_names_copy[OTX2_NIX_NUM_XSTATS_REG];\n+\tuint16_t i;\n+\n+\tif (limit < OTX2_NIX_NUM_XSTATS_REG && ids == NULL)\n+\t\treturn OTX2_NIX_NUM_XSTATS_REG;\n+\n+\tif (limit > OTX2_NIX_NUM_XSTATS_REG)\n+\t\treturn -EINVAL;\n+\n+\tif (xstats_names == NULL)\n+\t\treturn -ENOMEM;\n+\n+\totx2_nix_xstats_get_names(eth_dev, xstats_names_copy, limit);\n+\n+\tfor (i = 0; i < OTX2_NIX_NUM_XSTATS_REG; i++) {\n+\t\tif (ids[i] >= OTX2_NIX_NUM_XSTATS_REG) {\n+\t\t\totx2_err(\"Invalid id value\");\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\t\tstrncpy(xstats_names[i].name, xstats_names_copy[ids[i]].name,\n+\t\t\tsizeof(xstats_names[i].name));\n+\t}\n+\n+\treturn limit;\n+}\n+\n+int\n+otx2_nix_xstats_get_by_id(struct rte_eth_dev *eth_dev, const uint64_t *ids,\n+\t\t\t uint64_t *values, unsigned int n)\n+{\n+\tstruct rte_eth_xstat xstats[OTX2_NIX_NUM_XSTATS_REG];\n+\tuint16_t i;\n+\n+\tif (n < OTX2_NIX_NUM_XSTATS_REG && ids == NULL)\n+\t\treturn OTX2_NIX_NUM_XSTATS_REG;\n+\n+\tif (n > OTX2_NIX_NUM_XSTATS_REG)\n+\t\treturn -EINVAL;\n+\n+\tif (values == NULL)\n+\t\treturn -ENOMEM;\n+\n+\totx2_nix_xstats_get(eth_dev, xstats, n);\n+\n+\tfor (i = 0; i < OTX2_NIX_NUM_XSTATS_REG; i++) {\n+\t\tif (ids[i] >= OTX2_NIX_NUM_XSTATS_REG) {\n+\t\t\totx2_err(\"Invalid id value\");\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\t\tvalues[i] = xstats[ids[i]].value;\n+\t}\n+\n+\treturn n;\n+}\n+\n+static void\n+nix_queue_stats_reset(struct rte_eth_dev *eth_dev)\n+{\n+\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n+\tstruct otx2_mbox *mbox = dev->mbox;\n+\tstruct nix_aq_enq_rsp *rsp;\n+\tstruct nix_aq_enq_req *aq;\n+\tuint32_t i;\n+\tint rc;\n+\n+\tfor (i = 0; i < eth_dev->data->nb_rx_queues; i++) {\n+\t\taq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);\n+\t\taq->qidx = i;\n+\t\taq->ctype = NIX_AQ_CTYPE_RQ;\n+\t\taq->op = NIX_AQ_INSTOP_READ;\n+\t\trc = otx2_mbox_process_msg(mbox, (void *)&rsp);\n+\t\tif (rc) {\n+\t\t\totx2_err(\"Failed to read rq context\");\n+\t\t\treturn;\n+\t\t}\n+\t\taq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);\n+\t\taq->qidx = i;\n+\t\taq->ctype = NIX_AQ_CTYPE_RQ;\n+\t\taq->op = NIX_AQ_INSTOP_WRITE;\n+\t\totx2_mbox_memcpy(&aq->rq, &rsp->rq, sizeof(rsp->rq));\n+\t\totx2_mbox_memset(&aq->rq_mask, 0, sizeof(aq->rq_mask));\n+\t\taq->rq.octs = 0;\n+\t\taq->rq.pkts = 0;\n+\t\taq->rq.drop_octs = 0;\n+\t\taq->rq.drop_pkts = 0;\n+\t\taq->rq.re_pkts = 0;\n+\n+\t\taq->rq_mask.octs = ~(aq->rq_mask.octs);\n+\t\taq->rq_mask.pkts = ~(aq->rq_mask.pkts);\n+\t\taq->rq_mask.drop_octs = ~(aq->rq_mask.drop_octs);\n+\t\taq->rq_mask.drop_pkts = ~(aq->rq_mask.drop_pkts);\n+\t\taq->rq_mask.re_pkts = ~(aq->rq_mask.re_pkts);\n+\t\trc = otx2_mbox_process(mbox);\n+\t\tif (rc) {\n+\t\t\totx2_err(\"Failed to write rq context\");\n+\t\t\treturn;\n+\t\t}\n+\t}\n+\n+\tfor (i = 0; i < eth_dev->data->nb_tx_queues; i++) {\n+\t\taq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);\n+\t\taq->qidx = i;\n+\t\taq->ctype = NIX_AQ_CTYPE_SQ;\n+\t\taq->op = NIX_AQ_INSTOP_READ;\n+\t\trc = otx2_mbox_process_msg(mbox, (void *)&rsp);\n+\t\tif (rc) {\n+\t\t\totx2_err(\"Failed to read sq context\");\n+\t\t\treturn;\n+\t\t}\n+\t\taq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);\n+\t\taq->qidx = i;\n+\t\taq->ctype = NIX_AQ_CTYPE_SQ;\n+\t\taq->op = NIX_AQ_INSTOP_WRITE;\n+\t\totx2_mbox_memcpy(&aq->sq, &rsp->sq, sizeof(rsp->sq));\n+\t\totx2_mbox_memset(&aq->sq_mask, 0, sizeof(aq->sq_mask));\n+\t\taq->sq.octs = 0;\n+\t\taq->sq.pkts = 0;\n+\t\taq->sq.drop_octs = 0;\n+\t\taq->sq.drop_pkts = 0;\n+\n+\t\taq->sq_mask.octs = ~(aq->sq_mask.octs);\n+\t\taq->sq_mask.pkts = ~(aq->sq_mask.pkts);\n+\t\taq->sq_mask.drop_octs = ~(aq->sq_mask.drop_octs);\n+\t\taq->sq_mask.drop_pkts = ~(aq->sq_mask.drop_pkts);\n+\t\trc = otx2_mbox_process(mbox);\n+\t\tif (rc) {\n+\t\t\totx2_err(\"Failed to write sq context\");\n+\t\t\treturn;\n+\t\t}\n+\t}\n+}\n+\n+void\n+otx2_nix_xstats_reset(struct rte_eth_dev *eth_dev)\n+{\n+\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n+\tstruct otx2_mbox *mbox = dev->mbox;\n+\n+\totx2_mbox_alloc_msg_nix_stats_rst(mbox);\n+\totx2_mbox_process(mbox);\n+\n+\t/* Reset queue stats */\n+\tnix_queue_stats_reset(eth_dev);\n+}\n", "prefixes": [ "v1", "13/58" ] }