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GET /api/patches/54068/?format=api
HTTP 200 OK
Allow: GET, PUT, PATCH, HEAD, OPTIONS
Content-Type: application/json
Vary: Accept

{
    "id": 54068,
    "url": "http://patches.dpdk.org/api/patches/54068/?format=api",
    "web_url": "http://patches.dpdk.org/project/dpdk/patch/20190602152434.23996-13-jerinj@marvell.com/",
    "project": {
        "id": 1,
        "url": "http://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<20190602152434.23996-13-jerinj@marvell.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/20190602152434.23996-13-jerinj@marvell.com",
    "date": "2019-06-02T15:23:48",
    "name": "[v1,12/58] net/octeontx2: add basic stats operation",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": true,
    "hash": "da45c5a332ec102f00a8604022f6d6955254ad92",
    "submitter": {
        "id": 1188,
        "url": "http://patches.dpdk.org/api/people/1188/?format=api",
        "name": "Jerin Jacob Kollanukkaran",
        "email": "jerinj@marvell.com"
    },
    "delegate": {
        "id": 319,
        "url": "http://patches.dpdk.org/api/users/319/?format=api",
        "username": "fyigit",
        "first_name": "Ferruh",
        "last_name": "Yigit",
        "email": "ferruh.yigit@amd.com"
    },
    "mbox": "http://patches.dpdk.org/project/dpdk/patch/20190602152434.23996-13-jerinj@marvell.com/mbox/",
    "series": [
        {
            "id": 4848,
            "url": "http://patches.dpdk.org/api/series/4848/?format=api",
            "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=4848",
            "date": "2019-06-02T15:23:36",
            "name": "OCTEON TX2 Ethdev driver",
            "version": 1,
            "mbox": "http://patches.dpdk.org/series/4848/mbox/"
        }
    ],
    "comments": "http://patches.dpdk.org/api/patches/54068/comments/",
    "check": "fail",
    "checks": "http://patches.dpdk.org/api/patches/54068/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@dpdk.org",
        "Delivered-To": "patchwork@dpdk.org",
        "Received": [
            "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 69FA71B9B5;\n\tSun,  2 Jun 2019 17:25:16 +0200 (CEST)",
            "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n\t[67.231.156.173]) by dpdk.org (Postfix) with ESMTP id CCE1E1B99F\n\tfor <dev@dpdk.org>; Sun,  2 Jun 2019 17:25:14 +0200 (CEST)",
            "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n\tby mx0b-0016f401.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id\n\tx52FK4Ye020248; Sun, 2 Jun 2019 08:25:14 -0700",
            "from sc-exch02.marvell.com ([199.233.58.182])\n\tby mx0b-0016f401.pphosted.com with ESMTP id 2survk492h-1\n\t(version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); \n\tSun, 02 Jun 2019 08:25:14 -0700",
            "from SC-EXCH03.marvell.com (10.93.176.83) by SC-EXCH02.marvell.com\n\t(10.93.176.82) with Microsoft SMTP Server (TLS) id 15.0.1367.3;\n\tSun, 2 Jun 2019 08:25:12 -0700",
            "from maili.marvell.com (10.93.176.43) by SC-EXCH03.marvell.com\n\t(10.93.176.83) with Microsoft SMTP Server id 15.0.1367.3 via Frontend\n\tTransport; Sun, 2 Jun 2019 08:25:12 -0700",
            "from jerin-lab.marvell.com (jerin-lab.marvell.com [10.28.34.14])\n\tby maili.marvell.com (Postfix) with ESMTP id D44253F703F;\n\tSun,  2 Jun 2019 08:25:10 -0700 (PDT)"
        ],
        "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n\th=from : to : cc :\n\tsubject : date : message-id : in-reply-to : references : mime-version\n\t: content-transfer-encoding : content-type; s=pfpt0818;\n\tbh=VyuQV82IJWEVbIZAviCUHe8cqwSI1TP35/8qu0BXSgE=;\n\tb=AbRWf4i4jCK2P4MWgVHWlBoOaLsOjnagwVaqm9rKI/cVx8NPFqEPJBnahbus7F1MM2IA\n\tD6hlLF2JVFRvBuLNw4BEEWvUkb0J24SQyyyw6qm4SkWhpwQBZwpTmxOZMugImk7JQd9U\n\t77T+3CINn9Tnp+2kxRu8ADS/2ds9/0KCVKIrFvqtxWy4a7LW8vR/yGk9nNoGr2dOaEef\n\t/Y+bHEhtZMO8g7VmrlDIEEBcy43gnHj1fiQJJYBPn3jNk3Mw7zKUIGDEEfuXk4tOngOU\n\tIWk+R0E6NbBA6rjvB++Ny2XCVKjLumsm1Vgm7BcirdndsUNEV/YGRHMHfjJnsXf0Ut86\n\tyg== ",
        "From": "<jerinj@marvell.com>",
        "To": "<dev@dpdk.org>, John McNamara <john.mcnamara@intel.com>, Marko Kovacevic\n\t<marko.kovacevic@intel.com>, Jerin Jacob <jerinj@marvell.com>, \"Nithin\n\tDabilpuram\" <ndabilpuram@marvell.com>, Kiran Kumar K\n\t<kirankumark@marvell.com>",
        "CC": "<ferruh.yigit@intel.com>, Vamsi Attunuru <vattunuru@marvell.com>",
        "Date": "Sun, 2 Jun 2019 20:53:48 +0530",
        "Message-ID": "<20190602152434.23996-13-jerinj@marvell.com>",
        "X-Mailer": "git-send-email 2.21.0",
        "In-Reply-To": "<20190602152434.23996-1-jerinj@marvell.com>",
        "References": "<20190602152434.23996-1-jerinj@marvell.com>",
        "MIME-Version": "1.0",
        "Content-Transfer-Encoding": "8bit",
        "Content-Type": "text/plain",
        "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:, ,\n\tdefinitions=2019-06-02_09:, , signatures=0",
        "Subject": "[dpdk-dev] [PATCH v1 12/58] net/octeontx2: add basic stats operation",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.15",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "From: Kiran Kumar K <kirankumark@marvell.com>\n\nAdd basic stat operation and updated the feature list.\n\nSigned-off-by: Kiran Kumar K <kirankumark@marvell.com>\nSigned-off-by: Vamsi Attunuru <vattunuru@marvell.com>\n---\n doc/guides/nics/features/octeontx2.ini     |   2 +\n doc/guides/nics/features/octeontx2_vec.ini |   2 +\n doc/guides/nics/features/octeontx2_vf.ini  |   2 +\n drivers/net/octeontx2/Makefile             |   1 +\n drivers/net/octeontx2/meson.build          |   1 +\n drivers/net/octeontx2/otx2_ethdev.c        |   3 +\n drivers/net/octeontx2/otx2_ethdev.h        |  17 +++\n drivers/net/octeontx2/otx2_stats.c         | 117 +++++++++++++++++++++\n 8 files changed, 145 insertions(+)\n create mode 100644 drivers/net/octeontx2/otx2_stats.c",
    "diff": "diff --git a/doc/guides/nics/features/octeontx2.ini b/doc/guides/nics/features/octeontx2.ini\nindex 60009ab6d..72336ae15 100644\n--- a/doc/guides/nics/features/octeontx2.ini\n+++ b/doc/guides/nics/features/octeontx2.ini\n@@ -12,4 +12,6 @@ SR-IOV               = Y\n Multiprocess aware   = Y\n Link status          = Y\n Link status event    = Y\n+Basic stats          = Y\n+Stats per queue      = Y\n Registers dump       = Y\ndiff --git a/doc/guides/nics/features/octeontx2_vec.ini b/doc/guides/nics/features/octeontx2_vec.ini\nindex 3a859edd1..0f3850188 100644\n--- a/doc/guides/nics/features/octeontx2_vec.ini\n+++ b/doc/guides/nics/features/octeontx2_vec.ini\n@@ -12,4 +12,6 @@ SR-IOV               = Y\n Multiprocess aware   = Y\n Link status          = Y\n Link status event    = Y\n+Basic stats          = Y\n+Stats per queue      = Y\n Registers dump       = Y\ndiff --git a/doc/guides/nics/features/octeontx2_vf.ini b/doc/guides/nics/features/octeontx2_vf.ini\nindex e1cbd18b1..8bc72c4fb 100644\n--- a/doc/guides/nics/features/octeontx2_vf.ini\n+++ b/doc/guides/nics/features/octeontx2_vf.ini\n@@ -11,4 +11,6 @@ Lock-free Tx queue   = Y\n Multiprocess aware   = Y\n Link status          = Y\n Link status event    = Y\n+Basic stats          = Y\n+Stats per queue      = Y\n Registers dump       = Y\ndiff --git a/drivers/net/octeontx2/Makefile b/drivers/net/octeontx2/Makefile\nindex aa428fe6a..dcd692b7b 100644\n--- a/drivers/net/octeontx2/Makefile\n+++ b/drivers/net/octeontx2/Makefile\n@@ -32,6 +32,7 @@ LIBABIVER := 1\n SRCS-$(CONFIG_RTE_LIBRTE_OCTEONTX2_PMD) += \\\n \totx2_mac.c\t\\\n \totx2_link.c\t\\\n+\totx2_stats.c\t\\\n \totx2_ethdev.c\t\\\n \totx2_ethdev_irq.c \\\n \totx2_ethdev_ops.c \\\ndiff --git a/drivers/net/octeontx2/meson.build b/drivers/net/octeontx2/meson.build\nindex 117d038ab..384237104 100644\n--- a/drivers/net/octeontx2/meson.build\n+++ b/drivers/net/octeontx2/meson.build\n@@ -5,6 +5,7 @@\n sources = files(\n \t\t'otx2_mac.c',\n \t\t'otx2_link.c',\n+\t\t'otx2_stats.c',\n \t\t'otx2_ethdev.c',\n \t\t'otx2_ethdev_irq.c',\n \t\t'otx2_ethdev_ops.c',\ndiff --git a/drivers/net/octeontx2/otx2_ethdev.c b/drivers/net/octeontx2/otx2_ethdev.c\nindex cb4f6ebb9..5787029d9 100644\n--- a/drivers/net/octeontx2/otx2_ethdev.c\n+++ b/drivers/net/octeontx2/otx2_ethdev.c\n@@ -234,7 +234,10 @@ static const struct eth_dev_ops otx2_eth_dev_ops = {\n \t.dev_infos_get            = otx2_nix_info_get,\n \t.dev_configure            = otx2_nix_configure,\n \t.link_update              = otx2_nix_link_update,\n+\t.stats_get                = otx2_nix_dev_stats_get,\n+\t.stats_reset              = otx2_nix_dev_stats_reset,\n \t.get_reg                  = otx2_nix_dev_get_reg,\n+\t.queue_stats_mapping_set  = otx2_nix_queue_stats_mapping,\n };\n \n static inline int\ndiff --git a/drivers/net/octeontx2/otx2_ethdev.h b/drivers/net/octeontx2/otx2_ethdev.h\nindex 8a099817d..c9366a9ed 100644\n--- a/drivers/net/octeontx2/otx2_ethdev.h\n+++ b/drivers/net/octeontx2/otx2_ethdev.h\n@@ -57,6 +57,12 @@\n #define NIX_TX_NB_SEG_MAX\t\t9\n #endif\n \n+#define CQ_OP_STAT_OP_ERR\t63\n+#define CQ_OP_STAT_CQ_ERR\t46\n+\n+#define OP_ERR\t\t\tBIT_ULL(CQ_OP_STAT_OP_ERR)\n+#define CQ_ERR\t\t\tBIT_ULL(CQ_OP_STAT_CQ_ERR)\n+\n #define NIX_RSS_OFFLOAD\t\t(ETH_RSS_PORT | ETH_RSS_IP | ETH_RSS_UDP |\\\n \t\t\t\t ETH_RSS_TCP | ETH_RSS_SCTP | \\\n \t\t\t\t ETH_RSS_TUNNEL | ETH_RSS_L2_PAYLOAD)\n@@ -135,6 +141,8 @@ struct otx2_eth_dev {\n \tuint64_t tx_offload_capa;\n \tstruct otx2_qint qints_mem[RTE_MAX_QUEUES_PER_PORT];\n \tstruct otx2_rss_info rss_info;\n+\tuint32_t txmap[RTE_ETHDEV_QUEUE_STAT_CNTRS];\n+\tuint32_t rxmap[RTE_ETHDEV_QUEUE_STAT_CNTRS];\n \tstruct otx2_npc_flow_info npc_flow;\n \tstruct rte_eth_dev *eth_dev;\n } __rte_cache_aligned;\n@@ -168,6 +176,15 @@ int otx2_nix_dev_get_reg(struct rte_eth_dev *eth_dev,\n int otx2_nix_queues_ctx_dump(struct rte_eth_dev *eth_dev);\n void otx2_nix_cqe_dump(const struct nix_cqe_hdr_s *cq);\n \n+/* Stats */\n+int otx2_nix_dev_stats_get(struct rte_eth_dev *eth_dev,\n+\t\t\t   struct rte_eth_stats *stats);\n+void otx2_nix_dev_stats_reset(struct rte_eth_dev *eth_dev);\n+\n+int otx2_nix_queue_stats_mapping(struct rte_eth_dev *dev,\n+\t\t\t\t uint16_t queue_id, uint8_t stat_idx,\n+\t\t\t\t uint8_t is_rx);\n+\n /* CGX */\n int otx2_cgx_rxtx_start(struct otx2_eth_dev *dev);\n int otx2_cgx_rxtx_stop(struct otx2_eth_dev *dev);\ndiff --git a/drivers/net/octeontx2/otx2_stats.c b/drivers/net/octeontx2/otx2_stats.c\nnew file mode 100644\nindex 000000000..ade0f6ad6\n--- /dev/null\n+++ b/drivers/net/octeontx2/otx2_stats.c\n@@ -0,0 +1,117 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2019 Marvell International Ltd.\n+ */\n+\n+#include <inttypes.h>\n+\n+#include \"otx2_ethdev.h\"\n+\n+int\n+otx2_nix_dev_stats_get(struct rte_eth_dev *eth_dev,\n+\t\t       struct rte_eth_stats *stats)\n+{\n+\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n+\tuint64_t reg, val;\n+\tuint32_t qidx, i;\n+\tint64_t *addr;\n+\n+\tstats->opackets = otx2_read64(dev->base +\n+\t\t\tNIX_LF_TX_STATX(NIX_STAT_LF_TX_TX_UCAST));\n+\tstats->opackets += otx2_read64(dev->base +\n+\t\t\tNIX_LF_TX_STATX(NIX_STAT_LF_TX_TX_MCAST));\n+\tstats->opackets += otx2_read64(dev->base +\n+\t\t\tNIX_LF_TX_STATX(NIX_STAT_LF_TX_TX_BCAST));\n+\tstats->oerrors = otx2_read64(dev->base +\n+\t\t\tNIX_LF_TX_STATX(NIX_STAT_LF_TX_TX_DROP));\n+\tstats->obytes = otx2_read64(dev->base +\n+\t\t\tNIX_LF_TX_STATX(NIX_STAT_LF_TX_TX_OCTS));\n+\n+\tstats->ipackets = otx2_read64(dev->base +\n+\t\t\tNIX_LF_RX_STATX(NIX_STAT_LF_RX_RX_UCAST));\n+\tstats->ipackets += otx2_read64(dev->base +\n+\t\t\tNIX_LF_RX_STATX(NIX_STAT_LF_RX_RX_MCAST));\n+\tstats->ipackets += otx2_read64(dev->base +\n+\t\t\tNIX_LF_RX_STATX(NIX_STAT_LF_RX_RX_BCAST));\n+\tstats->imissed = otx2_read64(dev->base +\n+\t\t\tNIX_LF_RX_STATX(NIX_STAT_LF_RX_RX_DROP));\n+\tstats->ibytes = otx2_read64(dev->base +\n+\t\t\tNIX_LF_RX_STATX(NIX_STAT_LF_RX_RX_OCTS));\n+\tstats->ierrors = otx2_read64(dev->base +\n+\t\t\tNIX_LF_RX_STATX(NIX_STAT_LF_RX_RX_ERR));\n+\n+\tfor (i = 0; i < RTE_ETHDEV_QUEUE_STAT_CNTRS; i++) {\n+\t\tif (dev->txmap[i] & (1 << 31)) {\n+\t\t\tqidx = dev->txmap[i] & 0xFFFF;\n+\t\t\treg = (((uint64_t)qidx) << 32);\n+\n+\t\t\taddr = (int64_t *)(dev->base + NIX_LF_SQ_OP_PKTS);\n+\t\t\tval = otx2_atomic64_add_nosync(reg, addr);\n+\t\t\tif (val & OP_ERR)\n+\t\t\t\tval = 0;\n+\t\t\tstats->q_ipackets[i] = val;\n+\n+\t\t\taddr = (int64_t *)(dev->base + NIX_LF_SQ_OP_OCTS);\n+\t\t\tval = otx2_atomic64_add_nosync(reg, addr);\n+\t\t\tif (val & OP_ERR)\n+\t\t\t\tval = 0;\n+\t\t\tstats->q_ibytes[i] = val;\n+\n+\t\t\taddr = (int64_t *)(dev->base + NIX_LF_SQ_OP_DROP_PKTS);\n+\t\t\tval = otx2_atomic64_add_nosync(reg, addr);\n+\t\t\tif (val & OP_ERR)\n+\t\t\t\tval = 0;\n+\t\t\tstats->q_errors[i] = val;\n+\t\t}\n+\t}\n+\n+\tfor (i = 0; i < RTE_ETHDEV_QUEUE_STAT_CNTRS; i++) {\n+\t\tif (dev->rxmap[i] & (1 << 31)) {\n+\t\t\tqidx = dev->rxmap[i] & 0xFFFF;\n+\t\t\treg = (((uint64_t)qidx) << 32);\n+\n+\t\t\taddr = (int64_t *)(dev->base + NIX_LF_RQ_OP_PKTS);\n+\t\t\tval = otx2_atomic64_add_nosync(reg, addr);\n+\t\t\tif (val & OP_ERR)\n+\t\t\t\tval = 0;\n+\t\t\tstats->q_opackets[i] = val;\n+\n+\t\t\taddr = (int64_t *)(dev->base + NIX_LF_RQ_OP_OCTS);\n+\t\t\tval = otx2_atomic64_add_nosync(reg, addr);\n+\t\t\tif (val & OP_ERR)\n+\t\t\t\tval = 0;\n+\t\t\tstats->q_obytes[i] = val;\n+\n+\t\t\taddr = (int64_t *)(dev->base + NIX_LF_RQ_OP_DROP_PKTS);\n+\t\t\tval = otx2_atomic64_add_nosync(reg, addr);\n+\t\t\tif (val & OP_ERR)\n+\t\t\t\tval = 0;\n+\t\t\tstats->q_errors[i] += val;\n+\t\t}\n+\t}\n+\n+\treturn 0;\n+}\n+\n+void\n+otx2_nix_dev_stats_reset(struct rte_eth_dev *eth_dev)\n+{\n+\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n+\tstruct otx2_mbox *mbox = dev->mbox;\n+\n+\totx2_mbox_alloc_msg_nix_stats_rst(mbox);\n+\totx2_mbox_process(mbox);\n+}\n+\n+int\n+otx2_nix_queue_stats_mapping(struct rte_eth_dev *eth_dev, uint16_t queue_id,\n+\t\t\t     uint8_t stat_idx, uint8_t is_rx)\n+{\n+\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n+\n+\tif (is_rx)\n+\t\tdev->rxmap[stat_idx] = ((1 << 31) | queue_id);\n+\telse\n+\t\tdev->txmap[stat_idx] = ((1 << 31) | queue_id);\n+\n+\treturn 0;\n+}\n",
    "prefixes": [
        "v1",
        "12/58"
    ]
}