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GET /api/patches/54066/?format=api
{ "id": 54066, "url": "http://patches.dpdk.org/api/patches/54066/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20190602152434.23996-11-jerinj@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20190602152434.23996-11-jerinj@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20190602152434.23996-11-jerinj@marvell.com", "date": "2019-06-02T15:23:46", "name": "[v1,10/58] net/octeontx2: add register dump support", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "ed2559714adf3edad3c8a71c10f5c93144daa5a2", "submitter": { "id": 1188, "url": "http://patches.dpdk.org/api/people/1188/?format=api", "name": "Jerin Jacob Kollanukkaran", "email": "jerinj@marvell.com" }, "delegate": { "id": 319, "url": "http://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20190602152434.23996-11-jerinj@marvell.com/mbox/", "series": [ { "id": 4848, "url": "http://patches.dpdk.org/api/series/4848/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=4848", "date": "2019-06-02T15:23:36", "name": "OCTEON TX2 Ethdev driver", "version": 1, "mbox": "http://patches.dpdk.org/series/4848/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/54066/comments/", "check": "fail", "checks": "http://patches.dpdk.org/api/patches/54066/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 5AA141B995;\n\tSun, 2 Jun 2019 17:25:10 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n\t[67.231.156.173]) by dpdk.org (Postfix) with ESMTP id 8139B1B9A8\n\tfor <dev@dpdk.org>; Sun, 2 Jun 2019 17:25:08 +0200 (CEST)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n\tby mx0b-0016f401.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id\n\tx52FLOCR021032; Sun, 2 Jun 2019 08:25:08 -0700", "from sc-exch03.marvell.com ([199.233.58.183])\n\tby mx0b-0016f401.pphosted.com with ESMTP id 2survk492a-1\n\t(version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); \n\tSun, 02 Jun 2019 08:25:07 -0700", "from SC-EXCH03.marvell.com (10.93.176.83) by SC-EXCH03.marvell.com\n\t(10.93.176.83) with Microsoft SMTP Server (TLS) id 15.0.1367.3;\n\tSun, 2 Jun 2019 08:25:06 -0700", "from maili.marvell.com (10.93.176.43) by SC-EXCH03.marvell.com\n\t(10.93.176.83) with Microsoft SMTP Server id 15.0.1367.3 via Frontend\n\tTransport; Sun, 2 Jun 2019 08:25:06 -0700", "from jerin-lab.marvell.com (jerin-lab.marvell.com [10.28.34.14])\n\tby maili.marvell.com (Postfix) with ESMTP id 940843F7041;\n\tSun, 2 Jun 2019 08:25:04 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n\th=from : to : cc :\n\tsubject : date : message-id : in-reply-to : references : mime-version\n\t: content-transfer-encoding : content-type; s=pfpt0818;\n\tbh=9WSrop22NU4mZwCEoXpwqs5lsvRAjGf/hQgDMBnnrsY=;\n\tb=kHCasG39w9d9kRSeTz0bm9G1T4E1a7LKDywY4turLHvtD4UugEeIXROT+3wj1XXKFpcb\n\tgNwg9l3XsOHkJfz3DQC9bN2S9o0wdBaa/ekXX8HapOlrZpmn/eEzDey3sco9sATQ1hGY\n\tu43HJSYJ5ccvN3qa/sXsVaneIqjde8m14Y3PJiopACCh7cIWRiqjSculXEAjzo8sv5aY\n\tK/t224tec7rEs4KEsh/o/KdHG8nnp1lm0Za/VwF2lGEO0SdCs+Aek35TMikAJSVX/3lc\n\tBArFOEWKnDfu+gbOWfrm8mbdfPJR1/Gfmb15hXdmsgVI82wUvN3NR2CRyAnVw+3wybS1\n\tJA== ", "From": "<jerinj@marvell.com>", "To": "<dev@dpdk.org>, John McNamara <john.mcnamara@intel.com>, Marko Kovacevic\n\t<marko.kovacevic@intel.com>, Jerin Jacob <jerinj@marvell.com>, \"Nithin\n\tDabilpuram\" <ndabilpuram@marvell.com>, Kiran Kumar K\n\t<kirankumark@marvell.com>", "CC": "<ferruh.yigit@intel.com>", "Date": "Sun, 2 Jun 2019 20:53:46 +0530", "Message-ID": "<20190602152434.23996-11-jerinj@marvell.com>", "X-Mailer": "git-send-email 2.21.0", "In-Reply-To": "<20190602152434.23996-1-jerinj@marvell.com>", "References": "<20190602152434.23996-1-jerinj@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:, ,\n\tdefinitions=2019-06-02_09:, , signatures=0", "Subject": "[dpdk-dev] [PATCH v1 10/58] net/octeontx2: add register dump support", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Kiran Kumar K <kirankumark@marvell.com>\n\nAdd register dump support and mark Registers dump in features.\n\nSigned-off-by: Kiran Kumar K <kirankumark@marvell.com>\nSigned-off-by: Jerin Jacob <jerinj@marvell.com>\n---\n doc/guides/nics/features/octeontx2.ini | 1 +\n doc/guides/nics/features/octeontx2_vec.ini | 1 +\n doc/guides/nics/features/octeontx2_vf.ini | 1 +\n drivers/net/octeontx2/otx2_ethdev.c | 1 +\n drivers/net/octeontx2/otx2_ethdev.h | 3 +\n drivers/net/octeontx2/otx2_ethdev_debug.c | 228 +++++++++++++++++++++\n drivers/net/octeontx2/otx2_ethdev_irq.c | 6 +\n 7 files changed, 241 insertions(+)", "diff": "diff --git a/doc/guides/nics/features/octeontx2.ini b/doc/guides/nics/features/octeontx2.ini\nindex 1f0148669..ce3067596 100644\n--- a/doc/guides/nics/features/octeontx2.ini\n+++ b/doc/guides/nics/features/octeontx2.ini\n@@ -10,3 +10,4 @@ ARMv8 = Y\n Lock-free Tx queue = Y\n SR-IOV = Y\n Multiprocess aware = Y\n+Registers dump = Y\ndiff --git a/doc/guides/nics/features/octeontx2_vec.ini b/doc/guides/nics/features/octeontx2_vec.ini\nindex 2b0644ee5..b2be52ccb 100644\n--- a/doc/guides/nics/features/octeontx2_vec.ini\n+++ b/doc/guides/nics/features/octeontx2_vec.ini\n@@ -10,3 +10,4 @@ ARMv8 = Y\n Lock-free Tx queue = Y\n SR-IOV = Y\n Multiprocess aware = Y\n+Registers dump = Y\ndiff --git a/doc/guides/nics/features/octeontx2_vf.ini b/doc/guides/nics/features/octeontx2_vf.ini\nindex 80f0d5c95..76b0c3c10 100644\n--- a/doc/guides/nics/features/octeontx2_vf.ini\n+++ b/doc/guides/nics/features/octeontx2_vf.ini\n@@ -9,3 +9,4 @@ Linux VFIO = Y\n ARMv8 = Y\n Lock-free Tx queue = Y\n Multiprocess aware = Y\n+Registers dump = Y\ndiff --git a/drivers/net/octeontx2/otx2_ethdev.c b/drivers/net/octeontx2/otx2_ethdev.c\nindex 045855c2e..48d5a15d6 100644\n--- a/drivers/net/octeontx2/otx2_ethdev.c\n+++ b/drivers/net/octeontx2/otx2_ethdev.c\n@@ -229,6 +229,7 @@ otx2_nix_configure(struct rte_eth_dev *eth_dev)\n static const struct eth_dev_ops otx2_eth_dev_ops = {\n \t.dev_infos_get = otx2_nix_info_get,\n \t.dev_configure = otx2_nix_configure,\n+\t.get_reg = otx2_nix_dev_get_reg,\n };\n \n static inline int\ndiff --git a/drivers/net/octeontx2/otx2_ethdev.h b/drivers/net/octeontx2/otx2_ethdev.h\nindex ff14a0129..c01fe0211 100644\n--- a/drivers/net/octeontx2/otx2_ethdev.h\n+++ b/drivers/net/octeontx2/otx2_ethdev.h\n@@ -154,6 +154,9 @@ void otx2_nix_unregister_irqs(struct rte_eth_dev *eth_dev);\n void oxt2_nix_unregister_queue_irqs(struct rte_eth_dev *eth_dev);\n \n /* Debug */\n+int otx2_nix_reg_dump(struct otx2_eth_dev *dev, uint64_t *data);\n+int otx2_nix_dev_get_reg(struct rte_eth_dev *eth_dev,\n+\t\t\t struct rte_dev_reg_info *regs);\n int otx2_nix_queues_ctx_dump(struct rte_eth_dev *eth_dev);\n void otx2_nix_cqe_dump(const struct nix_cqe_hdr_s *cq);\n \ndiff --git a/drivers/net/octeontx2/otx2_ethdev_debug.c b/drivers/net/octeontx2/otx2_ethdev_debug.c\nindex 39cda7637..9f06e5505 100644\n--- a/drivers/net/octeontx2/otx2_ethdev_debug.c\n+++ b/drivers/net/octeontx2/otx2_ethdev_debug.c\n@@ -5,6 +5,234 @@\n #include \"otx2_ethdev.h\"\n \n #define nix_dump(fmt, ...) fprintf(stderr, fmt \"\\n\", ##__VA_ARGS__)\n+#define NIX_REG_INFO(reg) {reg, #reg}\n+\n+struct nix_lf_reg_info {\n+\tuint32_t offset;\n+\tconst char *name;\n+};\n+\n+static const struct\n+nix_lf_reg_info nix_lf_reg[] = {\n+\tNIX_REG_INFO(NIX_LF_RX_SECRETX(0)),\n+\tNIX_REG_INFO(NIX_LF_RX_SECRETX(1)),\n+\tNIX_REG_INFO(NIX_LF_RX_SECRETX(2)),\n+\tNIX_REG_INFO(NIX_LF_RX_SECRETX(3)),\n+\tNIX_REG_INFO(NIX_LF_RX_SECRETX(4)),\n+\tNIX_REG_INFO(NIX_LF_RX_SECRETX(5)),\n+\tNIX_REG_INFO(NIX_LF_CFG),\n+\tNIX_REG_INFO(NIX_LF_GINT),\n+\tNIX_REG_INFO(NIX_LF_GINT_W1S),\n+\tNIX_REG_INFO(NIX_LF_GINT_ENA_W1C),\n+\tNIX_REG_INFO(NIX_LF_GINT_ENA_W1S),\n+\tNIX_REG_INFO(NIX_LF_ERR_INT),\n+\tNIX_REG_INFO(NIX_LF_ERR_INT_W1S),\n+\tNIX_REG_INFO(NIX_LF_ERR_INT_ENA_W1C),\n+\tNIX_REG_INFO(NIX_LF_ERR_INT_ENA_W1S),\n+\tNIX_REG_INFO(NIX_LF_RAS),\n+\tNIX_REG_INFO(NIX_LF_RAS_W1S),\n+\tNIX_REG_INFO(NIX_LF_RAS_ENA_W1C),\n+\tNIX_REG_INFO(NIX_LF_RAS_ENA_W1S),\n+\tNIX_REG_INFO(NIX_LF_SQ_OP_ERR_DBG),\n+\tNIX_REG_INFO(NIX_LF_MNQ_ERR_DBG),\n+\tNIX_REG_INFO(NIX_LF_SEND_ERR_DBG),\n+};\n+\n+static int\n+nix_lf_get_reg_count(struct otx2_eth_dev *dev)\n+{\n+\tint reg_count = 0;\n+\n+\treg_count = RTE_DIM(nix_lf_reg);\n+\t/* NIX_LF_TX_STATX */\n+\treg_count += dev->lf_tx_stats;\n+\t/* NIX_LF_RX_STATX */\n+\treg_count += dev->lf_rx_stats;\n+\t/* NIX_LF_QINTX_CNT*/\n+\treg_count += dev->qints;\n+\t/* NIX_LF_QINTX_INT */\n+\treg_count += dev->qints;\n+\t/* NIX_LF_QINTX_ENA_W1S */\n+\treg_count += dev->qints;\n+\t/* NIX_LF_QINTX_ENA_W1C */\n+\treg_count += dev->qints;\n+\t/* NIX_LF_CINTX_CNT */\n+\treg_count += dev->cints;\n+\t/* NIX_LF_CINTX_WAIT */\n+\treg_count += dev->cints;\n+\t/* NIX_LF_CINTX_INT */\n+\treg_count += dev->cints;\n+\t/* NIX_LF_CINTX_INT_W1S */\n+\treg_count += dev->cints;\n+\t/* NIX_LF_CINTX_ENA_W1S */\n+\treg_count += dev->cints;\n+\t/* NIX_LF_CINTX_ENA_W1C */\n+\treg_count += dev->cints;\n+\n+\treturn reg_count;\n+}\n+\n+int\n+otx2_nix_reg_dump(struct otx2_eth_dev *dev, uint64_t *data)\n+{\n+\tuintptr_t nix_lf_base = dev->base;\n+\tbool dump_stdout;\n+\tuint64_t reg;\n+\tuint32_t i;\n+\n+\tdump_stdout = data ? 0 : 1;\n+\n+\tfor (i = 0; i < RTE_DIM(nix_lf_reg); i++) {\n+\t\treg = otx2_read64(nix_lf_base + nix_lf_reg[i].offset);\n+\t\tif (dump_stdout && reg)\n+\t\t\tnix_dump(\"%32s = 0x%\" PRIx64,\n+\t\t\t\t nix_lf_reg[i].name, reg);\n+\t\tif (data)\n+\t\t\t*data++ = reg;\n+\t}\n+\n+\t/* NIX_LF_TX_STATX */\n+\tfor (i = 0; i < dev->lf_tx_stats; i++) {\n+\t\treg = otx2_read64(nix_lf_base + NIX_LF_TX_STATX(i));\n+\t\tif (dump_stdout && reg)\n+\t\t\tnix_dump(\"%32s_%d = 0x%\" PRIx64,\n+\t\t\t\t \"NIX_LF_TX_STATX\", i, reg);\n+\t\tif (data)\n+\t\t\t*data++ = reg;\n+\t}\n+\n+\t/* NIX_LF_RX_STATX */\n+\tfor (i = 0; i < dev->lf_rx_stats; i++) {\n+\t\treg = otx2_read64(nix_lf_base + NIX_LF_RX_STATX(i));\n+\t\tif (dump_stdout && reg)\n+\t\t\tnix_dump(\"%32s_%d = 0x%\" PRIx64,\n+\t\t\t\t \"NIX_LF_RX_STATX\", i, reg);\n+\t\tif (data)\n+\t\t\t*data++ = reg;\n+\t}\n+\n+\t/* NIX_LF_QINTX_CNT*/\n+\tfor (i = 0; i < dev->qints; i++) {\n+\t\treg = otx2_read64(nix_lf_base + NIX_LF_QINTX_CNT(i));\n+\t\tif (dump_stdout && reg)\n+\t\t\tnix_dump(\"%32s_%d = 0x%\" PRIx64,\n+\t\t\t\t \"NIX_LF_QINTX_CNT\", i, reg);\n+\t\tif (data)\n+\t\t\t*data++ = reg;\n+\t}\n+\n+\t/* NIX_LF_QINTX_INT */\n+\tfor (i = 0; i < dev->qints; i++) {\n+\t\treg = otx2_read64(nix_lf_base + NIX_LF_QINTX_INT(i));\n+\t\tif (dump_stdout && reg)\n+\t\t\tnix_dump(\"%32s_%d = 0x%\" PRIx64,\n+\t\t\t\t \"NIX_LF_QINTX_INT\", i, reg);\n+\t\tif (data)\n+\t\t\t*data++ = reg;\n+\t}\n+\n+\t/* NIX_LF_QINTX_ENA_W1S */\n+\tfor (i = 0; i < dev->qints; i++) {\n+\t\treg = otx2_read64(nix_lf_base + NIX_LF_QINTX_ENA_W1S(i));\n+\t\tif (dump_stdout && reg)\n+\t\t\tnix_dump(\"%32s_%d = 0x%\" PRIx64,\n+\t\t\t\t \"NIX_LF_QINTX_ENA_W1S\", i, reg);\n+\t\tif (data)\n+\t\t\t*data++ = reg;\n+\t}\n+\n+\t/* NIX_LF_QINTX_ENA_W1C */\n+\tfor (i = 0; i < dev->qints; i++) {\n+\t\treg = otx2_read64(nix_lf_base + NIX_LF_QINTX_ENA_W1C(i));\n+\t\tif (dump_stdout && reg)\n+\t\t\tnix_dump(\"%32s_%d = 0x%\" PRIx64,\n+\t\t\t\t \"NIX_LF_QINTX_ENA_W1C\", i, reg);\n+\t\tif (data)\n+\t\t\t*data++ = reg;\n+\t}\n+\n+\t/* NIX_LF_CINTX_CNT */\n+\tfor (i = 0; i < dev->cints; i++) {\n+\t\treg = otx2_read64(nix_lf_base + NIX_LF_CINTX_CNT(i));\n+\t\tif (dump_stdout && reg)\n+\t\t\tnix_dump(\"%32s_%d = 0x%\" PRIx64,\n+\t\t\t\t \"NIX_LF_CINTX_CNT\", i, reg);\n+\t\tif (data)\n+\t\t\t*data++ = reg;\n+\t}\n+\n+\t/* NIX_LF_CINTX_WAIT */\n+\tfor (i = 0; i < dev->cints; i++) {\n+\t\treg = otx2_read64(nix_lf_base + NIX_LF_CINTX_WAIT(i));\n+\t\tif (dump_stdout && reg)\n+\t\t\tnix_dump(\"%32s_%d = 0x%\" PRIx64,\n+\t\t\t\t \"NIX_LF_CINTX_WAIT\", i, reg);\n+\t\tif (data)\n+\t\t\t*data++ = reg;\n+\t}\n+\n+\t/* NIX_LF_CINTX_INT */\n+\tfor (i = 0; i < dev->cints; i++) {\n+\t\treg = otx2_read64(nix_lf_base + NIX_LF_CINTX_INT(i));\n+\t\tif (dump_stdout && reg)\n+\t\t\tnix_dump(\"%32s_%d = 0x%\" PRIx64,\n+\t\t\t\t \"NIX_LF_CINTX_INT\", i, reg);\n+\t\tif (data)\n+\t\t\t*data++ = reg;\n+\t}\n+\n+\t/* NIX_LF_CINTX_INT_W1S */\n+\tfor (i = 0; i < dev->cints; i++) {\n+\t\treg = otx2_read64(nix_lf_base + NIX_LF_CINTX_INT_W1S(i));\n+\t\tif (dump_stdout && reg)\n+\t\t\tnix_dump(\"%32s_%d = 0x%\" PRIx64,\n+\t\t\t\t \"NIX_LF_CINTX_INT_W1S\", i, reg);\n+\t\tif (data)\n+\t\t\t*data++ = reg;\n+\t}\n+\n+\t/* NIX_LF_CINTX_ENA_W1S */\n+\tfor (i = 0; i < dev->cints; i++) {\n+\t\treg = otx2_read64(nix_lf_base + NIX_LF_CINTX_ENA_W1S(i));\n+\t\tif (dump_stdout && reg)\n+\t\t\tnix_dump(\"%32s_%d = 0x%\" PRIx64,\n+\t\t\t\t \"NIX_LF_CINTX_ENA_W1S\", i, reg);\n+\t\tif (data)\n+\t\t\t*data++ = reg;\n+\t}\n+\n+\t/* NIX_LF_CINTX_ENA_W1C */\n+\tfor (i = 0; i < dev->cints; i++) {\n+\t\treg = otx2_read64(nix_lf_base + NIX_LF_CINTX_ENA_W1C(i));\n+\t\tif (dump_stdout && reg)\n+\t\t\tnix_dump(\"%32s_%d = 0x%\" PRIx64,\n+\t\t\t\t \"NIX_LF_CINTX_ENA_W1C\", i, reg);\n+\t\tif (data)\n+\t\t\t*data++ = reg;\n+\t}\n+\treturn 0;\n+}\n+\n+int\n+otx2_nix_dev_get_reg(struct rte_eth_dev *eth_dev, struct rte_dev_reg_info *regs)\n+{\n+\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n+\tuint64_t *data = regs->data;\n+\n+\tif (data == NULL) {\n+\t\tregs->length = nix_lf_get_reg_count(dev);\n+\t\tregs->width = 8;\n+\t\treturn 0;\n+\t}\n+\n+\tif (!regs->length ||\n+\t regs->length == (uint32_t)nix_lf_get_reg_count(dev)) {\n+\t\totx2_nix_reg_dump(dev, data);\n+\t\treturn 0;\n+\t}\n+\n+\treturn -ENOTSUP;\n+}\n \n static inline void\n nix_lf_sq_dump(struct nix_sq_ctx_s *ctx)\ndiff --git a/drivers/net/octeontx2/otx2_ethdev_irq.c b/drivers/net/octeontx2/otx2_ethdev_irq.c\nindex 9bc9d99f8..7bb0ef35e 100644\n--- a/drivers/net/octeontx2/otx2_ethdev_irq.c\n+++ b/drivers/net/octeontx2/otx2_ethdev_irq.c\n@@ -24,6 +24,8 @@ nix_lf_err_irq(void *param)\n \t/* Clear interrupt */\n \totx2_write64(intr, dev->base + NIX_LF_ERR_INT);\n \n+\t/* Dump registers to std out */\n+\totx2_nix_reg_dump(dev, NULL);\n \totx2_nix_queues_ctx_dump(eth_dev);\n \trte_panic(\"nix_lf_error_interrupt\\n\");\n }\n@@ -79,6 +81,8 @@ nix_lf_ras_irq(void *param)\n \t/* Clear interrupt */\n \totx2_write64(intr, dev->base + NIX_LF_RAS);\n \n+\t/* Dump registers to std out */\n+\totx2_nix_reg_dump(dev, NULL);\n \totx2_nix_queues_ctx_dump(eth_dev);\n \trte_panic(\"nix_lf_ras_interrupt\\n\");\n }\n@@ -239,6 +243,8 @@ nix_lf_q_irq(void *param)\n \t/* Clear interrupt */\n \totx2_write64(intr, dev->base + NIX_LF_QINTX_INT(qintx));\n \n+\t/* Dump registers to std out */\n+\totx2_nix_reg_dump(dev, NULL);\n \totx2_nix_queues_ctx_dump(eth_dev);\n \trte_panic(\"nix_lf_q_interrupt\\n\");\n }\n", "prefixes": [ "v1", "10/58" ] }