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GET /api/patches/54061/?format=api
{ "id": 54061, "url": "http://patches.dpdk.org/api/patches/54061/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20190602152434.23996-6-jerinj@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20190602152434.23996-6-jerinj@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20190602152434.23996-6-jerinj@marvell.com", "date": "2019-06-02T15:23:41", "name": "[v1,05/58] net/octeontx2: handle device error interrupts", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "6548f00e13ce9c333da514e102e8dc404c506a8f", "submitter": { "id": 1188, "url": "http://patches.dpdk.org/api/people/1188/?format=api", "name": "Jerin Jacob Kollanukkaran", "email": "jerinj@marvell.com" }, "delegate": { "id": 319, "url": "http://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20190602152434.23996-6-jerinj@marvell.com/mbox/", "series": [ { "id": 4848, "url": "http://patches.dpdk.org/api/series/4848/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=4848", "date": "2019-06-02T15:23:36", "name": "OCTEON TX2 Ethdev driver", "version": 1, "mbox": "http://patches.dpdk.org/series/4848/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/54061/comments/", "check": "fail", "checks": "http://patches.dpdk.org/api/patches/54061/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id A33521B95A;\n\tSun, 2 Jun 2019 17:24:54 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n\t[67.231.156.173]) by dpdk.org (Postfix) with ESMTP id 196BD1B964\n\tfor <dev@dpdk.org>; Sun, 2 Jun 2019 17:24:53 +0200 (CEST)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n\tby mx0b-0016f401.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id\n\tx52FK4Yc020248; Sun, 2 Jun 2019 08:24:52 -0700", "from sc-exch04.marvell.com ([199.233.58.184])\n\tby mx0b-0016f401.pphosted.com with ESMTP id 2survk4912-1\n\t(version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); \n\tSun, 02 Jun 2019 08:24:52 -0700", "from SC-EXCH01.marvell.com (10.93.176.81) by SC-EXCH04.marvell.com\n\t(10.93.176.84) with Microsoft SMTP Server (TLS) id 15.0.1367.3;\n\tSun, 2 Jun 2019 08:24:50 -0700", "from maili.marvell.com (10.93.176.43) by SC-EXCH01.marvell.com\n\t(10.93.176.81) with Microsoft SMTP Server id 15.0.1367.3 via Frontend\n\tTransport; Sun, 2 Jun 2019 08:24:50 -0700", "from jerin-lab.marvell.com (jerin-lab.marvell.com [10.28.34.14])\n\tby maili.marvell.com (Postfix) with ESMTP id 20D123F7040;\n\tSun, 2 Jun 2019 08:24:48 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n\th=from : to : cc :\n\tsubject : date : message-id : in-reply-to : references : mime-version\n\t: content-transfer-encoding : content-type; s=pfpt0818;\n\tbh=BwLUGcyJQijgn6oO43rjpGDJqEAJjgcDtPiQJVHf2x4=;\n\tb=YIj4XYCfWRFQlnbID+0oKrZiBbs+s4n2QTR4a+rORpLIqJFP1g7GrukzNvrI5lg955Ru\n\t3KSsLLx/kMF4woFvl+f2YCzxOuZyyrmVMzqEo5aWSI7aKU2y8f1W+U6zhJ+/QuwsNIjR\n\tZ8hjJeJoUrncDMwkQgpcjxY536Cforx3bQRbiA6d/+uyelUhIkPwRWj/PEW1SXCsyY1Y\n\tTT4iUPFV/7jKKbf5HCoTJwxQ+nTw9EZV31IJ1DS0BfSDvc8Sk8eeeFQ63XO7xlCMuXPj\n\tLV0Iaxqq6AuRvonu/DAqq7mGUOrQA9PKMerChFUB6045FI+t/Rddr8U2iI9i9tQ0adH9\n\tCg== ", "From": "<jerinj@marvell.com>", "To": "<dev@dpdk.org>, Jerin Jacob <jerinj@marvell.com>, Nithin Dabilpuram\n\t<ndabilpuram@marvell.com>, Kiran Kumar K <kirankumark@marvell.com>", "CC": "<ferruh.yigit@intel.com>, Harman Kalra <hkalra@marvell.com>", "Date": "Sun, 2 Jun 2019 20:53:41 +0530", "Message-ID": "<20190602152434.23996-6-jerinj@marvell.com>", "X-Mailer": "git-send-email 2.21.0", "In-Reply-To": "<20190602152434.23996-1-jerinj@marvell.com>", "References": "<20190602152434.23996-1-jerinj@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:, ,\n\tdefinitions=2019-06-02_09:, , signatures=0", "Subject": "[dpdk-dev] [PATCH v1 05/58] net/octeontx2: handle device error\n\tinterrupts", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Jerin Jacob <jerinj@marvell.com>\n\nHandle device specific error and ras interrupts.\n\nSigned-off-by: Jerin Jacob <jerinj@marvell.com>\nSigned-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>\nSigned-off-by: Harman Kalra <hkalra@marvell.com>\n---\n drivers/net/octeontx2/Makefile | 1 +\n drivers/net/octeontx2/meson.build | 1 +\n drivers/net/octeontx2/otx2_ethdev.c | 12 +-\n drivers/net/octeontx2/otx2_ethdev.h | 4 +\n drivers/net/octeontx2/otx2_ethdev_irq.c | 140 ++++++++++++++++++++++++\n 5 files changed, 156 insertions(+), 2 deletions(-)\n create mode 100644 drivers/net/octeontx2/otx2_ethdev_irq.c", "diff": "diff --git a/drivers/net/octeontx2/Makefile b/drivers/net/octeontx2/Makefile\nindex dbcfec5b4..a56143dcd 100644\n--- a/drivers/net/octeontx2/Makefile\n+++ b/drivers/net/octeontx2/Makefile\n@@ -32,6 +32,7 @@ LIBABIVER := 1\n SRCS-$(CONFIG_RTE_LIBRTE_OCTEONTX2_PMD) += \\\n \totx2_mac.c\t\\\n \totx2_ethdev.c\t\\\n+\totx2_ethdev_irq.c \\\n \totx2_ethdev_devargs.c\n \n LDLIBS += -lrte_eal -lrte_mbuf -lrte_mempool -lrte_common_octeontx2 -lm\ndiff --git a/drivers/net/octeontx2/meson.build b/drivers/net/octeontx2/meson.build\nindex 57657de3d..c49e1cb80 100644\n--- a/drivers/net/octeontx2/meson.build\n+++ b/drivers/net/octeontx2/meson.build\n@@ -5,6 +5,7 @@\n sources = files(\n \t\t'otx2_mac.c',\n \t\t'otx2_ethdev.c',\n+\t\t'otx2_ethdev_irq.c',\n \t\t'otx2_ethdev_devargs.c'\n \t\t)\n \ndiff --git a/drivers/net/octeontx2/otx2_ethdev.c b/drivers/net/octeontx2/otx2_ethdev.c\nindex eeba0c2c6..67a7ebb36 100644\n--- a/drivers/net/octeontx2/otx2_ethdev.c\n+++ b/drivers/net/octeontx2/otx2_ethdev.c\n@@ -175,12 +175,17 @@ otx2_eth_dev_init(struct rte_eth_dev *eth_dev)\n \tif (rc)\n \t\tgoto otx2_npa_uninit;\n \n+\t/* Register LF irq handlers */\n+\trc = otx2_nix_register_irqs(eth_dev);\n+\tif (rc)\n+\t\tgoto mbox_detach;\n+\n \t/* Get maximum number of supported MAC entries */\n \tmax_entries = otx2_cgx_mac_max_entries_get(dev);\n \tif (max_entries < 0) {\n \t\totx2_err(\"Failed to get max entries for mac addr\");\n \t\trc = -ENOTSUP;\n-\t\tgoto mbox_detach;\n+\t\tgoto unregister_irq;\n \t}\n \n \t/* For VFs, returned max_entries will be 0. But to keep default MAC\n@@ -194,7 +199,7 @@ otx2_eth_dev_init(struct rte_eth_dev *eth_dev)\n \tif (eth_dev->data->mac_addrs == NULL) {\n \t\totx2_err(\"Failed to allocate memory for mac addr\");\n \t\trc = -ENOMEM;\n-\t\tgoto mbox_detach;\n+\t\tgoto unregister_irq;\n \t}\n \n \tdev->max_mac_entries = max_entries;\n@@ -226,6 +231,8 @@ otx2_eth_dev_init(struct rte_eth_dev *eth_dev)\n \n free_mac_addrs:\n \trte_free(eth_dev->data->mac_addrs);\n+unregister_irq:\n+\totx2_nix_unregister_irqs(eth_dev);\n mbox_detach:\n \totx2_eth_dev_lf_detach(dev->mbox);\n otx2_npa_uninit:\n@@ -261,6 +268,7 @@ otx2_eth_dev_uninit(struct rte_eth_dev *eth_dev, bool mbox_close)\n \tdev->drv_inited = false;\n \n \tpci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);\n+\totx2_nix_unregister_irqs(eth_dev);\n \n \trc = otx2_eth_dev_lf_detach(dev->mbox);\n \tif (rc)\ndiff --git a/drivers/net/octeontx2/otx2_ethdev.h b/drivers/net/octeontx2/otx2_ethdev.h\nindex f91e5fcac..670d1ff0b 100644\n--- a/drivers/net/octeontx2/otx2_ethdev.h\n+++ b/drivers/net/octeontx2/otx2_ethdev.h\n@@ -102,6 +102,10 @@ otx2_eth_pmd_priv(struct rte_eth_dev *eth_dev)\n \treturn eth_dev->data->dev_private;\n }\n \n+/* IRQ */\n+int otx2_nix_register_irqs(struct rte_eth_dev *eth_dev);\n+void otx2_nix_unregister_irqs(struct rte_eth_dev *eth_dev);\n+\n /* CGX */\n int otx2_cgx_rxtx_start(struct otx2_eth_dev *dev);\n int otx2_cgx_rxtx_stop(struct otx2_eth_dev *dev);\ndiff --git a/drivers/net/octeontx2/otx2_ethdev_irq.c b/drivers/net/octeontx2/otx2_ethdev_irq.c\nnew file mode 100644\nindex 000000000..33fed93c4\n--- /dev/null\n+++ b/drivers/net/octeontx2/otx2_ethdev_irq.c\n@@ -0,0 +1,140 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2019 Marvell International Ltd.\n+ */\n+\n+#include <inttypes.h>\n+\n+#include <rte_bus_pci.h>\n+\n+#include \"otx2_ethdev.h\"\n+\n+static void\n+nix_lf_err_irq(void *param)\n+{\n+\tstruct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;\n+\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n+\tuint64_t intr;\n+\n+\tintr = otx2_read64(dev->base + NIX_LF_ERR_INT);\n+\tif (intr == 0)\n+\t\treturn;\n+\n+\totx2_err(\"Err_intr=0x%\" PRIx64 \" pf=%d, vf=%d\", intr, dev->pf, dev->vf);\n+\n+\t/* Clear interrupt */\n+\totx2_write64(intr, dev->base + NIX_LF_ERR_INT);\n+}\n+\n+static int\n+nix_lf_register_err_irq(struct rte_eth_dev *eth_dev)\n+{\n+\tstruct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);\n+\tstruct rte_intr_handle *handle = &pci_dev->intr_handle;\n+\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n+\tint rc, vec;\n+\n+\tvec = dev->nix_msixoff + NIX_LF_INT_VEC_ERR_INT;\n+\n+\t/* Clear err interrupt */\n+\totx2_write64(~0ull, dev->base + NIX_LF_ERR_INT_ENA_W1C);\n+\t/* Set used interrupt vectors */\n+\trc = otx2_register_irq(handle, nix_lf_err_irq, eth_dev, vec);\n+\t/* Enable all dev interrupt except for RQ_DISABLED */\n+\totx2_write64(~BIT_ULL(11), dev->base + NIX_LF_ERR_INT_ENA_W1S);\n+\n+\treturn rc;\n+}\n+\n+static void\n+nix_lf_unregister_err_irq(struct rte_eth_dev *eth_dev)\n+{\n+\tstruct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);\n+\tstruct rte_intr_handle *handle = &pci_dev->intr_handle;\n+\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n+\tint vec;\n+\n+\tvec = dev->nix_msixoff + NIX_LF_INT_VEC_ERR_INT;\n+\n+\t/* Clear err interrupt */\n+\totx2_write64(~0ull, dev->base + NIX_LF_ERR_INT_ENA_W1C);\n+\totx2_unregister_irq(handle, nix_lf_err_irq, eth_dev, vec);\n+}\n+\n+static void\n+nix_lf_ras_irq(void *param)\n+{\n+\tstruct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;\n+\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n+\tuint64_t intr;\n+\n+\tintr = otx2_read64(dev->base + NIX_LF_RAS);\n+\tif (intr == 0)\n+\t\treturn;\n+\n+\totx2_err(\"Ras_intr=0x%\" PRIx64 \" pf=%d, vf=%d\", intr, dev->pf, dev->vf);\n+\n+\t/* Clear interrupt */\n+\totx2_write64(intr, dev->base + NIX_LF_RAS);\n+}\n+\n+static int\n+nix_lf_register_ras_irq(struct rte_eth_dev *eth_dev)\n+{\n+\tstruct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);\n+\tstruct rte_intr_handle *handle = &pci_dev->intr_handle;\n+\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n+\tint rc, vec;\n+\n+\tvec = dev->nix_msixoff + NIX_LF_INT_VEC_POISON;\n+\n+\t/* Clear err interrupt */\n+\totx2_write64(~0ull, dev->base + NIX_LF_RAS_ENA_W1C);\n+\t/* Set used interrupt vectors */\n+\trc = otx2_register_irq(handle, nix_lf_ras_irq, eth_dev, vec);\n+\t/* Enable dev interrupt */\n+\totx2_write64(~0ull, dev->base + NIX_LF_RAS_ENA_W1S);\n+\n+\treturn rc;\n+}\n+\n+static void\n+nix_lf_unregister_ras_irq(struct rte_eth_dev *eth_dev)\n+{\n+\tstruct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);\n+\tstruct rte_intr_handle *handle = &pci_dev->intr_handle;\n+\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n+\tint vec;\n+\n+\tvec = dev->nix_msixoff + NIX_LF_INT_VEC_POISON;\n+\n+\t/* Clear err interrupt */\n+\totx2_write64(~0ull, dev->base + NIX_LF_RAS_ENA_W1C);\n+\totx2_unregister_irq(handle, nix_lf_ras_irq, eth_dev, vec);\n+}\n+\n+int\n+otx2_nix_register_irqs(struct rte_eth_dev *eth_dev)\n+{\n+\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n+\tint rc;\n+\n+\tif (dev->nix_msixoff == MSIX_VECTOR_INVALID) {\n+\t\totx2_err(\"Invalid NIXLF MSIX vector offset vector: 0x%x\",\n+\t\t\t dev->nix_msixoff);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\t/* Register lf err interrupt */\n+\trc = nix_lf_register_err_irq(eth_dev);\n+\t/* Register RAS interrupt */\n+\trc |= nix_lf_register_ras_irq(eth_dev);\n+\n+\treturn rc;\n+}\n+\n+void\n+otx2_nix_unregister_irqs(struct rte_eth_dev *eth_dev)\n+{\n+\tnix_lf_unregister_err_irq(eth_dev);\n+\tnix_lf_unregister_ras_irq(eth_dev);\n+}\n", "prefixes": [ "v1", "05/58" ] }