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{
    "id": 54060,
    "url": "http://patches.dpdk.org/api/patches/54060/?format=api",
    "web_url": "http://patches.dpdk.org/project/dpdk/patch/20190602152434.23996-5-jerinj@marvell.com/",
    "project": {
        "id": 1,
        "url": "http://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<20190602152434.23996-5-jerinj@marvell.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/20190602152434.23996-5-jerinj@marvell.com",
    "date": "2019-06-02T15:23:40",
    "name": "[v1,04/58] net/octeontx2: add devargs parsing functions",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": true,
    "hash": "0916579a3738d81fc0a0fdbaa4e0bf0a9265a70a",
    "submitter": {
        "id": 1188,
        "url": "http://patches.dpdk.org/api/people/1188/?format=api",
        "name": "Jerin Jacob Kollanukkaran",
        "email": "jerinj@marvell.com"
    },
    "delegate": {
        "id": 319,
        "url": "http://patches.dpdk.org/api/users/319/?format=api",
        "username": "fyigit",
        "first_name": "Ferruh",
        "last_name": "Yigit",
        "email": "ferruh.yigit@amd.com"
    },
    "mbox": "http://patches.dpdk.org/project/dpdk/patch/20190602152434.23996-5-jerinj@marvell.com/mbox/",
    "series": [
        {
            "id": 4848,
            "url": "http://patches.dpdk.org/api/series/4848/?format=api",
            "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=4848",
            "date": "2019-06-02T15:23:36",
            "name": "OCTEON TX2 Ethdev driver",
            "version": 1,
            "mbox": "http://patches.dpdk.org/series/4848/mbox/"
        }
    ],
    "comments": "http://patches.dpdk.org/api/patches/54060/comments/",
    "check": "fail",
    "checks": "http://patches.dpdk.org/api/patches/54060/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@dpdk.org",
        "Delivered-To": "patchwork@dpdk.org",
        "Received": [
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            "from jerin-lab.marvell.com (jerin-lab.marvell.com [10.28.34.14])\n\tby maili.marvell.com (Postfix) with ESMTP id DC56F3F703F;\n\tSun,  2 Jun 2019 08:24:45 -0700 (PDT)"
        ],
        "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n\th=from : to : cc :\n\tsubject : date : message-id : in-reply-to : references : mime-version\n\t: content-transfer-encoding : content-type; s=pfpt0818;\n\tbh=0ghDKM4kvjam50/0X1Iw8KQJvj9UiIvMaUfetRGfpgY=;\n\tb=p7oCANBlxXDaUE8zkJrvnKEfjQpGzPJTsMl2a2I06SZ03TC1m3h+dk+fIG4ZD0toaPq8\n\tF6nf+V9hFC7AQpAdGGbMSAPcxtRI7mIUDquh5HTf604j2IwDoE8SEamj2voOoGCfV8cJ\n\tiK+puAUyw584RA+/bum2z5325WxyXaAfItE9NCpPwT/E5VZj9wl2tBtc1WaNhhqsyryx\n\tonpByvP3S6gWEAuJcqV8Uxjc2lwNNXmqM1AkVb0RGFFVGrEhUUTSmqisqM/vHnYR2vAa\n\tpwSkk3YvOXEfzBL9a8OCVFLCvU7VcL86vvO1Y7seOcJa5jypH6RiIo8f8bV6fCP6RhDP\n\tMA== ",
        "From": "<jerinj@marvell.com>",
        "To": "<dev@dpdk.org>, Jerin Jacob <jerinj@marvell.com>, Nithin Dabilpuram\n\t<ndabilpuram@marvell.com>, Kiran Kumar K <kirankumark@marvell.com>",
        "CC": "<ferruh.yigit@intel.com>, Pavan Nikhilesh <pbhagavatula@marvell.com>",
        "Date": "Sun, 2 Jun 2019 20:53:40 +0530",
        "Message-ID": "<20190602152434.23996-5-jerinj@marvell.com>",
        "X-Mailer": "git-send-email 2.21.0",
        "In-Reply-To": "<20190602152434.23996-1-jerinj@marvell.com>",
        "References": "<20190602152434.23996-1-jerinj@marvell.com>",
        "MIME-Version": "1.0",
        "Content-Transfer-Encoding": "8bit",
        "Content-Type": "text/plain",
        "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:, ,\n\tdefinitions=2019-06-02_09:, , signatures=0",
        "Subject": "[dpdk-dev] [PATCH v1 04/58] net/octeontx2: add devargs parsing\n\tfunctions",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.15",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "From: Jerin Jacob <jerinj@marvell.com>\n\nadd various devargs command line options supported by\nthis driver.\n\nSigned-off-by: Jerin Jacob <jerinj@marvell.com>\nSigned-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>\nSigned-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>\nSigned-off-by: Kiran Kumar K <kirankumark@marvell.com>\n---\n drivers/net/octeontx2/Makefile              |   3 +-\n drivers/net/octeontx2/meson.build           |   1 +\n drivers/net/octeontx2/otx2_ethdev.c         |   7 +\n drivers/net/octeontx2/otx2_ethdev.h         |  20 +++\n drivers/net/octeontx2/otx2_ethdev_devargs.c | 143 ++++++++++++++++++++\n drivers/net/octeontx2/otx2_rx.h             |  10 ++\n 6 files changed, 183 insertions(+), 1 deletion(-)\n create mode 100644 drivers/net/octeontx2/otx2_ethdev_devargs.c\n create mode 100644 drivers/net/octeontx2/otx2_rx.h",
    "diff": "diff --git a/drivers/net/octeontx2/Makefile b/drivers/net/octeontx2/Makefile\nindex 9ca1eea99..dbcfec5b4 100644\n--- a/drivers/net/octeontx2/Makefile\n+++ b/drivers/net/octeontx2/Makefile\n@@ -31,7 +31,8 @@ LIBABIVER := 1\n #\n SRCS-$(CONFIG_RTE_LIBRTE_OCTEONTX2_PMD) += \\\n \totx2_mac.c\t\\\n-\totx2_ethdev.c\n+\totx2_ethdev.c\t\\\n+\totx2_ethdev_devargs.c\n \n LDLIBS += -lrte_eal -lrte_mbuf -lrte_mempool -lrte_common_octeontx2 -lm\n LDLIBS += -lrte_ethdev -lrte_net -lrte_kvargs -lrte_bus_pci -lrte_mempool_octeontx2\ndiff --git a/drivers/net/octeontx2/meson.build b/drivers/net/octeontx2/meson.build\nindex 6cdd036e9..57657de3d 100644\n--- a/drivers/net/octeontx2/meson.build\n+++ b/drivers/net/octeontx2/meson.build\n@@ -5,6 +5,7 @@\n sources = files(\n \t\t'otx2_mac.c',\n \t\t'otx2_ethdev.c',\n+\t\t'otx2_ethdev_devargs.c'\n \t\t)\n \n allow_experimental_apis = true\ndiff --git a/drivers/net/octeontx2/otx2_ethdev.c b/drivers/net/octeontx2/otx2_ethdev.c\nindex 08f03b4c3..eeba0c2c6 100644\n--- a/drivers/net/octeontx2/otx2_ethdev.c\n+++ b/drivers/net/octeontx2/otx2_ethdev.c\n@@ -137,6 +137,13 @@ otx2_eth_dev_init(struct rte_eth_dev *eth_dev)\n \tmemset(&dev->otx2_eth_dev_data_start, 0, sizeof(*dev) -\n \t\toffsetof(struct otx2_eth_dev, otx2_eth_dev_data_start));\n \n+\t/* Parse devargs string */\n+\trc = otx2_ethdev_parse_devargs(eth_dev->device->devargs, dev);\n+\tif (rc) {\n+\t\totx2_err(\"Failed to parse devargs rc=%d\", rc);\n+\t\tgoto error;\n+\t}\n+\n \tif (!dev->mbox_active) {\n \t\t/* Initialize the base otx2_dev object\n \t\t * only if already present\ndiff --git a/drivers/net/octeontx2/otx2_ethdev.h b/drivers/net/octeontx2/otx2_ethdev.h\nindex d9f72686a..f91e5fcac 100644\n--- a/drivers/net/octeontx2/otx2_ethdev.h\n+++ b/drivers/net/octeontx2/otx2_ethdev.h\n@@ -9,11 +9,13 @@\n \n #include <rte_common.h>\n #include <rte_ethdev.h>\n+#include <rte_kvargs.h>\n \n #include \"otx2_common.h\"\n #include \"otx2_dev.h\"\n #include \"otx2_irq.h\"\n #include \"otx2_mempool.h\"\n+#include \"otx2_rx.h\"\n \n #define OTX2_ETH_DEV_PMD_VERSION\t\"1.0\"\n \n@@ -31,6 +33,8 @@\n /* Used for struct otx2_eth_dev::flags */\n #define OTX2_LINK_CFG_IN_PROGRESS_F\tBIT_ULL(0)\n \n+#define NIX_RSS_RETA_SIZE\t\t64\n+\n #define NIX_TX_OFFLOAD_CAPA ( \\\n \tDEV_TX_OFFLOAD_MBUF_FAST_FREE\t| \\\n \tDEV_TX_OFFLOAD_MT_LOCKFREE\t| \\\n@@ -56,6 +60,15 @@\n \tDEV_RX_OFFLOAD_QINQ_STRIP | \\\n \tDEV_RX_OFFLOAD_TIMESTAMP)\n \n+struct otx2_rss_info {\n+\tuint16_t rss_size;\n+};\n+\n+struct otx2_npc_flow_info {\n+\tuint16_t flow_prealloc_size;\n+\tuint16_t flow_max_priority;\n+};\n+\n struct otx2_eth_dev {\n \tOTX2_DEV; /* Base class */\n \tMARKER otx2_eth_dev_data_start;\n@@ -72,12 +85,15 @@ struct otx2_eth_dev {\n \tuint16_t nix_msixoff;\n \tuintptr_t base;\n \tuintptr_t lmt_addr;\n+\tuint16_t scalar_ena;\n \tuint16_t rx_offload_flags; /* Selected Rx offload flags(NIX_RX_*_F) */\n \tuint64_t rx_offloads;\n \tuint16_t tx_offload_flags; /* Selected Tx offload flags(NIX_TX_*_F) */\n \tuint64_t tx_offloads;\n \tuint64_t rx_offload_capa;\n \tuint64_t tx_offload_capa;\n+\tstruct otx2_rss_info rss_info;\n+\tstruct otx2_npc_flow_info npc_flow;\n } __rte_cache_aligned;\n \n static inline struct otx2_eth_dev *\n@@ -96,4 +112,8 @@ int otx2_cgx_mac_addr_set(struct rte_eth_dev *eth_dev,\n int otx2_nix_mac_addr_get(struct rte_eth_dev *eth_dev, uint8_t *addr);\n int otx2_cgx_mac_max_entries_get(struct otx2_eth_dev *dev);\n \n+/* Devargs */\n+int otx2_ethdev_parse_devargs(struct rte_devargs *devargs,\n+\t\t\t      struct otx2_eth_dev *dev);\n+\n #endif /* __OTX2_ETHDEV_H__ */\ndiff --git a/drivers/net/octeontx2/otx2_ethdev_devargs.c b/drivers/net/octeontx2/otx2_ethdev_devargs.c\nnew file mode 100644\nindex 000000000..0b3e7c145\n--- /dev/null\n+++ b/drivers/net/octeontx2/otx2_ethdev_devargs.c\n@@ -0,0 +1,143 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2019 Marvell International Ltd.\n+ */\n+\n+#include <inttypes.h>\n+#include <math.h>\n+\n+#include \"otx2_ethdev.h\"\n+\n+static int\n+parse_flow_max_priority(const char *key, const char *value, void *extra_args)\n+{\n+\tRTE_SET_USED(key);\n+\tuint16_t val;\n+\n+\tval = atoi(value);\n+\n+\t/* Limit the max priority to 32 */\n+\tif (val < 1 || val > 32)\n+\t\treturn -EINVAL;\n+\n+\t*(uint16_t *)extra_args = val;\n+\n+\treturn 0;\n+}\n+\n+static int\n+parse_flow_prealloc_size(const char *key, const char *value, void *extra_args)\n+{\n+\tRTE_SET_USED(key);\n+\tuint16_t val;\n+\n+\tval = atoi(value);\n+\n+\t/* Limit the prealloc size to 32 */\n+\tif (val < 1 || val > 32)\n+\t\treturn -EINVAL;\n+\n+\t*(uint16_t *)extra_args = val;\n+\n+\treturn 0;\n+}\n+\n+static int\n+parse_reta_size(const char *key, const char *value, void *extra_args)\n+{\n+\tRTE_SET_USED(key);\n+\tuint32_t val;\n+\n+\tval = atoi(value);\n+\n+\tif (val <= ETH_RSS_RETA_SIZE_64)\n+\t\tval = ETH_RSS_RETA_SIZE_64;\n+\telse if (val > ETH_RSS_RETA_SIZE_64 && val <= ETH_RSS_RETA_SIZE_128)\n+\t\tval = ETH_RSS_RETA_SIZE_128;\n+\telse if (val > ETH_RSS_RETA_SIZE_128 && val <= ETH_RSS_RETA_SIZE_256)\n+\t\tval = ETH_RSS_RETA_SIZE_256;\n+\telse\n+\t\tval = NIX_RSS_RETA_SIZE;\n+\n+\t*(uint16_t *)extra_args = val;\n+\n+\treturn 0;\n+}\n+\n+static int\n+parse_ptype_flag(const char *key, const char *value, void *extra_args)\n+{\n+\tRTE_SET_USED(key);\n+\tuint32_t val;\n+\n+\tval = atoi(value);\n+\tif (val)\n+\t\tval = 0; /* Disable NIX_RX_OFFLOAD_PTYPE_F */\n+\n+\t*(uint16_t *)extra_args = val;\n+\n+\treturn 0;\n+}\n+\n+static int\n+parse_flag(const char *key, const char *value, void *extra_args)\n+{\n+\tRTE_SET_USED(key);\n+\n+\t*(uint16_t *)extra_args = atoi(value);\n+\n+\treturn 0;\n+}\n+\n+#define OTX2_RSS_RETA_SIZE \"reta_size\"\n+#define OTX2_PTYPE_DISABLE \"ptype_disable\"\n+#define OTX2_SCL_ENABLE \"scalar_enable\"\n+#define OTX2_FLOW_PREALLOC_SIZE \"flow_prealloc_size\"\n+#define OTX2_FLOW_MAX_PRIORITY \"flow_max_priority\"\n+\n+int\n+otx2_ethdev_parse_devargs(struct rte_devargs *devargs, struct otx2_eth_dev *dev)\n+{\n+\tuint16_t offload_flag = NIX_RX_OFFLOAD_PTYPE_F;\n+\tuint16_t rss_size = NIX_RSS_RETA_SIZE;\n+\tuint16_t flow_prealloc_size = 8;\n+\tuint16_t flow_max_priority = 3;\n+\tuint16_t scalar_enable = 0;\n+\tstruct rte_kvargs *kvlist;\n+\n+\tif (devargs == NULL)\n+\t\tgoto null_devargs;\n+\n+\tkvlist = rte_kvargs_parse(devargs->args, NULL);\n+\tif (kvlist == NULL)\n+\t\tgoto exit;\n+\n+\trte_kvargs_process(kvlist, OTX2_PTYPE_DISABLE,\n+\t\t\t   &parse_ptype_flag, &offload_flag);\n+\trte_kvargs_process(kvlist, OTX2_RSS_RETA_SIZE,\n+\t\t\t   &parse_reta_size, &rss_size);\n+\trte_kvargs_process(kvlist, OTX2_SCL_ENABLE,\n+\t\t\t   &parse_flag, &scalar_enable);\n+\trte_kvargs_process(kvlist, OTX2_FLOW_PREALLOC_SIZE,\n+\t\t\t   &parse_flow_prealloc_size, &flow_prealloc_size);\n+\trte_kvargs_process(kvlist, OTX2_FLOW_MAX_PRIORITY,\n+\t\t\t   &parse_flow_max_priority, &flow_max_priority);\n+\trte_kvargs_free(kvlist);\n+\n+null_devargs:\n+\tdev->rx_offload_flags = offload_flag;\n+\tdev->scalar_ena = scalar_enable;\n+\tdev->rss_info.rss_size = rss_size;\n+\tdev->npc_flow.flow_prealloc_size = flow_prealloc_size;\n+\tdev->npc_flow.flow_max_priority = flow_max_priority;\n+\treturn 0;\n+\n+exit:\n+\treturn -EINVAL;\n+}\n+\n+RTE_PMD_REGISTER_PARAM_STRING(net_octeontx2,\n+\t\t\t      OTX2_RSS_RETA_SIZE \"=<64|128|256>\"\n+\t\t\t      OTX2_PTYPE_DISABLE \"=1\"\n+\t\t\t      OTX2_SCL_ENABLE \"=1\"\n+\t\t\t      OTX2_FLOW_PREALLOC_SIZE \"=<1-32>\"\n+\t\t\t      OTX2_FLOW_MAX_PRIORITY \"=<1-32>\");\ndiff --git a/drivers/net/octeontx2/otx2_rx.h b/drivers/net/octeontx2/otx2_rx.h\nnew file mode 100644\nindex 000000000..1749c43ff\n--- /dev/null\n+++ b/drivers/net/octeontx2/otx2_rx.h\n@@ -0,0 +1,10 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2019 Marvell International Ltd.\n+ */\n+\n+#ifndef __OTX2_RX_H__\n+#define __OTX2_RX_H__\n+\n+#define NIX_RX_OFFLOAD_PTYPE_F         BIT(1)\n+\n+#endif /* __OTX2_RX_H__ */\n",
    "prefixes": [
        "v1",
        "04/58"
    ]
}