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GET /api/patches/54053/?format=api
http://patches.dpdk.org/api/patches/54053/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20190601185355.370-43-pbhagavatula@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20190601185355.370-43-pbhagavatula@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20190601185355.370-43-pbhagavatula@marvell.com", "date": "2019-06-01T18:53:52", "name": "[42/44] event/octeontx2: add devargs to limit timer adapters", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "65277cc74b55bd50f27bb486b1e19a2d093154c5", "submitter": { "id": 1183, "url": "http://patches.dpdk.org/api/people/1183/?format=api", "name": "Pavan Nikhilesh Bhagavatula", "email": "pbhagavatula@marvell.com" }, "delegate": { "id": 310, "url": "http://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20190601185355.370-43-pbhagavatula@marvell.com/mbox/", "series": [ { "id": 4847, "url": "http://patches.dpdk.org/api/series/4847/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=4847", "date": "2019-06-01T18:53:10", "name": "OCTEON TX2 event device driver", "version": 1, "mbox": "http://patches.dpdk.org/series/4847/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/54053/comments/", "check": "fail", "checks": "http://patches.dpdk.org/api/patches/54053/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 9D6891BBB4;\n\tSat, 1 Jun 2019 20:57:19 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n\t[67.231.148.174]) by dpdk.org (Postfix) with ESMTP id B08941B955\n\tfor <dev@dpdk.org>; Sat, 1 Jun 2019 20:56:48 +0200 (CEST)", "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n\tby mx0a-0016f401.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id\n\tx51It682029402 for <dev@dpdk.org>; Sat, 1 Jun 2019 11:56:48 -0700", "from sc-exch03.marvell.com ([199.233.58.183])\n\tby mx0a-0016f401.pphosted.com with ESMTP id 2supqksg1f-1\n\t(version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n\tfor <dev@dpdk.org>; Sat, 01 Jun 2019 11:56:47 -0700", "from SC-EXCH03.marvell.com (10.93.176.83) by SC-EXCH03.marvell.com\n\t(10.93.176.83) with Microsoft SMTP Server (TLS) id 15.0.1367.3;\n\tSat, 1 Jun 2019 11:56:47 -0700", "from maili.marvell.com (10.93.176.43) by SC-EXCH03.marvell.com\n\t(10.93.176.83) with Microsoft SMTP Server id 15.0.1367.3 via Frontend\n\tTransport; Sat, 1 Jun 2019 11:56:47 -0700", "from BG-LT7430.marvell.com (unknown [10.28.17.28])\n\tby maili.marvell.com (Postfix) with ESMTP id AB5A93F7040;\n\tSat, 1 Jun 2019 11:56:45 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n\th=from : to : cc :\n\tsubject : date : message-id : in-reply-to : references : mime-version\n\t: content-transfer-encoding : content-type; s=pfpt0818;\n\tbh=rh7rP1zBU2U0KmD5lx05/RvxUV01y5rWHyBert6Cvyo=;\n\tb=K+UtVNd/C2Mc1aw9uUmp8Zx+v8pnvpsG41eJ5c9Kd3/CtTSHkTPFJ0BaKSbgwCipkWqc\n\tsyY+gp+mVe+b7ei9IryQMEVW3DyOzry6zeKvj1wxmJnh6EgMMbqDzKazjnZVfN2liItq\n\tOK4sWmnOOAXNSWcW/AK2Rb0/1RIvjpmn5FE8C7FXYuDvonJ+kusuZCBfKUI4gbe9FJRe\n\tSBXXlU8lPmKQnj6mvYQJKnkEWE2K7h6UGcjtN2Z7NU/uyclbYaXh9gMbR6qcQnUZbrmo\n\tQ7wR/02ENe6ty2mRsNil56i0Q4tl1wY4lYuOByrA/dALuFNACiS1Z4IksQdil7ZOxF8d\n\tUA== ", "From": "<pbhagavatula@marvell.com>", "To": "<jerinj@marvell.com>, Pavan Nikhilesh <pbhagavatula@marvell.com>", "CC": "<dev@dpdk.org>", "Date": "Sun, 2 Jun 2019 00:23:52 +0530", "Message-ID": "<20190601185355.370-43-pbhagavatula@marvell.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20190601185355.370-1-pbhagavatula@marvell.com>", "References": "<20190601185355.370-1-pbhagavatula@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:, ,\n\tdefinitions=2019-06-01_13:, , signatures=0", "Subject": "[dpdk-dev] [PATCH 42/44] event/octeontx2: add devargs to limit\n\ttimer adapters", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Pavan Nikhilesh <pbhagavatula@marvell.com>\n\nAdd devargs to limit the max number of TIM rings reserved on probe.\nSince, TIM rings are HW resources we can avoid starving other\napplications by not grabbing all the rings.\nExample:\n\n\t--dev \"0002:0e:00.0,tim_rings_lmt=2\"\n\nSigned-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>\n---\n drivers/event/octeontx2/otx2_tim_evdev.c | 6 +++++-\n drivers/event/octeontx2/otx2_tim_evdev.h | 1 +\n 2 files changed, 6 insertions(+), 1 deletion(-)", "diff": "diff --git a/drivers/event/octeontx2/otx2_tim_evdev.c b/drivers/event/octeontx2/otx2_tim_evdev.c\nindex 2849b8858..c4fd2271e 100644\n--- a/drivers/event/octeontx2/otx2_tim_evdev.c\n+++ b/drivers/event/octeontx2/otx2_tim_evdev.c\n@@ -527,6 +527,7 @@ otx2_tim_caps_get(const struct rte_eventdev *evdev, uint64_t flags,\n #define OTX2_TIM_DISABLE_NPA\t\"tim_disable_npa\"\n #define OTX2_TIM_CHNK_SLOTS\t\"tim_chnk_slots\"\n #define OTX2_TIM_STATS_ENA\t\"tim_stats_ena\"\n+#define OTX2_TIM_RINGS_LMT\t\"tim_rings_lmt\"\n \n static void\n tim_parse_devargs(struct rte_devargs *devargs, struct otx2_tim_evdev *dev)\n@@ -546,6 +547,8 @@ tim_parse_devargs(struct rte_devargs *devargs, struct otx2_tim_evdev *dev)\n \t\t\t &parse_kvargs_value, &dev->chunk_slots);\n \trte_kvargs_process(kvlist, OTX2_TIM_STATS_ENA, &parse_kvargs_flag,\n \t\t\t &dev->enable_stats);\n+\trte_kvargs_process(kvlist, OTX2_TIM_RINGS_LMT, &parse_kvargs_value,\n+\t\t\t &dev->min_ring_cnt);\n }\n \n void\n@@ -583,7 +586,8 @@ otx2_tim_init(struct rte_pci_device *pci_dev, struct otx2_dev *cmn_dev)\n \t\tgoto mz_free;\n \t}\n \n-\tdev->nb_rings = rsrc_cnt->tim;\n+\tdev->nb_rings = dev->min_ring_cnt ?\n+\t\tRTE_MIN(dev->min_ring_cnt, rsrc_cnt->tim) : rsrc_cnt->tim;\n \n \tif (!dev->nb_rings) {\n \t\totx2_tim_dbg(\"No TIM Logical functions provisioned.\");\ndiff --git a/drivers/event/octeontx2/otx2_tim_evdev.h b/drivers/event/octeontx2/otx2_tim_evdev.h\nindex 79be046f0..ef3c8b50e 100644\n--- a/drivers/event/octeontx2/otx2_tim_evdev.h\n+++ b/drivers/event/octeontx2/otx2_tim_evdev.h\n@@ -111,6 +111,7 @@ struct otx2_tim_evdev {\n \t/* Dev args */\n \tuint8_t disable_npa;\n \tuint16_t chunk_slots;\n+\tuint16_t min_ring_cnt;\n \tuint8_t enable_stats;\n \t/* MSIX offsets */\n \tuint16_t tim_msixoff[OTX2_MAX_TIM_RINGS];\n", "prefixes": [ "42/44" ] }{ "id": 54053, "url": "