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GET /api/patches/54044/?format=api
{ "id": 54044, "url": "http://patches.dpdk.org/api/patches/54044/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20190601185355.370-33-pbhagavatula@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20190601185355.370-33-pbhagavatula@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20190601185355.370-33-pbhagavatula@marvell.com", "date": "2019-06-01T18:53:42", "name": "[32/44] event/octeontx2: add devargs to modify chunk slots", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "e3145a2894cce940ba481673a105ed63d895d677", "submitter": { "id": 1183, "url": "http://patches.dpdk.org/api/people/1183/?format=api", "name": "Pavan Nikhilesh Bhagavatula", "email": "pbhagavatula@marvell.com" }, "delegate": { "id": 310, "url": "http://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20190601185355.370-33-pbhagavatula@marvell.com/mbox/", "series": [ { "id": 4847, "url": "http://patches.dpdk.org/api/series/4847/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=4847", "date": "2019-06-01T18:53:10", "name": "OCTEON TX2 event device driver", "version": 1, "mbox": "http://patches.dpdk.org/series/4847/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/54044/comments/", "check": "fail", "checks": "http://patches.dpdk.org/api/patches/54044/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 262B61BAB6;\n\tSat, 1 Jun 2019 20:57:05 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n\t[67.231.148.174]) by dpdk.org (Postfix) with ESMTP id BC6621B9DC\n\tfor <dev@dpdk.org>; Sat, 1 Jun 2019 20:56:22 +0200 (CEST)", "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n\tby mx0a-0016f401.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id\n\tx51ItbNT029526 for <dev@dpdk.org>; Sat, 1 Jun 2019 11:56:22 -0700", "from sc-exch03.marvell.com ([199.233.58.183])\n\tby mx0a-0016f401.pphosted.com with ESMTP id 2supqksg05-1\n\t(version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n\tfor <dev@dpdk.org>; Sat, 01 Jun 2019 11:56:21 -0700", "from SC-EXCH01.marvell.com (10.93.176.81) by SC-EXCH03.marvell.com\n\t(10.93.176.83) with Microsoft SMTP Server (TLS) id 15.0.1367.3;\n\tSat, 1 Jun 2019 11:56:20 -0700", "from maili.marvell.com (10.93.176.43) by SC-EXCH01.marvell.com\n\t(10.93.176.81) with Microsoft SMTP Server id 15.0.1367.3 via Frontend\n\tTransport; Sat, 1 Jun 2019 11:56:20 -0700", "from BG-LT7430.marvell.com (unknown [10.28.17.28])\n\tby maili.marvell.com (Postfix) with ESMTP id AD45C3F7040;\n\tSat, 1 Jun 2019 11:56:19 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n\th=from : to : cc :\n\tsubject : date : message-id : in-reply-to : references : mime-version\n\t: content-transfer-encoding : content-type; s=pfpt0818;\n\tbh=36oElAralxVt9dQk+X6JT+x8UQQ1v9WR+Pdukful8Ik=;\n\tb=N9wND+czyt5pA6apWnNqjkuANaFu5f8HNlzS9QtlcYQG7kE9TYLFgxnrj8HhZlAUmJt6\n\t9OAuD+8yE3exjk+CggdbvRs9nYaczZREnjU5zrj54/wctMJFAESj5CITGk8/k/xBtD4q\n\tfn/TJJFVQjQmxSBzMrEC+OgisVfAhRULSoPJdFZuRaoTgstpQEp3c4DqSzM6GgTmJ6oh\n\tnZxnkqC6ICkO7uo8B5Dx1G2p7wrWYrERS2FJErIOfKUai1jZiiwT4s7nDar/3T1e5Aii\n\tEnX1hIgoH+Q3Faza0yYWR/knHjG/iAfYXGndT5ZYD9j117IrIKWXCrAgmKwzkcMt+1EJ\n\tKg== ", "From": "<pbhagavatula@marvell.com>", "To": "<jerinj@marvell.com>, Pavan Nikhilesh <pbhagavatula@marvell.com>", "CC": "<dev@dpdk.org>", "Date": "Sun, 2 Jun 2019 00:23:42 +0530", "Message-ID": "<20190601185355.370-33-pbhagavatula@marvell.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20190601185355.370-1-pbhagavatula@marvell.com>", "References": "<20190601185355.370-1-pbhagavatula@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:, ,\n\tdefinitions=2019-06-01_13:, , signatures=0", "Subject": "[dpdk-dev] [PATCH 32/44] event/octeontx2: add devargs to modify\n\tchunk slots", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Pavan Nikhilesh <pbhagavatula@marvell.com>\n\nAdd devargs support to modify number of chunk slots. Chunks are used to\nstore event timers, a chunk can be visualised as an array where the last\nelement points to the next chunk and rest of them are used to store\nevents. TIM traverses the list of chunks and enqueues the event timers\nto SSO.\nIf no argument is passed then a default value of 255 is taken.\nExample:\n\n\t--dev \"0002:0e:00.0,tim_chnk_slots=511\"\n\nSigned-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>\n---\n drivers/event/octeontx2/otx2_tim_evdev.c | 11 ++++++++++-\n drivers/event/octeontx2/otx2_tim_evdev.h | 2 ++\n 2 files changed, 12 insertions(+), 1 deletion(-)", "diff": "diff --git a/drivers/event/octeontx2/otx2_tim_evdev.c b/drivers/event/octeontx2/otx2_tim_evdev.c\nindex 9cceafd77..bba6cc609 100644\n--- a/drivers/event/octeontx2/otx2_tim_evdev.c\n+++ b/drivers/event/octeontx2/otx2_tim_evdev.c\n@@ -240,7 +240,7 @@ otx2_tim_ring_create(struct rte_event_timer_adapter *adptr)\n \ttim_ring->tck_nsec = RTE_ALIGN_MUL_CEIL(rcfg->timer_tick_ns, 10);\n \ttim_ring->max_tout = rcfg->max_tmo_ns;\n \ttim_ring->nb_bkts = (tim_ring->max_tout / tim_ring->tck_nsec);\n-\ttim_ring->chunk_sz = OTX2_TIM_RING_DEF_CHNK_SZ;\n+\ttim_ring->chunk_sz = dev->chunk_sz;\n \tnb_timers = rcfg->nb_timers;\n \ttim_ring->disable_npa = dev->disable_npa;\n \n@@ -355,6 +355,7 @@ otx2_tim_caps_get(const struct rte_eventdev *evdev, uint64_t flags,\n }\n \n #define OTX2_TIM_DISABLE_NPA\t\"tim_disable_npa\"\n+#define OTX2_TIM_CHNK_SLOTS\t\"tim_chnk_slots\"\n \n static void\n tim_parse_devargs(struct rte_devargs *devargs, struct otx2_tim_evdev *dev)\n@@ -370,6 +371,8 @@ tim_parse_devargs(struct rte_devargs *devargs, struct otx2_tim_evdev *dev)\n \n \trte_kvargs_process(kvlist, OTX2_TIM_DISABLE_NPA,\n \t\t\t &parse_kvargs_flag, &dev->disable_npa);\n+\trte_kvargs_process(kvlist, OTX2_TIM_CHNK_SLOTS,\n+\t\t\t &parse_kvargs_value, &dev->chunk_slots);\n }\n \n void\n@@ -423,6 +426,12 @@ otx2_tim_init(struct rte_pci_device *pci_dev, struct otx2_dev *cmn_dev)\n \t\tgoto mz_free;\n \t}\n \n+\tif (!dev->chunk_slots)\n+\t\tdev->chunk_sz = OTX2_TIM_RING_DEF_CHNK_SZ;\n+\telse\n+\t\tdev->chunk_sz = (dev->chunk_slots + 1) *\n+\t\t\tOTX2_TIM_CHUNK_ALIGNMENT;\n+\n \treturn;\n \n mz_free:\ndiff --git a/drivers/event/octeontx2/otx2_tim_evdev.h b/drivers/event/octeontx2/otx2_tim_evdev.h\nindex e4b8cd4ce..617902a0b 100644\n--- a/drivers/event/octeontx2/otx2_tim_evdev.h\n+++ b/drivers/event/octeontx2/otx2_tim_evdev.h\n@@ -54,9 +54,11 @@ struct otx2_tim_evdev {\n \tstruct rte_eventdev *event_dev;\n \tstruct otx2_mbox *mbox;\n \tuint16_t nb_rings;\n+\tuint32_t chunk_sz;\n \tuintptr_t bar2;\n \t/* Dev args */\n \tuint8_t disable_npa;\n+\tuint16_t chunk_slots;\n };\n \n struct otx2_tim_ring {\n", "prefixes": [ "32/44" ] }