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GET /api/patches/54043/?format=api
{ "id": 54043, "url": "http://patches.dpdk.org/api/patches/54043/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20190601185355.370-32-pbhagavatula@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20190601185355.370-32-pbhagavatula@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20190601185355.370-32-pbhagavatula@marvell.com", "date": "2019-06-01T18:53:41", "name": "[31/44] event/octeontx2: add devargs to disable NPA", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "53b64cbd580ce1abb9c9c7e62b3718056376e633", "submitter": { "id": 1183, "url": "http://patches.dpdk.org/api/people/1183/?format=api", "name": "Pavan Nikhilesh Bhagavatula", "email": "pbhagavatula@marvell.com" }, "delegate": { "id": 310, "url": "http://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20190601185355.370-32-pbhagavatula@marvell.com/mbox/", "series": [ { "id": 4847, "url": "http://patches.dpdk.org/api/series/4847/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=4847", "date": "2019-06-01T18:53:10", "name": "OCTEON TX2 event device driver", "version": 1, "mbox": "http://patches.dpdk.org/series/4847/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/54043/comments/", "check": "fail", "checks": "http://patches.dpdk.org/api/patches/54043/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id B9D861BA8E;\n\tSat, 1 Jun 2019 20:57:03 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n\t[67.231.156.173]) by dpdk.org (Postfix) with ESMTP id 579012BD3\n\tfor <dev@dpdk.org>; Sat, 1 Jun 2019 20:56:20 +0200 (CEST)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n\tby mx0b-0016f401.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id\n\tx51It9nr029954 for <dev@dpdk.org>; Sat, 1 Jun 2019 11:56:19 -0700", "from sc-exch02.marvell.com ([199.233.58.182])\n\tby mx0b-0016f401.pphosted.com with ESMTP id 2survk12gx-1\n\t(version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n\tfor <dev@dpdk.org>; Sat, 01 Jun 2019 11:56:19 -0700", "from SC-EXCH03.marvell.com (10.93.176.83) by SC-EXCH02.marvell.com\n\t(10.93.176.82) with Microsoft SMTP Server (TLS) id 15.0.1367.3;\n\tSat, 1 Jun 2019 11:56:18 -0700", "from maili.marvell.com (10.93.176.43) by SC-EXCH03.marvell.com\n\t(10.93.176.83) with Microsoft SMTP Server id 15.0.1367.3 via Frontend\n\tTransport; Sat, 1 Jun 2019 11:56:18 -0700", "from BG-LT7430.marvell.com (unknown [10.28.17.28])\n\tby maili.marvell.com (Postfix) with ESMTP id 24D3B3F7040;\n\tSat, 1 Jun 2019 11:56:16 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n\th=from : to : cc :\n\tsubject : date : message-id : in-reply-to : references : mime-version\n\t: content-transfer-encoding : content-type; s=pfpt0818;\n\tbh=Y/LD/wzVCzAiPD5hKqPhFkKLaqTqqg4lpLngtjDX/Uc=;\n\tb=OQIANOPnQP6xgPfF53JWUOHMR/LULBSS+cgw094gHjeioUh4keBc932Ph5grvkYAjowU\n\t02rv1JwYqgFL42EO131m22QWPFR8ykbja3PRPD3oDUlErQVwiiQRpvRd41znxbS6TGK6\n\tCeqlghf6AMx4Vhft0pn6By2mSMpksAQkckmzHTAvX2fZVX//4FeP3YXy6fMg1r+/4EKQ\n\ttWfQMtthQ40EB/dAdXyKlgCG+/oZlvkA+ppaqSq9PgjmJnW76qe5WRcISE7NSNI/MpJU\n\tqStG/ZCokN5vkecmi9rjQBzJSLC02CD98IXQAjON0tOnexWlxKMjtLsWKkYPKUIwVG3C\n\tUg== ", "From": "<pbhagavatula@marvell.com>", "To": "<jerinj@marvell.com>, Pavan Nikhilesh <pbhagavatula@marvell.com>", "CC": "<dev@dpdk.org>", "Date": "Sun, 2 Jun 2019 00:23:41 +0530", "Message-ID": "<20190601185355.370-32-pbhagavatula@marvell.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20190601185355.370-1-pbhagavatula@marvell.com>", "References": "<20190601185355.370-1-pbhagavatula@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:, ,\n\tdefinitions=2019-06-01_13:, , signatures=0", "Subject": "[dpdk-dev] [PATCH 31/44] event/octeontx2: add devargs to disable NPA", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Pavan Nikhilesh <pbhagavatula@marvell.com>\n\nIf the chunks are allocated from NPA then TIM can automatically free\nthem when traversing the list of chunks.\nAdd devargs to disable NPA and use software mempool to manage chunks.\nExample:\n\n\t--dev \"0002:0e:00.0,tim_disable_npa=1\"\n\nSigned-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>\n---\n drivers/event/octeontx2/otx2_tim_evdev.c | 81 +++++++++++++++++-------\n drivers/event/octeontx2/otx2_tim_evdev.h | 3 +\n 2 files changed, 61 insertions(+), 23 deletions(-)", "diff": "diff --git a/drivers/event/octeontx2/otx2_tim_evdev.c b/drivers/event/octeontx2/otx2_tim_evdev.c\nindex 772cb0c75..9cceafd77 100644\n--- a/drivers/event/octeontx2/otx2_tim_evdev.c\n+++ b/drivers/event/octeontx2/otx2_tim_evdev.c\n@@ -2,6 +2,7 @@\n * Copyright(C) 2019 Marvell International Ltd.\n */\n \n+#include <rte_kvargs.h>\n #include <rte_malloc.h>\n #include <rte_mbuf_pool_ops.h>\n \n@@ -77,33 +78,45 @@ tim_chnk_pool_create(struct otx2_tim_ring *tim_ring,\n \tif (cache_sz > RTE_MEMPOOL_CACHE_MAX_SIZE)\n \t\tcache_sz = RTE_MEMPOOL_CACHE_MAX_SIZE;\n \n-\t/* NPA need not have cache as free is not visible to SW */\n-\ttim_ring->chunk_pool = rte_mempool_create_empty(pool_name,\n-\t\t\t\t\t\t\ttim_ring->nb_chunks,\n-\t\t\t\t\t\t\ttim_ring->chunk_sz,\n-\t\t\t\t\t\t\t0, 0, rte_socket_id(),\n-\t\t\t\t\t\t\tmp_flags);\n+\tif (!tim_ring->disable_npa) {\n+\t\t/* NPA need not have cache as free is not visible to SW */\n+\t\ttim_ring->chunk_pool = rte_mempool_create_empty(pool_name,\n+\t\t\t\ttim_ring->nb_chunks, tim_ring->chunk_sz,\n+\t\t\t\t0, 0, rte_socket_id(), mp_flags);\n \n-\tif (tim_ring->chunk_pool == NULL) {\n-\t\totx2_err(\"Unable to create chunkpool.\");\n-\t\treturn -ENOMEM;\n-\t}\n+\t\tif (tim_ring->chunk_pool == NULL) {\n+\t\t\totx2_err(\"Unable to create chunkpool.\");\n+\t\t\treturn -ENOMEM;\n+\t\t}\n \n-\trc = rte_mempool_set_ops_byname(tim_ring->chunk_pool,\n-\t\t\t\t\trte_mbuf_platform_mempool_ops(), NULL);\n-\tif (rc < 0) {\n-\t\totx2_err(\"Unable to set chunkpool ops\");\n-\t\tgoto free;\n-\t}\n+\t\trc = rte_mempool_set_ops_byname(tim_ring->chunk_pool,\n+\t\t\t\t\t\trte_mbuf_platform_mempool_ops(),\n+\t\t\t\t\t\tNULL);\n+\t\tif (rc < 0) {\n+\t\t\totx2_err(\"Unable to set chunkpool ops\");\n+\t\t\tgoto free;\n+\t\t}\n \n-\trc = rte_mempool_populate_default(tim_ring->chunk_pool);\n-\tif (rc < 0) {\n-\t\totx2_err(\"Unable to set populate chunkpool.\");\n-\t\tgoto free;\n+\t\trc = rte_mempool_populate_default(tim_ring->chunk_pool);\n+\t\tif (rc < 0) {\n+\t\t\totx2_err(\"Unable to set populate chunkpool.\");\n+\t\t\tgoto free;\n+\t\t}\n+\t\ttim_ring->aura = npa_lf_aura_handle_to_aura(\n+\t\t\t\ttim_ring->chunk_pool->pool_id);\n+\t\ttim_ring->ena_dfb = 0;\n+\t} else {\n+\t\ttim_ring->chunk_pool = rte_mempool_create(pool_name,\n+\t\t\t\ttim_ring->nb_chunks, tim_ring->chunk_sz,\n+\t\t\t\tcache_sz, 0, NULL, NULL, NULL, NULL,\n+\t\t\t\trte_socket_id(),\n+\t\t\t\tmp_flags);\n+\t\tif (tim_ring->chunk_pool == NULL) {\n+\t\t\totx2_err(\"Unable to create chunkpool.\");\n+\t\t\treturn -ENOMEM;\n+\t\t}\n+\t\ttim_ring->ena_dfb = 1;\n \t}\n-\ttim_ring->aura = npa_lf_aura_handle_to_aura(\n-\t\t\t\t\t\ttim_ring->chunk_pool->pool_id);\n-\ttim_ring->ena_dfb = 0;\n \n \treturn 0;\n \n@@ -229,6 +242,8 @@ otx2_tim_ring_create(struct rte_event_timer_adapter *adptr)\n \ttim_ring->nb_bkts = (tim_ring->max_tout / tim_ring->tck_nsec);\n \ttim_ring->chunk_sz = OTX2_TIM_RING_DEF_CHNK_SZ;\n \tnb_timers = rcfg->nb_timers;\n+\ttim_ring->disable_npa = dev->disable_npa;\n+\n \ttim_ring->nb_chunks = nb_timers / OTX2_TIM_NB_CNK_SLOTS(\n \t\t\t\t\t\t\ttim_ring->chunk_sz);\n \ttim_ring->nb_chunk_slots = OTX2_TIM_NB_CNK_SLOTS(tim_ring->chunk_sz);\n@@ -339,6 +354,24 @@ otx2_tim_caps_get(const struct rte_eventdev *evdev, uint64_t flags,\n \treturn 0;\n }\n \n+#define OTX2_TIM_DISABLE_NPA\t\"tim_disable_npa\"\n+\n+static void\n+tim_parse_devargs(struct rte_devargs *devargs, struct otx2_tim_evdev *dev)\n+{\n+\tstruct rte_kvargs *kvlist;\n+\n+\tif (devargs == NULL)\n+\t\treturn;\n+\n+\tkvlist = rte_kvargs_parse(devargs->args, NULL);\n+\tif (kvlist == NULL)\n+\t\treturn;\n+\n+\trte_kvargs_process(kvlist, OTX2_TIM_DISABLE_NPA,\n+\t\t\t &parse_kvargs_flag, &dev->disable_npa);\n+}\n+\n void\n otx2_tim_init(struct rte_pci_device *pci_dev, struct otx2_dev *cmn_dev)\n {\n@@ -364,6 +397,8 @@ otx2_tim_init(struct rte_pci_device *pci_dev, struct otx2_dev *cmn_dev)\n \tdev->mbox = cmn_dev->mbox;\n \tdev->bar2 = cmn_dev->bar2;\n \n+\ttim_parse_devargs(pci_dev->device.devargs, dev);\n+\n \totx2_mbox_alloc_msg_free_rsrc_cnt(dev->mbox);\n \trc = otx2_mbox_process_msg(dev->mbox, (void *)&rsrc_cnt);\n \tif (rc < 0) {\ndiff --git a/drivers/event/octeontx2/otx2_tim_evdev.h b/drivers/event/octeontx2/otx2_tim_evdev.h\nindex 3c0b7a5e0..e4b8cd4ce 100644\n--- a/drivers/event/octeontx2/otx2_tim_evdev.h\n+++ b/drivers/event/octeontx2/otx2_tim_evdev.h\n@@ -55,6 +55,8 @@ struct otx2_tim_evdev {\n \tstruct otx2_mbox *mbox;\n \tuint16_t nb_rings;\n \tuintptr_t bar2;\n+\t/* Dev args */\n+\tuint8_t disable_npa;\n };\n \n struct otx2_tim_ring {\n@@ -65,6 +67,7 @@ struct otx2_tim_ring {\n \tstruct rte_mempool *chunk_pool;\n \tuint64_t tck_int;\n \tuint8_t prod_type_sp;\n+\tuint8_t disable_npa;\n \tuint8_t optimized;\n \tuint8_t ena_dfb;\n \tuint16_t ring_id;\n", "prefixes": [ "31/44" ] }