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GET /api/patches/54038/?format=api
{ "id": 54038, "url": "http://patches.dpdk.org/api/patches/54038/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20190601185355.370-27-pbhagavatula@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20190601185355.370-27-pbhagavatula@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20190601185355.370-27-pbhagavatula@marvell.com", "date": "2019-06-01T18:53:36", "name": "[26/44] doc: add Marvell OCTEON TX2 event device documentation", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "26aff83e85cf0ef83796e2da76bddf0233e296a1", "submitter": { "id": 1183, "url": "http://patches.dpdk.org/api/people/1183/?format=api", "name": "Pavan Nikhilesh Bhagavatula", "email": "pbhagavatula@marvell.com" }, "delegate": { "id": 310, "url": "http://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20190601185355.370-27-pbhagavatula@marvell.com/mbox/", "series": [ { "id": 4847, "url": "http://patches.dpdk.org/api/series/4847/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=4847", "date": "2019-06-01T18:53:10", "name": "OCTEON TX2 event device driver", "version": 1, "mbox": "http://patches.dpdk.org/series/4847/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/54038/comments/", "check": "fail", "checks": "http://patches.dpdk.org/api/patches/54038/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 022091B9FD;\n\tSat, 1 Jun 2019 20:56:55 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n\t[67.231.156.173]) by dpdk.org (Postfix) with ESMTP id AB46B1B9AB\n\tfor <dev@dpdk.org>; Sat, 1 Jun 2019 20:56:06 +0200 (CEST)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n\tby mx0b-0016f401.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id\n\tx51It9nl029954; Sat, 1 Jun 2019 11:56:06 -0700", "from sc-exch02.marvell.com ([199.233.58.182])\n\tby mx0b-0016f401.pphosted.com with ESMTP id 2survk12fr-1\n\t(version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); \n\tSat, 01 Jun 2019 11:56:06 -0700", "from SC-EXCH01.marvell.com (10.93.176.81) by SC-EXCH02.marvell.com\n\t(10.93.176.82) with Microsoft SMTP Server (TLS) id 15.0.1367.3;\n\tSat, 1 Jun 2019 11:56:04 -0700", "from maili.marvell.com (10.93.176.43) by SC-EXCH01.marvell.com\n\t(10.93.176.81) with Microsoft SMTP Server id 15.0.1367.3 via Frontend\n\tTransport; Sat, 1 Jun 2019 11:56:04 -0700", "from BG-LT7430.marvell.com (unknown [10.28.17.28])\n\tby maili.marvell.com (Postfix) with ESMTP id F02F63F704B;\n\tSat, 1 Jun 2019 11:56:01 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n\th=from : to : cc :\n\tsubject : date : message-id : in-reply-to : references : mime-version\n\t: content-transfer-encoding : content-type; s=pfpt0818;\n\tbh=cXuMtjuI+XGDrwgiGp9Crspwqn6/796l0UbO2WDjxVU=;\n\tb=YPrcGZHa4LpS8FywNjCO3ZHgIxspf64cVg/aViVbNv6t3Lv2as+ob62GjyEG6rin1Af7\n\tLeMiyWu9iLh/iOeX8EuCvJxyKhMkNI3lTVcUEQOluFXXrO5A3b/jwOV5BkZMyZOinr1W\n\tP1+nnRUKzffBtwOYZ9x4heG15QDZmyjFdoi6OG3j2OlMzKGE0qXbIqYXHatC72lgcZI/\n\tmss1h1ha70kq1vmpx10EYxFmrTRjoeGbQh6OIX+vBEVPjsp3pRhZmWH8x6oDtKUJ4oa9\n\tZ/iTp2imQQp3IrbewqQAsxwe8EtUlMo2u8qTsndqu+ndKTJARNUsMIA3PYUqgeYd61hh\n\tSg== ", "From": "<pbhagavatula@marvell.com>", "To": "<jerinj@marvell.com>, John McNamara <john.mcnamara@intel.com>, \"Marko\n\tKovacevic\" <marko.kovacevic@intel.com>, Pavan Nikhilesh\n\t<pbhagavatula@marvell.com>, Nithin Dabilpuram <ndabilpuram@marvell.com>, \n\tVamsi Attunuru <vattunuru@marvell.com>", "CC": "<dev@dpdk.org>, Thomas Monjalon <thomas@monjalon.net>", "Date": "Sun, 2 Jun 2019 00:23:36 +0530", "Message-ID": "<20190601185355.370-27-pbhagavatula@marvell.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20190601185355.370-1-pbhagavatula@marvell.com>", "References": "<20190601185355.370-1-pbhagavatula@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:, ,\n\tdefinitions=2019-06-01_13:, , signatures=0", "Subject": "[dpdk-dev] [PATCH 26/44] doc: add Marvell OCTEON TX2 event device\n\tdocumentation", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Pavan Nikhilesh <pbhagavatula@marvell.com>\n\nAdd Marvell OCTEON TX2 event device documentation.\n\nThis patch also updates the MAINTAINERS file and\nupdates shared library versions in release_19_08.rst.\n\nCc: John McNamara <john.mcnamara@intel.com>\nCc: Thomas Monjalon <thomas@monjalon.net>\n\nSigned-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>\n---\n doc/guides/eventdevs/index.rst | 1 +\n doc/guides/eventdevs/octeontx2.rst | 104 +++++++++++++++++++++++++\n doc/guides/platform/octeontx2.rst | 3 +\n doc/guides/rel_notes/release_19_08.rst | 1 +\n 4 files changed, 109 insertions(+)\n create mode 100644 doc/guides/eventdevs/octeontx2.rst\n\n--\n2.21.0", "diff": "diff --git a/doc/guides/eventdevs/index.rst b/doc/guides/eventdevs/index.rst\nindex f7382dc8a..570905b81 100644\n--- a/doc/guides/eventdevs/index.rst\n+++ b/doc/guides/eventdevs/index.rst\n@@ -16,4 +16,5 @@ application trough the eventdev API.\n dsw\n sw\n octeontx\n+ octeontx2\n opdl\ndiff --git a/doc/guides/eventdevs/octeontx2.rst b/doc/guides/eventdevs/octeontx2.rst\nnew file mode 100644\nindex 000000000..928251aa6\n--- /dev/null\n+++ b/doc/guides/eventdevs/octeontx2.rst\n@@ -0,0 +1,104 @@\n+.. SPDX-License-Identifier: BSD-3-Clause\n+ Copyright(c) 2019 Marvell International Ltd.\n+\n+OCTEON TX2 SSO Eventdev Driver\n+===============================\n+\n+The OCTEON TX2 SSO PMD (**librte_pmd_octeontx2_event**) provides poll mode\n+eventdev driver support for the inbuilt event device found in the **Marvell OCTEON TX2**\n+SoC family.\n+\n+More information about OCTEON TX2 SoC can be found at `Marvell Official Website\n+<https://www.marvell.com/embedded-processors/infrastructure-processors/>`_.\n+\n+Features\n+--------\n+\n+Features of the OCTEON TX2 SSO PMD are:\n+\n+- 256 Event queues\n+- 26 (dual) and 52 (single) Event ports\n+- HW event scheduler\n+- Supports 1M flows per event queue\n+- Flow based event pipelining\n+- Flow pinning support in flow based event pipelining\n+- Queue based event pipelining\n+- Supports ATOMIC, ORDERED, PARALLEL schedule types per flow\n+- Event scheduling QoS based on event queue priority\n+- Open system with configurable amount of outstanding events limited only by\n+ DRAM\n+- HW accelerated dequeue timeout support to enable power management\n+\n+Prerequisites and Compilation procedure\n+---------------------------------------\n+\n+ See :doc:`../platform/octeontx2` for setup information.\n+\n+Pre-Installation Configuration\n+------------------------------\n+\n+Compile time Config Options\n+~~~~~~~~~~~~~~~~~~~~~~~~~~~\n+\n+The following option can be modified in the ``config`` file.\n+\n+- ``CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_EVENTDEV`` (default ``y``)\n+\n+ Toggle compilation of the ``librte_pmd_octeontx2_event`` driver.\n+\n+Runtime Config Options\n+~~~~~~~~~~~~~~~~~~~~~~\n+\n+- ``Maximum number of in-flight events`` (default ``8192``)\n+\n+ In **Marvell OCTEON TX2** the max number of in-flight events are only limited\n+ by DRAM size, the ``xae_cnt`` devargs parameter is introduced to provide\n+ upper limit for in-flight events.\n+ For example::\n+\n+ --dev \"0002:0e:00.0,xae_cnt=16384\"\n+\n+- ``Force legacy mode``\n+\n+ The ``single_ws`` devargs parameter is introduced to force legacy mode i.e\n+ single workslot mode in SSO and disable the default dual workslot mode.\n+ For example::\n+\n+ --dev \"0002:0e:00.0,single_ws=1\"\n+\n+- ``Event Group QoS support``\n+\n+ SSO GGRPs i.e. queue uses DRAM & SRAM buffers to hold in-flight\n+ events. By default the buffers are assigned to the SSO GGRPs to\n+ satisfy minimum HW requirements. SSO is free to assign the remaining\n+ buffers to GGRPs based on a preconfigured threshold.\n+ We can control the QoS of SSO GGRP by modifying the above mentioned\n+ thresholds. GGRPs that have higher importance can be assigned higher\n+ thresholds than the rest. The dictionary format is as follows\n+ [Qx-XAQ-TAQ-IAQ][Qz-XAQ-TAQ-IAQ] expressed in percentages, 0 represents\n+ default.\n+ For example::\n+\n+ --dev \"0002:0e:00.0,qos=[1-50-50-50]\"\n+\n+- ``Selftest``\n+\n+ The functionality of OCTEON TX2 eventdev can be verified using this option,\n+ various unit and functional tests are run to verify the sanity.\n+ The tests are run once the vdev creation is successfully complete.\n+ For example::\n+\n+ --dev \"0002:0e:00.0,selftest=1\"\n+\n+Debugging Options\n+~~~~~~~~~~~~~~~~~\n+\n+.. _table_octeontx2_event_debug_options:\n+\n+.. table:: OCTEON TX2 event device debug options\n+\n+ +---+------------+-------------------------------------------------------+\n+ | # | Component | EAL log command |\n+ +===+============+=======================================================+\n+ | 1 | SSO | --log-level='pmd\\.event\\.octeontx2,8' |\n+ +---+------------+-------------------------------------------------------+\ndiff --git a/doc/guides/platform/octeontx2.rst b/doc/guides/platform/octeontx2.rst\nindex c9ea45647..fbf1193e7 100644\n--- a/doc/guides/platform/octeontx2.rst\n+++ b/doc/guides/platform/octeontx2.rst\n@@ -101,6 +101,9 @@ This section lists dataplane H/W block(s) available in OCTEON TX2 SoC.\n #. **Mempool Driver**\n See :doc:`../mempool/octeontx2` for NPA mempool driver information.\n\n+#. **Event Device Driver**\n+ See :doc:`../eventdevs/octeontx2` for SSO event device driver information.\n+\n Procedure to Setup Platform\n ---------------------------\n\ndiff --git a/doc/guides/rel_notes/release_19_08.rst b/doc/guides/rel_notes/release_19_08.rst\nindex c8b22ff25..99d9828b0 100644\n--- a/doc/guides/rel_notes/release_19_08.rst\n+++ b/doc/guides/rel_notes/release_19_08.rst\n@@ -142,6 +142,7 @@ The libraries prepended with a plus sign were incremented in this version.\n librte_efd.so.1\n librte_ethdev.so.12\n librte_eventdev.so.6\n+ + librte_pmd_octeontx2_event.so.1\n librte_flow_classify.so.1\n librte_gro.so.1\n librte_gso.so.1\n", "prefixes": [ "26/44" ] }