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GET /api/patches/54036/?format=api
{ "id": 54036, "url": "http://patches.dpdk.org/api/patches/54036/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20190601185355.370-24-pbhagavatula@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20190601185355.370-24-pbhagavatula@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20190601185355.370-24-pbhagavatula@marvell.com", "date": "2019-06-01T18:53:33", "name": "[23/44] event/octeontx2: add devargs to control SSO GGRP QoS", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "755a4c491073ac5759d73aea80669226c1a7aca9", "submitter": { "id": 1183, "url": "http://patches.dpdk.org/api/people/1183/?format=api", "name": "Pavan Nikhilesh Bhagavatula", "email": "pbhagavatula@marvell.com" }, "delegate": { "id": 310, "url": "http://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20190601185355.370-24-pbhagavatula@marvell.com/mbox/", "series": [ { "id": 4847, "url": "http://patches.dpdk.org/api/series/4847/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=4847", "date": "2019-06-01T18:53:10", "name": "OCTEON TX2 event device driver", "version": 1, "mbox": "http://patches.dpdk.org/series/4847/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/54036/comments/", "check": "fail", "checks": "http://patches.dpdk.org/api/patches/54036/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 1160F1B9F0;\n\tSat, 1 Jun 2019 20:56:43 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n\t[67.231.156.173]) by dpdk.org (Postfix) with ESMTP id 426391B974\n\tfor <dev@dpdk.org>; Sat, 1 Jun 2019 20:55:57 +0200 (CEST)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n\tby mx0b-0016f401.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id\n\tx51IsiFY029446 for <dev@dpdk.org>; Sat, 1 Jun 2019 11:55:56 -0700", "from sc-exch02.marvell.com ([199.233.58.182])\n\tby mx0b-0016f401.pphosted.com with ESMTP id 2survk12ex-1\n\t(version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n\tfor <dev@dpdk.org>; Sat, 01 Jun 2019 11:55:56 -0700", "from SC-EXCH03.marvell.com (10.93.176.83) by SC-EXCH02.marvell.com\n\t(10.93.176.82) with Microsoft SMTP Server (TLS) id 15.0.1367.3;\n\tSat, 1 Jun 2019 11:55:55 -0700", "from maili.marvell.com (10.93.176.43) by SC-EXCH03.marvell.com\n\t(10.93.176.83) with Microsoft SMTP Server id 15.0.1367.3 via Frontend\n\tTransport; Sat, 1 Jun 2019 11:55:55 -0700", "from BG-LT7430.marvell.com (unknown [10.28.17.28])\n\tby maili.marvell.com (Postfix) with ESMTP id 08F713F7040;\n\tSat, 1 Jun 2019 11:55:53 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n\th=from : to : cc :\n\tsubject : date : message-id : in-reply-to : references : mime-version\n\t: content-transfer-encoding : content-type; s=pfpt0818;\n\tbh=AX84tgj1DKoI6JmEp7E+4GS6uYuskyF1VqYmU757X0w=;\n\tb=nUrpecSlErXRJ6s2FHuvISSGxFKKM6ClJm7fwIaa1kIrb7wEnfVb5cvkP/LOQTYJ86vz\n\t/QLrMShE1dTvlLA3PIRsrozA5Zrj1u/ZvdwqOrffJco3LEjW2+ySbhG0t9QenQxQYT2v\n\tQr3WHFLFoPXHpS8JRQLFkBwsCVenWbfC9PRm9p7KT1vd5YoD3hw4BGh0Qg0TFurGiaiI\n\t8vDLMAtDsf3GyTFqxvH/xkTPfYIUpnjC46ku8GsT7w5uvsUhanvdGhoHrwlQa9QZ2aoX\n\tLuB9o1S+46CNaasEq6+4iLl/YXcJpuPKngV+o4gPYv0S1Vedz3HSnGRIlCzR5g4j1b4l\n\tXg== ", "From": "<pbhagavatula@marvell.com>", "To": "<jerinj@marvell.com>, Pavan Nikhilesh <pbhagavatula@marvell.com>", "CC": "<dev@dpdk.org>", "Date": "Sun, 2 Jun 2019 00:23:33 +0530", "Message-ID": "<20190601185355.370-24-pbhagavatula@marvell.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20190601185355.370-1-pbhagavatula@marvell.com>", "References": "<20190601185355.370-1-pbhagavatula@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:, ,\n\tdefinitions=2019-06-01_13:, , signatures=0", "Subject": "[dpdk-dev] [PATCH 23/44] event/octeontx2: add devargs to control\n\tSSO GGRP QoS", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Pavan Nikhilesh <pbhagavatula@marvell.com>\n\nSSO GGRPs i.e. queue uses DRAM & SRAM buffers to hold in-flight\nevents. By default the buffers are assigned to the SSO GGRPs to\nsatisfy minimum HW requirements. SSO is free to assign the remaining\nbuffers to GGRPs based on a preconfigured threshold.\nWe can control the QoS of SSO GGRP by modifying the above mentioned\nthresholds. GGRPs that have higher importance can be assigned higher\nthresholds than the rest.\n\nExample:\n\t--dev \"0002:0e:00.0,qos=[1-50-50-50]\" // [Qx-XAQ-TAQ-IAQ]\n\nQx -> Event queue Aka SSO GGRP.\nXAQ -> DRAM In-flights.\nTAQ & IAQ -> SRAM In-flights.\n\nThe values need to be expressed in terms of percentages, 0 represents\ndefault.\n\nSigned-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>\nSigned-off-by: Jerin Jacob <jerinj@marvell.com>\n---\n drivers/event/octeontx2/otx2_evdev.c | 104 ++++++++++++++++++++++++++-\n drivers/event/octeontx2/otx2_evdev.h | 9 +++\n 2 files changed, 112 insertions(+), 1 deletion(-)", "diff": "diff --git a/drivers/event/octeontx2/otx2_evdev.c b/drivers/event/octeontx2/otx2_evdev.c\nindex 51d1a45c6..438bfcb9f 100644\n--- a/drivers/event/octeontx2/otx2_evdev.c\n+++ b/drivers/event/octeontx2/otx2_evdev.c\n@@ -929,6 +929,34 @@ otx2_handle_event(void *arg, struct rte_event event)\n \t\t\t\tevent, event_dev->data->dev_stop_flush_arg);\n }\n \n+static void\n+sso_qos_cfg(struct rte_eventdev *event_dev)\n+{\n+\tstruct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);\n+\tstruct sso_grp_qos_cfg *req;\n+\tuint16_t i;\n+\n+\tfor (i = 0; i < dev->qos_queue_cnt; i++) {\n+\t\tuint8_t xaq_prcnt = dev->qos_parse_data[i].xaq_prcnt;\n+\t\tuint8_t iaq_prcnt = dev->qos_parse_data[i].iaq_prcnt;\n+\t\tuint8_t taq_prcnt = dev->qos_parse_data[i].taq_prcnt;\n+\n+\t\tif (dev->qos_parse_data[i].queue >= dev->nb_event_queues)\n+\t\t\tcontinue;\n+\n+\t\treq = otx2_mbox_alloc_msg_sso_grp_qos_config(dev->mbox);\n+\t\treq->xaq_limit = (dev->nb_xaq_cfg *\n+\t\t\t\t (xaq_prcnt ? xaq_prcnt : 100)) / 100;\n+\t\treq->taq_thr = (SSO_HWGRP_IAQ_MAX_THR_MASK *\n+\t\t\t\t(iaq_prcnt ? iaq_prcnt : 100)) / 100;\n+\t\treq->iaq_thr = (SSO_HWGRP_TAQ_MAX_THR_MASK *\n+\t\t\t\t(taq_prcnt ? taq_prcnt : 100)) / 100;\n+\t}\n+\n+\tif (dev->qos_queue_cnt)\n+\t\totx2_mbox_process(dev->mbox);\n+}\n+\n static void\n sso_cleanup(struct rte_eventdev *event_dev, uint8_t enable)\n {\n@@ -1000,6 +1028,7 @@ static int\n otx2_sso_start(struct rte_eventdev *event_dev)\n {\n \tsso_func_trace();\n+\tsso_qos_cfg(event_dev);\n \tsso_cleanup(event_dev, 1);\n \tsso_fastpath_fns_set(event_dev);\n \n@@ -1030,6 +1059,76 @@ static struct rte_eventdev_ops otx2_sso_ops = {\n \n #define OTX2_SSO_XAE_CNT\t\"xae_cnt\"\n #define OTX2_SSO_SINGLE_WS\t\"single_ws\"\n+#define OTX2_SSO_GGRP_QOS\t\"qos\"\n+\n+static void\n+parse_queue_param(char *value, void *opaque)\n+{\n+\tstruct otx2_sso_qos queue_qos = {0};\n+\tuint8_t *val = (uint8_t *)&queue_qos;\n+\tstruct otx2_sso_evdev *dev = opaque;\n+\tchar *tok = strtok(value, \"-\");\n+\n+\tif (!strlen(value))\n+\t\treturn;\n+\n+\twhile (tok != NULL) {\n+\t\t*val = atoi(tok);\n+\t\ttok = strtok(NULL, \"-\");\n+\t\tval++;\n+\t}\n+\n+\tif (val != (&queue_qos.iaq_prcnt + 1)) {\n+\t\totx2_err(\"Invalid QoS parameter expected [Qx-XAQ-TAQ-IAQ]\");\n+\t\treturn;\n+\t}\n+\n+\tdev->qos_queue_cnt++;\n+\tdev->qos_parse_data = rte_realloc(dev->qos_parse_data,\n+\t\t\t\t\t sizeof(struct otx2_sso_qos) *\n+\t\t\t\t\t dev->qos_queue_cnt, 0);\n+\tdev->qos_parse_data[dev->qos_queue_cnt - 1] = queue_qos;\n+}\n+\n+static void\n+parse_qos_list(const char *value, void *opaque)\n+{\n+\tchar *s = strdup(value);\n+\tchar *start = NULL;\n+\tchar *end = NULL;\n+\tchar *f = s;\n+\n+\twhile (*s) {\n+\t\tif (*s == '[')\n+\t\t\tstart = s;\n+\t\telse if (*s == ']')\n+\t\t\tend = s;\n+\n+\t\tif (start < end && *start) {\n+\t\t\t*end = 0;\n+\t\t\tparse_queue_param(start + 1, opaque);\n+\t\t\ts = end;\n+\t\t\tstart = end;\n+\t\t}\n+\t\ts++;\n+\t}\n+\n+\tfree(f);\n+}\n+\n+static int\n+parse_sso_kvargs_dict(const char *key, const char *value, void *opaque)\n+{\n+\tRTE_SET_USED(key);\n+\n+\t/* Dict format [Qx-XAQ-TAQ-IAQ][Qz-XAQ-TAQ-IAQ] use '-' cause ','\n+\t * isn't allowed. Everything is expressed in percentages, 0 represents\n+\t * default.\n+\t */\n+\tparse_qos_list(value, opaque);\n+\n+\treturn 0;\n+}\n \n static void\n sso_parse_devargs(struct otx2_sso_evdev *dev, struct rte_devargs *devargs)\n@@ -1047,6 +1146,8 @@ sso_parse_devargs(struct otx2_sso_evdev *dev, struct rte_devargs *devargs)\n \t\t\t &dev->xae_cnt);\n \trte_kvargs_process(kvlist, OTX2_SSO_SINGLE_WS, &parse_kvargs_flag,\n \t\t\t &single_ws);\n+\trte_kvargs_process(kvlist, OTX2_SSO_GGRP_QOS, &parse_sso_kvargs_dict,\n+\t\t\t dev);\n \n \tdev->dual_ws = !single_ws;\n \trte_kvargs_free(kvlist);\n@@ -1202,4 +1303,5 @@ RTE_PMD_REGISTER_PCI(event_octeontx2, pci_sso);\n RTE_PMD_REGISTER_PCI_TABLE(event_octeontx2, pci_sso_map);\n RTE_PMD_REGISTER_KMOD_DEP(event_octeontx2, \"vfio-pci\");\n RTE_PMD_REGISTER_PARAM_STRING(event_octeontx2, OTX2_SSO_XAE_CNT \"=<int>\"\n-\t\t\t OTX2_SSO_SINGLE_WS \"=1\");\n+\t\t\t OTX2_SSO_SINGLE_WS \"=1\"\n+\t\t\t OTX2_SSO_GGRP_QOS \"=<string>\");\ndiff --git a/drivers/event/octeontx2/otx2_evdev.h b/drivers/event/octeontx2/otx2_evdev.h\nindex 1a7a1b0d0..6b221f5d4 100644\n--- a/drivers/event/octeontx2/otx2_evdev.h\n+++ b/drivers/event/octeontx2/otx2_evdev.h\n@@ -89,6 +89,13 @@ enum {\n \tSSO_SYNC_EMPTY\n };\n \n+struct otx2_sso_qos {\n+\tuint8_t queue;\n+\tuint8_t xaq_prcnt;\n+\tuint8_t taq_prcnt;\n+\tuint8_t iaq_prcnt;\n+};\n+\n struct otx2_sso_evdev {\n \tOTX2_DEV; /* Base class */\n \tuint8_t max_event_queues;\n@@ -109,6 +116,8 @@ struct otx2_sso_evdev {\n \t/* Dev args */\n \tuint8_t dual_ws;\n \tuint32_t xae_cnt;\n+\tuint8_t qos_queue_cnt;\n+\tstruct otx2_sso_qos *qos_parse_data;\n \t/* HW const */\n \tuint32_t xae_waes;\n \tuint32_t xaq_buf_size;\n", "prefixes": [ "23/44" ] }