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GET /api/patches/54024/?format=api
http://patches.dpdk.org/api/patches/54024/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20190601185355.370-10-pbhagavatula@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20190601185355.370-10-pbhagavatula@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20190601185355.370-10-pbhagavatula@marvell.com", "date": "2019-06-01T18:53:19", "name": "[09/44] event/octeontx2: support linking queues to ports", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "606c5a5ddc2e9807f177b00d58dcf14eb088f9f2", "submitter": { "id": 1183, "url": "http://patches.dpdk.org/api/people/1183/?format=api", "name": "Pavan Nikhilesh Bhagavatula", "email": "pbhagavatula@marvell.com" }, "delegate": { "id": 310, "url": "http://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20190601185355.370-10-pbhagavatula@marvell.com/mbox/", "series": [ { "id": 4847, "url": "http://patches.dpdk.org/api/series/4847/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=4847", "date": "2019-06-01T18:53:10", "name": "OCTEON TX2 event device driver", "version": 1, "mbox": "http://patches.dpdk.org/series/4847/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/54024/comments/", "check": "fail", "checks": "http://patches.dpdk.org/api/patches/54024/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 94C961B9B6;\n\tSat, 1 Jun 2019 20:56:11 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n\t[67.231.156.173]) by dpdk.org (Postfix) with ESMTP id 20ECE1B947\n\tfor <dev@dpdk.org>; Sat, 1 Jun 2019 20:55:41 +0200 (CEST)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n\tby mx0b-0016f401.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id\n\tx51Itbrd030054 for <dev@dpdk.org>; Sat, 1 Jun 2019 11:55:40 -0700", "from sc-exch02.marvell.com ([199.233.58.182])\n\tby mx0b-0016f401.pphosted.com with ESMTP id 2survk12dg-6\n\t(version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n\tfor <dev@dpdk.org>; Sat, 01 Jun 2019 11:55:40 -0700", "from SC-EXCH03.marvell.com (10.93.176.83) by SC-EXCH02.marvell.com\n\t(10.93.176.82) with Microsoft SMTP Server (TLS) id 15.0.1367.3;\n\tSat, 1 Jun 2019 11:55:37 -0700", "from maili.marvell.com (10.93.176.43) by SC-EXCH03.marvell.com\n\t(10.93.176.83) with Microsoft SMTP Server id 15.0.1367.3 via Frontend\n\tTransport; Sat, 1 Jun 2019 11:55:37 -0700", "from BG-LT7430.marvell.com (unknown [10.28.17.28])\n\tby maili.marvell.com (Postfix) with ESMTP id 6E4BC3F7129;\n\tSat, 1 Jun 2019 11:55:17 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n\th=from : to : cc :\n\tsubject : date : message-id : in-reply-to : references : mime-version\n\t: content-transfer-encoding : content-type; s=pfpt0818;\n\tbh=ahpRi9fGIWyJ190rzyTCbayQvi4ncvlAKDrizzwvnb8=;\n\tb=fX3gLEtKIx1G1JEL/3RQvdVCeJgimsYymyM8wxVmYTAu1WV/zeAcYMfjPAzrmmldYSmm\n\t/Grdiw5eVEcYC3/LAtsLtqyDGCgwMxtJj4x8IfW7vPK2ikwV3eEDergPLwanwUNbXtlN\n\tUfI4Nq6dak/PYtOpPX8rR1WE9QG1iHWfDsHm7Si3a+za5AkMC058Su9xdRxazCdTHUXl\n\t0KL9O62+HKphDc1tx3DMK/+Q6X+j/xUo6Afcf9w7p3hbV/HexE+oeUaQnDGE2KwTxdL1\n\tQGRnQ72U6bxolyM1d4PP3d7hR7sEdKQoByb5cwEcC1crp4RFKAOluZz+/wf0i6y2jK2n\n\t+w== ", "From": "<pbhagavatula@marvell.com>", "To": "<jerinj@marvell.com>, Pavan Nikhilesh <pbhagavatula@marvell.com>", "CC": "<dev@dpdk.org>", "Date": "Sun, 2 Jun 2019 00:23:19 +0530", "Message-ID": "<20190601185355.370-10-pbhagavatula@marvell.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20190601185355.370-1-pbhagavatula@marvell.com>", "References": "<20190601185355.370-1-pbhagavatula@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:, ,\n\tdefinitions=2019-06-01_13:, , signatures=0", "Subject": "[dpdk-dev] [PATCH 09/44] event/octeontx2: support linking queues to\n\tports", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Pavan Nikhilesh <pbhagavatula@marvell.com>\n\nLinks between queues and ports are controlled by setting/clearing GGRP\nmembership in SSOW_LF_GWS_GRPMSK_CHG.\n\nSigned-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>\n---\n drivers/event/octeontx2/otx2_evdev.c | 73 ++++++++++++++++++++++++++++\n 1 file changed, 73 insertions(+)", "diff": "diff --git a/drivers/event/octeontx2/otx2_evdev.c b/drivers/event/octeontx2/otx2_evdev.c\nindex baae47054..7875a9ac5 100644\n--- a/drivers/event/octeontx2/otx2_evdev.c\n+++ b/drivers/event/octeontx2/otx2_evdev.c\n@@ -39,6 +39,60 @@ otx2_sso_info_get(struct rte_eventdev *event_dev,\n \t\t\t\t\tRTE_EVENT_DEV_CAP_NONSEQ_MODE;\n }\n \n+static void\n+sso_port_link_modify(struct otx2_ssogws *ws, uint8_t queue, uint8_t enable)\n+{\n+\tuintptr_t base = OTX2_SSOW_GET_BASE_ADDR(ws->getwrk_op);\n+\tuint64_t val;\n+\n+\tval = queue;\n+\tval |= 0ULL << 12; /* SET 0 */\n+\tval |= 0x8000800080000000; /* Dont modify rest of the masks */\n+\tval |= (uint64_t)enable << 14; /* Enable/Disable Membership. */\n+\n+\totx2_write64(val, base + SSOW_LF_GWS_GRPMSK_CHG);\n+}\n+\n+static int\n+otx2_sso_port_link(struct rte_eventdev *event_dev, void *port,\n+\t\t const uint8_t queues[], const uint8_t priorities[],\n+\t\t uint16_t nb_links)\n+{\n+\tuint8_t port_id = 0;\n+\tuint16_t link;\n+\n+\tRTE_SET_USED(event_dev);\n+\tRTE_SET_USED(priorities);\n+\tfor (link = 0; link < nb_links; link++) {\n+\t\tstruct otx2_ssogws *ws = port;\n+\n+\t\tport_id = ws->port;\n+\t\tsso_port_link_modify(ws, queues[link], true);\n+\t}\n+\tsso_func_trace(\"port=%d nb_links=%d\", port_id, nb_links);\n+\n+\treturn (int)nb_links;\n+}\n+\n+static int\n+otx2_sso_port_unlink(struct rte_eventdev *event_dev, void *port,\n+\t\t uint8_t queues[], uint16_t nb_unlinks)\n+{\n+\tuint8_t port_id = 0;\n+\tuint16_t unlink;\n+\n+\tRTE_SET_USED(event_dev);\n+\tfor (unlink = 0; unlink < nb_unlinks; unlink++) {\n+\t\tstruct otx2_ssogws *ws = port;\n+\n+\t\tport_id = ws->port;\n+\t\tsso_port_link_modify(ws, queues[unlink], false);\n+\t}\n+\tsso_func_trace(\"port=%d nb_unlinks=%d\", port_id, nb_unlinks);\n+\n+\treturn (int)nb_unlinks;\n+}\n+\n static int\n sso_hw_lf_cfg(struct otx2_mbox *mbox, enum otx2_sso_lf_type type,\n \t uint16_t nb_lf, uint8_t attach)\n@@ -157,6 +211,21 @@ otx2_sso_queue_release(struct rte_eventdev *event_dev, uint8_t queue_id)\n \tRTE_SET_USED(queue_id);\n }\n \n+static void\n+sso_clr_links(const struct rte_eventdev *event_dev)\n+{\n+\tstruct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);\n+\tint i, j;\n+\n+\tfor (i = 0; i < dev->nb_event_ports; i++) {\n+\t\tstruct otx2_ssogws *ws;\n+\n+\t\tws = event_dev->data->ports[i];\n+\t\tfor (j = 0; j < dev->nb_event_queues; j++)\n+\t\t\tsso_port_link_modify(ws, j, false);\n+\t}\n+}\n+\n static void\n sso_set_port_ops(struct otx2_ssogws *ws, uintptr_t base)\n {\n@@ -445,6 +514,8 @@ otx2_sso_configure(const struct rte_eventdev *event_dev)\n \t\tgoto teardown_hwggrp;\n \t}\n \n+\t/* Clear any prior port-queue mapping. */\n+\tsso_clr_links(event_dev);\n \trc = sso_ggrp_alloc_xaq(dev);\n \tif (rc < 0) {\n \t\totx2_err(\"failed to alloc xaq to ggrp %d\", rc);\n@@ -569,6 +640,8 @@ static struct rte_eventdev_ops otx2_sso_ops = {\n \t.port_def_conf = otx2_sso_port_def_conf,\n \t.port_setup = otx2_sso_port_setup,\n \t.port_release = otx2_sso_port_release,\n+\t.port_link = otx2_sso_port_link,\n+\t.port_unlink = otx2_sso_port_unlink,\n };\n \n #define OTX2_SSO_XAE_CNT\t\"xae_cnt\"\n", "prefixes": [ "09/44" ] }{ "id": 54024, "url": "