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GET /api/patches/54021/?format=api
{ "id": 54021, "url": "http://patches.dpdk.org/api/patches/54021/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20190601185355.370-12-pbhagavatula@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20190601185355.370-12-pbhagavatula@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20190601185355.370-12-pbhagavatula@marvell.com", "date": "2019-06-01T18:53:21", "name": "[11/44] event/octeontx2: add SSO GWS and GGRP IRQ handlers", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "09ad0ea61238251c8574410f4201e782de5dcab6", "submitter": { "id": 1183, "url": "http://patches.dpdk.org/api/people/1183/?format=api", "name": "Pavan Nikhilesh Bhagavatula", "email": "pbhagavatula@marvell.com" }, "delegate": { "id": 310, "url": "http://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20190601185355.370-12-pbhagavatula@marvell.com/mbox/", "series": [ { "id": 4847, "url": "http://patches.dpdk.org/api/series/4847/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=4847", "date": "2019-06-01T18:53:10", "name": "OCTEON TX2 event device driver", "version": 1, "mbox": "http://patches.dpdk.org/series/4847/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/54021/comments/", "check": "fail", "checks": "http://patches.dpdk.org/api/patches/54021/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 7EC301B9A8;\n\tSat, 1 Jun 2019 20:56:06 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n\t[67.231.156.173]) by dpdk.org (Postfix) with ESMTP id DDA7F2F4F\n\tfor <dev@dpdk.org>; Sat, 1 Jun 2019 20:55:40 +0200 (CEST)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n\tby mx0b-0016f401.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id\n\tx51Itbrc030054 for <dev@dpdk.org>; Sat, 1 Jun 2019 11:55:40 -0700", "from sc-exch01.marvell.com ([199.233.58.181])\n\tby mx0b-0016f401.pphosted.com with ESMTP id 2survk12dh-5\n\t(version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n\tfor <dev@dpdk.org>; Sat, 01 Jun 2019 11:55:40 -0700", "from SC-EXCH01.marvell.com (10.93.176.81) by SC-EXCH01.marvell.com\n\t(10.93.176.81) with Microsoft SMTP Server (TLS) id 15.0.1367.3;\n\tSat, 1 Jun 2019 11:55:37 -0700", "from maili.marvell.com (10.93.176.43) by SC-EXCH01.marvell.com\n\t(10.93.176.81) with Microsoft SMTP Server id 15.0.1367.3 via Frontend\n\tTransport; Sat, 1 Jun 2019 11:55:37 -0700", "from BG-LT7430.marvell.com (unknown [10.28.17.28])\n\tby maili.marvell.com (Postfix) with ESMTP id A47E23F7132;\n\tSat, 1 Jun 2019 11:55:22 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n\th=from : to : cc :\n\tsubject : date : message-id : in-reply-to : references : mime-version\n\t: content-transfer-encoding : content-type; s=pfpt0818;\n\tbh=bgpRd0PLzXhsRrtQGWq3mlLAh4J7VkTWa3YkLG6+nbo=;\n\tb=FDrNaBbZxs6S0PMTmg6MN/QNFMJANRp1hklT7mC2xlsNeL+Nfa9hMK9jYAx/Z8Am0etE\n\tbKdc5PVVHJcUc9qgMz643L/k3AvrUUG0qPUSIK+Aexwizqs0uXt/L/+enwCgS22R2TWF\n\ty0ov6nROxDCvMb7Zlre0GzZMRlH70eGgCP6Fmr2PizfwrIBhcVe8PyNy17BS2G+q9OYh\n\tavYzxfAgex1nFIpFClMIqLNDQd7DcbpPJZ4jPi8sYTRX4Hek37ZIKMKZDOXy+YbkanLL\n\tfyQoMxsKH+MD1AkYRgyQcVlHBOn9tFjqvpBTHqGwbZEaqhtyUMfboy74pS8XHjVWHvj1\n\tVQ== ", "From": "<pbhagavatula@marvell.com>", "To": "<jerinj@marvell.com>, Pavan Nikhilesh <pbhagavatula@marvell.com>", "CC": "<dev@dpdk.org>", "Date": "Sun, 2 Jun 2019 00:23:21 +0530", "Message-ID": "<20190601185355.370-12-pbhagavatula@marvell.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20190601185355.370-1-pbhagavatula@marvell.com>", "References": "<20190601185355.370-1-pbhagavatula@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:, ,\n\tdefinitions=2019-06-01_13:, , signatures=0", "Subject": "[dpdk-dev] [PATCH 11/44] event/octeontx2: add SSO GWS and GGRP IRQ\n\thandlers", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Pavan Nikhilesh <pbhagavatula@marvell.com>\n\nRegister and implement SSO GWS and GGRP IRQ handlers for error\ninterrupts.\n\nSigned-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>\nSigned-off-by: Jerin Jacob <jerinj@marvell.com>\n---\n drivers/event/octeontx2/Makefile | 1 +\n drivers/event/octeontx2/meson.build | 4 +-\n drivers/event/octeontx2/otx2_evdev.c | 38 +++++\n drivers/event/octeontx2/otx2_evdev.h | 6 +\n drivers/event/octeontx2/otx2_evdev_irq.c | 179 +++++++++++++++++++++++\n 5 files changed, 227 insertions(+), 1 deletion(-)\n create mode 100644 drivers/event/octeontx2/otx2_evdev_irq.c", "diff": "diff --git a/drivers/event/octeontx2/Makefile b/drivers/event/octeontx2/Makefile\nindex 58853e1b9..4f09c1fc8 100644\n--- a/drivers/event/octeontx2/Makefile\n+++ b/drivers/event/octeontx2/Makefile\n@@ -31,6 +31,7 @@ LIBABIVER := 1\n #\n \n SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_EVENTDEV) += otx2_evdev.c\n+SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_EVENTDEV) += otx2_evdev_irq.c\n \n LDLIBS += -lrte_eal -lrte_bus_pci -lrte_pci -lrte_kvargs\n LDLIBS += -lrte_mempool -lrte_eventdev -lrte_mbuf\ndiff --git a/drivers/event/octeontx2/meson.build b/drivers/event/octeontx2/meson.build\nindex 3fc96421d..5aa8113bd 100644\n--- a/drivers/event/octeontx2/meson.build\n+++ b/drivers/event/octeontx2/meson.build\n@@ -2,7 +2,9 @@\n # Copyright(C) 2019 Marvell International Ltd.\n #\n \n-sources = files('otx2_evdev.c')\n+sources = files('otx2_evdev.c',\n+\t\t'otx2_evdev_irq.c',\n+\t\t)\n \n allow_experimental_apis = true\n \ndiff --git a/drivers/event/octeontx2/otx2_evdev.c b/drivers/event/octeontx2/otx2_evdev.c\nindex 485552c44..c8623b502 100644\n--- a/drivers/event/octeontx2/otx2_evdev.c\n+++ b/drivers/event/octeontx2/otx2_evdev.c\n@@ -13,6 +13,29 @@\n #include <rte_pci.h>\n \n #include \"otx2_evdev.h\"\n+#include \"otx2_irq.h\"\n+\n+static inline int\n+sso_get_msix_offsets(const struct rte_eventdev *event_dev)\n+{\n+\tstruct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);\n+\tuint8_t nb_ports = dev->nb_event_ports;\n+\tstruct otx2_mbox *mbox = dev->mbox;\n+\tstruct msix_offset_rsp *msix_rsp;\n+\tint i, rc;\n+\n+\t/* Get SSO and SSOW MSIX vector offsets */\n+\totx2_mbox_alloc_msg_msix_offset(mbox);\n+\trc = otx2_mbox_process_msg(mbox, (void *)&msix_rsp);\n+\n+\tfor (i = 0; i < nb_ports; i++)\n+\t\tdev->ssow_msixoff[i] = msix_rsp->ssow_msixoff[i];\n+\n+\tfor (i = 0; i < dev->nb_event_queues; i++)\n+\t\tdev->sso_msixoff[i] = msix_rsp->sso_msixoff[i];\n+\n+\treturn rc;\n+}\n \n static void\n otx2_sso_info_get(struct rte_eventdev *event_dev,\n@@ -486,6 +509,9 @@ otx2_sso_configure(const struct rte_eventdev *event_dev)\n \t\treturn -EINVAL;\n \t}\n \n+\tif (dev->configured)\n+\t\tsso_unregister_irqs(event_dev);\n+\n \tif (dev->nb_event_queues) {\n \t\t/* Finit any previous queues. */\n \t\tsso_lf_teardown(dev, SSO_LF_GGRP);\n@@ -522,6 +548,18 @@ otx2_sso_configure(const struct rte_eventdev *event_dev)\n \t\tgoto teardown_hwggrp;\n \t}\n \n+\trc = sso_get_msix_offsets(event_dev);\n+\tif (rc < 0) {\n+\t\totx2_err(\"failed to get msix offsets %d\", rc);\n+\t\tgoto teardown_hwggrp;\n+\t}\n+\n+\trc = sso_register_irqs(event_dev);\n+\tif (rc < 0) {\n+\t\totx2_err(\"failed to register irq %d\", rc);\n+\t\tgoto teardown_hwggrp;\n+\t}\n+\n \tdev->configured = 1;\n \trte_mb();\n \ndiff --git a/drivers/event/octeontx2/otx2_evdev.h b/drivers/event/octeontx2/otx2_evdev.h\nindex 1a9de1b86..e1d2dcc69 100644\n--- a/drivers/event/octeontx2/otx2_evdev.h\n+++ b/drivers/event/octeontx2/otx2_evdev.h\n@@ -105,6 +105,9 @@ struct otx2_sso_evdev {\n \tuint32_t xae_waes;\n \tuint32_t xaq_buf_size;\n \tuint32_t iue;\n+\t/* MSIX offsets */\n+\tuint16_t sso_msixoff[OTX2_SSO_MAX_VHGRP];\n+\tuint16_t ssow_msixoff[OTX2_SSO_MAX_VHWS];\n } __rte_cache_aligned;\n \n #define OTX2_SSOGWS_OPS \\\n@@ -148,5 +151,8 @@ parse_kvargs_value(const char *key, const char *value, void *opaque)\n /* Init and Fini API's */\n int otx2_sso_init(struct rte_eventdev *event_dev);\n int otx2_sso_fini(struct rte_eventdev *event_dev);\n+/* IRQ handlers */\n+int sso_register_irqs(const struct rte_eventdev *event_dev);\n+void sso_unregister_irqs(const struct rte_eventdev *event_dev);\n \n #endif /* __OTX2_EVDEV_H__ */\ndiff --git a/drivers/event/octeontx2/otx2_evdev_irq.c b/drivers/event/octeontx2/otx2_evdev_irq.c\nnew file mode 100644\nindex 000000000..ecc8ae775\n--- /dev/null\n+++ b/drivers/event/octeontx2/otx2_evdev_irq.c\n@@ -0,0 +1,179 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2019 Marvell International Ltd.\n+ */\n+\n+#include \"otx2_evdev.h\"\n+\n+static void\n+sso_lf_irq(void *param)\n+{\n+\tuintptr_t base = (uintptr_t)param;\n+\tuint64_t intr;\n+\tuint8_t ggrp;\n+\n+\tggrp = (base >> 12) & 0xFF;\n+\n+\tintr = otx2_read64(base + SSO_LF_GGRP_INT);\n+\tif (intr == 0)\n+\t\treturn;\n+\n+\totx2_err(\"GGRP %d GGRP_INT=0x%\" PRIx64 \"\", ggrp, intr);\n+\n+\t/* Clear interrupt */\n+\totx2_write64(intr, base + SSO_LF_GGRP_INT);\n+\n+\tabort();\n+}\n+\n+static int\n+sso_lf_register_irq(const struct rte_eventdev *event_dev, uint16_t ggrp_msixoff,\n+\t\t uintptr_t base)\n+{\n+\tstruct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(event_dev->dev);\n+\tstruct rte_intr_handle *handle = &pci_dev->intr_handle;\n+\tint rc, vec;\n+\n+\tvec = ggrp_msixoff + SSO_LF_INT_VEC_GRP;\n+\n+\t/* Clear err interrupt */\n+\totx2_write64(~0ull, base + SSO_LF_GGRP_INT_ENA_W1C);\n+\t/* Set used interrupt vectors */\n+\trc = otx2_register_irq(handle, sso_lf_irq, (void *)base, vec);\n+\t/* Enable hw interrupt */\n+\totx2_write64(~0ull, base + SSO_LF_GGRP_INT_ENA_W1S);\n+\n+\treturn rc;\n+}\n+\n+static void\n+ssow_lf_irq(void *param)\n+{\n+\tuintptr_t base = (uintptr_t)param;\n+\tuint8_t gws = (base >> 12) & 0xFF;\n+\tuint64_t intr;\n+\n+\tintr = otx2_read64(base + SSOW_LF_GWS_INT);\n+\tif (intr == 0)\n+\t\treturn;\n+\n+\totx2_err(\"GWS %d GWS_INT=0x%\" PRIx64 \"\", gws, intr);\n+\n+\t/* Clear interrupt */\n+\totx2_write64(intr, base + SSOW_LF_GWS_INT);\n+\n+\tabort();\n+}\n+\n+static int\n+ssow_lf_register_irq(const struct rte_eventdev *event_dev, uint16_t gws_msixoff,\n+\t\t uintptr_t base)\n+{\n+\tstruct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(event_dev->dev);\n+\tstruct rte_intr_handle *handle = &pci_dev->intr_handle;\n+\tint rc, vec;\n+\n+\tvec = gws_msixoff + SSOW_LF_INT_VEC_IOP;\n+\n+\t/* Clear err interrupt */\n+\totx2_write64(~0ull, base + SSOW_LF_GWS_INT_ENA_W1C);\n+\t/* Set used interrupt vectors */\n+\trc = otx2_register_irq(handle, ssow_lf_irq, (void *)base, vec);\n+\t/* Enable hw interrupt */\n+\totx2_write64(~0ull, base + SSOW_LF_GWS_INT_ENA_W1S);\n+\n+\treturn rc;\n+}\n+\n+static void\n+sso_lf_unregister_irq(const struct rte_eventdev *event_dev,\n+\t\t uint16_t ggrp_msixoff, uintptr_t base)\n+{\n+\tstruct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(event_dev->dev);\n+\tstruct rte_intr_handle *handle = &pci_dev->intr_handle;\n+\tint vec;\n+\n+\tvec = ggrp_msixoff + SSO_LF_INT_VEC_GRP;\n+\n+\t/* Clear err interrupt */\n+\totx2_write64(~0ull, base + SSO_LF_GGRP_INT_ENA_W1C);\n+\totx2_unregister_irq(handle, sso_lf_irq, (void *)base, vec);\n+}\n+\n+static void\n+ssow_lf_unregister_irq(const struct rte_eventdev *event_dev,\n+\t\t uint16_t gws_msixoff, uintptr_t base)\n+{\n+\tstruct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(event_dev->dev);\n+\tstruct rte_intr_handle *handle = &pci_dev->intr_handle;\n+\tint vec;\n+\n+\tvec = gws_msixoff + SSOW_LF_INT_VEC_IOP;\n+\n+\t/* Clear err interrupt */\n+\totx2_write64(~0ull, base + SSOW_LF_GWS_INT_ENA_W1C);\n+\totx2_unregister_irq(handle, ssow_lf_irq, (void *)base, vec);\n+}\n+\n+int\n+sso_register_irqs(const struct rte_eventdev *event_dev)\n+{\n+\tstruct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);\n+\tint i, rc = -EINVAL;\n+\tuint8_t nb_ports;\n+\n+\tnb_ports = dev->nb_event_ports;\n+\n+\tfor (i = 0; i < dev->nb_event_queues; i++) {\n+\t\tif (dev->sso_msixoff[i] == MSIX_VECTOR_INVALID) {\n+\t\t\totx2_err(\"Invalid SSOLF MSIX offset[%d] vector: 0x%x\",\n+\t\t\t\t i, dev->sso_msixoff[i]);\n+\t\t\tgoto fail;\n+\t\t}\n+\t}\n+\n+\tfor (i = 0; i < nb_ports; i++) {\n+\t\tif (dev->ssow_msixoff[i] == MSIX_VECTOR_INVALID) {\n+\t\t\totx2_err(\"Invalid SSOWLF MSIX offset[%d] vector: 0x%x\",\n+\t\t\t\t i, dev->ssow_msixoff[i]);\n+\t\t\tgoto fail;\n+\t\t}\n+\t}\n+\n+\tfor (i = 0; i < dev->nb_event_queues; i++) {\n+\t\tuintptr_t base = dev->bar2 + (RVU_BLOCK_ADDR_SSO << 20 |\n+\t\t\t\t\t i << 12);\n+\t\trc = sso_lf_register_irq(event_dev, dev->sso_msixoff[i], base);\n+\t}\n+\n+\tfor (i = 0; i < nb_ports; i++) {\n+\t\tuintptr_t base = dev->bar2 + (RVU_BLOCK_ADDR_SSOW << 20 |\n+\t\t\t\t\t i << 12);\n+\t\trc = ssow_lf_register_irq(event_dev, dev->ssow_msixoff[i],\n+\t\t\t\t\t base);\n+\t}\n+\n+fail:\n+\treturn rc;\n+}\n+\n+void\n+sso_unregister_irqs(const struct rte_eventdev *event_dev)\n+{\n+\tstruct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);\n+\tuint8_t nb_ports;\n+\tint i;\n+\n+\tnb_ports = dev->nb_event_ports;\n+\n+\tfor (i = 0; i < dev->nb_event_queues; i++) {\n+\t\tuintptr_t base = dev->bar2 + (RVU_BLOCK_ADDR_SSO << 20 |\n+\t\t\t\t\t i << 12);\n+\t\tsso_lf_unregister_irq(event_dev, dev->sso_msixoff[i], base);\n+\t}\n+\n+\tfor (i = 0; i < nb_ports; i++) {\n+\t\tuintptr_t base = dev->bar2 + (RVU_BLOCK_ADDR_SSOW << 20 |\n+\t\t\t\t\t i << 12);\n+\t\tssow_lf_unregister_irq(event_dev, dev->ssow_msixoff[i], base);\n+\t}\n+}\n", "prefixes": [ "11/44" ] }