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GET /api/patches/54017/?format=api
{ "id": 54017, "url": "http://patches.dpdk.org/api/patches/54017/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20190601185355.370-2-pbhagavatula@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20190601185355.370-2-pbhagavatula@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20190601185355.370-2-pbhagavatula@marvell.com", "date": "2019-06-01T18:53:11", "name": "[01/44] event/octeontx2: add build infra and device probe", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "0b6b9318521d466ec263b1013ecbd3d7957b1755", "submitter": { "id": 1183, "url": "http://patches.dpdk.org/api/people/1183/?format=api", "name": "Pavan Nikhilesh Bhagavatula", "email": "pbhagavatula@marvell.com" }, "delegate": { "id": 310, "url": "http://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20190601185355.370-2-pbhagavatula@marvell.com/mbox/", "series": [ { "id": 4847, "url": "http://patches.dpdk.org/api/series/4847/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=4847", "date": "2019-06-01T18:53:10", "name": "OCTEON TX2 event device driver", "version": 1, "mbox": "http://patches.dpdk.org/series/4847/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/54017/comments/", "check": "fail", "checks": "http://patches.dpdk.org/api/patches/54017/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 323211B996;\n\tSat, 1 Jun 2019 20:55:59 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n\t[67.231.156.173]) by dpdk.org (Postfix) with ESMTP id 5F1C3493D\n\tfor <dev@dpdk.org>; Sat, 1 Jun 2019 20:55:40 +0200 (CEST)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n\tby mx0b-0016f401.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id\n\tx51ItbrZ030054; Sat, 1 Jun 2019 11:55:39 -0700", "from sc-exch02.marvell.com ([199.233.58.182])\n\tby mx0b-0016f401.pphosted.com with ESMTP id 2survk12dg-4\n\t(version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); \n\tSat, 01 Jun 2019 11:55:39 -0700", "from SC-EXCH03.marvell.com (10.93.176.83) by SC-EXCH02.marvell.com\n\t(10.93.176.82) with Microsoft SMTP Server (TLS) id 15.0.1367.3;\n\tSat, 1 Jun 2019 11:55:35 -0700", "from maili.marvell.com (10.93.176.43) by SC-EXCH03.marvell.com\n\t(10.93.176.83) with Microsoft SMTP Server id 15.0.1367.3 via Frontend\n\tTransport; Sat, 1 Jun 2019 11:55:35 -0700", "from BG-LT7430.marvell.com (unknown [10.28.17.28])\n\tby maili.marvell.com (Postfix) with ESMTP id 9D6C13F70E2;\n\tSat, 1 Jun 2019 11:54:55 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n\th=from : to : cc :\n\tsubject : date : message-id : in-reply-to : references : mime-version\n\t: content-transfer-encoding : content-type; s=pfpt0818;\n\tbh=VOGgOXKqHMMlhrPKl+uaS/vTmVMRxrTOSFsE+KMK4c4=;\n\tb=XbRulVxzmR3BltLFGz+XWGR1fisATjTB6v5I4NDU1d6UIYo0A8YcBMXZILs8gNyXLAzz\n\tlWlNNnu+inEcgXXaXEzNoLAA+w7/2Mpo4hl/aHkTtjxwe2eddCD3l7VrJlQJBBLb1W/p\n\t5HIbjkEtI5Cc5zMOvLg6c3xjxyEXRgMQ4e9rhtSsslDwkTRLeg25Fc3K0LLeomFo9WsJ\n\tc+zN91aPfTugK131l3HBvvZjPtSMljHyCoBjMHakEUPm2XOpivQsXkMRJsnYGEFmwuyH\n\tZzHQs/euXoIdTgq70vrj8qzFvuSX3vvGZOeF0siH4G1Z0x7G7UgkbvHjVcwbpd3Vjnke\n\t6A== ", "From": "<pbhagavatula@marvell.com>", "To": "<jerinj@marvell.com>, Thomas Monjalon <thomas@monjalon.net>, \"Pavan\n\tNikhilesh\" <pbhagavatula@marvell.com>, Anatoly Burakov\n\t<anatoly.burakov@intel.com>", "CC": "<dev@dpdk.org>, Nithin Dabilpuram <ndabilpuram@marvell.com>", "Date": "Sun, 2 Jun 2019 00:23:11 +0530", "Message-ID": "<20190601185355.370-2-pbhagavatula@marvell.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20190601185355.370-1-pbhagavatula@marvell.com>", "References": "<20190601185355.370-1-pbhagavatula@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:, ,\n\tdefinitions=2019-06-01_13:, , signatures=0", "Subject": "[dpdk-dev] [PATCH 01/44] event/octeontx2: add build infra and\n\tdevice probe", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Pavan Nikhilesh <pbhagavatula@marvell.com>\n\nAdd the make and meson based build infrastructure along with the\neventdev(SSO) device probe.\n\nSigned-off-by: Jerin Jacob <jerinj@marvell.com>\nSigned-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>\nSigned-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>\n---\n config/common_base | 5 ++\n drivers/event/Makefile | 1 +\n drivers/event/meson.build | 2 +-\n drivers/event/octeontx2/Makefile | 39 +++++++++++\n drivers/event/octeontx2/meson.build | 21 ++++++\n drivers/event/octeontx2/otx2_evdev.c | 70 +++++++++++++++++++\n drivers/event/octeontx2/otx2_evdev.h | 26 +++++++\n .../rte_pmd_octeontx2_event_version.map | 4 ++\n mk/rte.app.mk | 2 +\n 9 files changed, 169 insertions(+), 1 deletion(-)\n create mode 100644 drivers/event/octeontx2/Makefile\n create mode 100644 drivers/event/octeontx2/meson.build\n create mode 100644 drivers/event/octeontx2/otx2_evdev.c\n create mode 100644 drivers/event/octeontx2/otx2_evdev.h\n create mode 100644 drivers/event/octeontx2/rte_pmd_octeontx2_event_version.map", "diff": "diff --git a/config/common_base b/config/common_base\nindex 4a3de0360..40d1cd18a 100644\n--- a/config/common_base\n+++ b/config/common_base\n@@ -741,6 +741,11 @@ CONFIG_RTE_LIBRTE_PMD_DPAA2_QDMA_RAWDEV=n\n #\n CONFIG_RTE_LIBRTE_PMD_IFPGA_RAWDEV=y\n \n+#\n+# Compile PMD for octeontx sso event device\n+#\n+CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_EVENTDEV=y\n+\n #\n # Compile librte_ring\n #\ndiff --git a/drivers/event/Makefile b/drivers/event/Makefile\nindex 03ad1b6cb..e4e7eff37 100644\n--- a/drivers/event/Makefile\n+++ b/drivers/event/Makefile\n@@ -15,5 +15,6 @@ ifeq ($(CONFIG_RTE_EAL_VFIO)$(CONFIG_RTE_LIBRTE_FSLMC_BUS),yy)\n DIRS-$(CONFIG_RTE_LIBRTE_PMD_DPAA2_EVENTDEV) += dpaa2\n endif\n DIRS-$(CONFIG_RTE_LIBRTE_PMD_OPDL_EVENTDEV) += opdl\n+DIRS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_EVENTDEV) += octeontx2\n \n include $(RTE_SDK)/mk/rte.subdir.mk\ndiff --git a/drivers/event/meson.build b/drivers/event/meson.build\nindex fb723f727..b204a9f8d 100644\n--- a/drivers/event/meson.build\n+++ b/drivers/event/meson.build\n@@ -1,7 +1,7 @@\n # SPDX-License-Identifier: BSD-3-Clause\n # Copyright(c) 2017 Intel Corporation\n \n-drivers = ['dpaa', 'dpaa2', 'opdl', 'skeleton', 'sw', 'dsw']\n+drivers = ['dpaa', 'dpaa2', 'opdl', 'skeleton', 'sw', 'dsw', 'octeontx2']\n if not (toolchain == 'gcc' and cc.version().version_compare('<4.8.6') and\n \tdpdk_conf.has('RTE_ARCH_ARM64'))\n \tdrivers += 'octeontx'\ndiff --git a/drivers/event/octeontx2/Makefile b/drivers/event/octeontx2/Makefile\nnew file mode 100644\nindex 000000000..dbf6ec22d\n--- /dev/null\n+++ b/drivers/event/octeontx2/Makefile\n@@ -0,0 +1,39 @@\n+# SPDX-License-Identifier: BSD-3-Clause\n+# Copyright(C) 2019 Marvell International Ltd.\n+#\n+\n+include $(RTE_SDK)/mk/rte.vars.mk\n+\n+#\n+# library name\n+#\n+LIB = librte_pmd_octeontx2_event.a\n+\n+CFLAGS += $(WERROR_FLAGS)\n+CFLAGS += -I$(RTE_SDK)/drivers/common/octeontx2\n+CFLAGS += -I$(RTE_SDK)/drivers/mempool/octeontx2\n+CFLAGS += -I$(RTE_SDK)/drivers/event/octeontx2\n+CFLAGS += -I$(RTE_SDK)/drivers/net/octeontx2\n+CFLAGS += -O3\n+CFLAGS += -DALLOW_EXPERIMENTAL_API\n+\n+ifneq ($(CONFIG_RTE_ARCH_64),y)\n+CFLAGS += -Wno-int-to-pointer-cast\n+CFLAGS += -Wno-pointer-to-int-cast\n+endif\n+\n+EXPORT_MAP := rte_pmd_octeontx2_event_version.map\n+\n+LIBABIVER := 1\n+\n+#\n+# all source are stored in SRCS-y\n+#\n+\n+SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_EVENTDEV) += otx2_evdev.c\n+\n+LDLIBS += -lrte_eal -lrte_bus_pci -lrte_pci\n+LDLIBS += -lrte_eventdev\n+LDLIBS += -lrte_common_octeontx2\n+\n+include $(RTE_SDK)/mk/rte.lib.mk\ndiff --git a/drivers/event/octeontx2/meson.build b/drivers/event/octeontx2/meson.build\nnew file mode 100644\nindex 000000000..c4f442174\n--- /dev/null\n+++ b/drivers/event/octeontx2/meson.build\n@@ -0,0 +1,21 @@\n+# SPDX-License-Identifier: BSD-3-Clause\n+# Copyright(C) 2019 Marvell International Ltd.\n+#\n+\n+sources = files('otx2_evdev.c')\n+\n+allow_experimental_apis = true\n+\n+extra_flags = []\n+# This integrated controller runs only on a arm64 machine, remove 32bit warnings\n+if not dpdk_conf.get('RTE_ARCH_64')\n+\textra_flags += ['-Wno-int-to-pointer-cast', '-Wno-pointer-to-int-cast']\n+endif\n+\n+foreach flag: extra_flags\n+\tif cc.has_argument(flag)\n+\t\tcflags += flag\n+\tendif\n+endforeach\n+\n+deps += ['bus_pci', 'common_octeontx2']\ndiff --git a/drivers/event/octeontx2/otx2_evdev.c b/drivers/event/octeontx2/otx2_evdev.c\nnew file mode 100644\nindex 000000000..faffd3f0c\n--- /dev/null\n+++ b/drivers/event/octeontx2/otx2_evdev.c\n@@ -0,0 +1,70 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2019 Marvell International Ltd.\n+ */\n+\n+#include <inttypes.h>\n+\n+#include <rte_bus_pci.h>\n+#include <rte_common.h>\n+#include <rte_eal.h>\n+#include <rte_eventdev_pmd_pci.h>\n+#include <rte_pci.h>\n+\n+#include \"otx2_evdev.h\"\n+\n+static int\n+otx2_sso_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)\n+{\n+\treturn rte_event_pmd_pci_probe(pci_drv, pci_dev,\n+\t\t\t\t sizeof(struct otx2_sso_evdev),\n+\t\t\t\t otx2_sso_init);\n+}\n+\n+static int\n+otx2_sso_remove(struct rte_pci_device *pci_dev)\n+{\n+\treturn rte_event_pmd_pci_remove(pci_dev, otx2_sso_fini);\n+}\n+\n+static const struct rte_pci_id pci_sso_map[] = {\n+\t{\n+\t\tRTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM,\n+\t\t\t PCI_DEVID_OCTEONTX2_RVU_SSO_TIM_PF)\n+\t},\n+\t{\n+\t\t.vendor_id = 0,\n+\t},\n+};\n+\n+static struct rte_pci_driver pci_sso = {\n+\t.id_table = pci_sso_map,\n+\t.drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_IOVA_AS_VA,\n+\t.probe = otx2_sso_probe,\n+\t.remove = otx2_sso_remove,\n+};\n+\n+int\n+otx2_sso_init(struct rte_eventdev *event_dev)\n+{\n+\tRTE_SET_USED(event_dev);\n+\t/* For secondary processes, the primary has done all the work */\n+\tif (rte_eal_process_type() != RTE_PROC_PRIMARY)\n+\t\treturn 0;\n+\n+\treturn 0;\n+}\n+\n+int\n+otx2_sso_fini(struct rte_eventdev *event_dev)\n+{\n+\tRTE_SET_USED(event_dev);\n+\t/* For secondary processes, nothing to be done */\n+\tif (rte_eal_process_type() != RTE_PROC_PRIMARY)\n+\t\treturn 0;\n+\n+\treturn 0;\n+}\n+\n+RTE_PMD_REGISTER_PCI(event_octeontx2, pci_sso);\n+RTE_PMD_REGISTER_PCI_TABLE(event_octeontx2, pci_sso_map);\n+RTE_PMD_REGISTER_KMOD_DEP(event_octeontx2, \"vfio-pci\");\ndiff --git a/drivers/event/octeontx2/otx2_evdev.h b/drivers/event/octeontx2/otx2_evdev.h\nnew file mode 100644\nindex 000000000..1df233293\n--- /dev/null\n+++ b/drivers/event/octeontx2/otx2_evdev.h\n@@ -0,0 +1,26 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2019 Marvell International Ltd.\n+ */\n+\n+#ifndef __OTX2_EVDEV_H__\n+#define __OTX2_EVDEV_H__\n+\n+#include <rte_eventdev.h>\n+\n+#include \"otx2_common.h\"\n+\n+#define EVENTDEV_NAME_OCTEONTX2_PMD otx2_eventdev\n+\n+#define sso_func_trace otx2_sso_dbg\n+\n+#define OTX2_SSO_MAX_VHGRP RTE_EVENT_MAX_QUEUES_PER_DEV\n+#define OTX2_SSO_MAX_VHWS (UINT8_MAX)\n+\n+struct otx2_sso_evdev {\n+};\n+\n+/* Init and Fini API's */\n+int otx2_sso_init(struct rte_eventdev *event_dev);\n+int otx2_sso_fini(struct rte_eventdev *event_dev);\n+\n+#endif /* __OTX2_EVDEV_H__ */\ndiff --git a/drivers/event/octeontx2/rte_pmd_octeontx2_event_version.map b/drivers/event/octeontx2/rte_pmd_octeontx2_event_version.map\nnew file mode 100644\nindex 000000000..26a69c2c9\n--- /dev/null\n+++ b/drivers/event/octeontx2/rte_pmd_octeontx2_event_version.map\n@@ -0,0 +1,4 @@\n+DPDK_19.05 {\n+\tlocal: *;\n+};\n+\ndiff --git a/mk/rte.app.mk b/mk/rte.app.mk\nindex cd89ccfd5..8f39f7342 100644\n--- a/mk/rte.app.mk\n+++ b/mk/rte.app.mk\n@@ -127,6 +127,7 @@ _LDLIBS-$(CONFIG_RTE_LIBRTE_COMMON_DPAAX) += -lrte_common_dpaax\n endif\n \n OCTEONTX2-y := $(CONFIG_RTE_LIBRTE_OCTEONTX2_MEMPOOL)\n+OCTEONTX2-y += $(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_EVENTDEV)\n ifeq ($(findstring y,$(OCTEONTX2-y)),y)\n _LDLIBS-y += -lrte_common_octeontx2\n endif\n@@ -296,6 +297,7 @@ endif # CONFIG_RTE_LIBRTE_FSLMC_BUS\n _LDLIBS-$(CONFIG_RTE_LIBRTE_OCTEONTX_MEMPOOL) += -lrte_mempool_octeontx\n _LDLIBS-$(CONFIG_RTE_LIBRTE_OCTEONTX_PMD) += -lrte_pmd_octeontx\n _LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_OPDL_EVENTDEV) += -lrte_pmd_opdl_event\n+_LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_EVENTDEV) += -lrte_pmd_octeontx2_event\n endif # CONFIG_RTE_LIBRTE_EVENTDEV\n \n ifeq ($(CONFIG_RTE_LIBRTE_RAWDEV),y)\n", "prefixes": [ "01/44" ] }