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GET /api/patches/54013/?format=api
{ "id": 54013, "url": "http://patches.dpdk.org/api/patches/54013/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20190601185355.370-3-pbhagavatula@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20190601185355.370-3-pbhagavatula@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20190601185355.370-3-pbhagavatula@marvell.com", "date": "2019-06-01T18:53:12", "name": "[02/44] event/octeontx2: add init and fini for octeontx2 SSO object", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "6690a3a911fcc43099fbe8b930b536e1297b5e90", "submitter": { "id": 1183, "url": "http://patches.dpdk.org/api/people/1183/?format=api", "name": "Pavan Nikhilesh Bhagavatula", "email": "pbhagavatula@marvell.com" }, "delegate": { "id": 310, "url": "http://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20190601185355.370-3-pbhagavatula@marvell.com/mbox/", "series": [ { "id": 4847, "url": "http://patches.dpdk.org/api/series/4847/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=4847", "date": "2019-06-01T18:53:10", "name": "OCTEON TX2 event device driver", "version": 1, "mbox": "http://patches.dpdk.org/series/4847/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/54013/comments/", "check": "fail", "checks": "http://patches.dpdk.org/api/patches/54013/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 3D8BA1B952;\n\tSat, 1 Jun 2019 20:55:47 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n\t[67.231.156.173]) by dpdk.org (Postfix) with ESMTP id D5C2B2C60\n\tfor <dev@dpdk.org>; Sat, 1 Jun 2019 20:55:39 +0200 (CEST)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n\tby mx0b-0016f401.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id\n\tx51ItbrX030054 for <dev@dpdk.org>; Sat, 1 Jun 2019 11:55:39 -0700", "from sc-exch02.marvell.com ([199.233.58.182])\n\tby mx0b-0016f401.pphosted.com with ESMTP id 2survk12dg-3\n\t(version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n\tfor <dev@dpdk.org>; Sat, 01 Jun 2019 11:55:38 -0700", "from SC-EXCH01.marvell.com (10.93.176.81) by SC-EXCH02.marvell.com\n\t(10.93.176.82) with Microsoft SMTP Server (TLS) id 15.0.1367.3;\n\tSat, 1 Jun 2019 11:55:35 -0700", "from maili.marvell.com (10.93.176.43) by SC-EXCH01.marvell.com\n\t(10.93.176.81) with Microsoft SMTP Server id 15.0.1367.3 via Frontend\n\tTransport; Sat, 1 Jun 2019 11:55:35 -0700", "from BG-LT7430.marvell.com (unknown [10.28.17.28])\n\tby maili.marvell.com (Postfix) with ESMTP id 0C25A3F70E4;\n\tSat, 1 Jun 2019 11:54:58 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n\th=from : to : cc :\n\tsubject : date : message-id : in-reply-to : references : mime-version\n\t: content-transfer-encoding : content-type; s=pfpt0818;\n\tbh=dooWT1712FVtM0en9YKuX9x8jcqvMnFRUQv2sNjvaUg=;\n\tb=UqDXqgkfId58Dhha7Wzb3hx0l1cSVw128u27kD5AfPe7MfYOZrzcjykDEeSnadC5C1kC\n\tMpIUmi0552aCU9nUZMLHiAiOa+acfdGqPQyL7yOFtYPjgX+rusgJs9yuoH4U08NwCcN3\n\tC+TVHva3Qky12T2G+zxBUiTE7itv9uVlAFmDRczjkXHQSrb9m9dPHJflrpZFoFMS67+D\n\topuEFYrroFN8sK5W5ED9e9h4wou54Qupi0Mv0Q0u8Ornd4CUJjmM40LSx5ydIZdN73WC\n\t/wFmJnn9gPOYc9aev/FvxnC4K72+pYiblNhdeT4om+mxIdlkW1Y5kMU9S1Lh4KuVfbGs\n\tbw== ", "From": "<pbhagavatula@marvell.com>", "To": "<jerinj@marvell.com>, Pavan Nikhilesh <pbhagavatula@marvell.com>", "CC": "<dev@dpdk.org>, Nithin Dabilpuram <ndabilpuram@marvell.com>", "Date": "Sun, 2 Jun 2019 00:23:12 +0530", "Message-ID": "<20190601185355.370-3-pbhagavatula@marvell.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20190601185355.370-1-pbhagavatula@marvell.com>", "References": "<20190601185355.370-1-pbhagavatula@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:, ,\n\tdefinitions=2019-06-01_13:, , signatures=0", "Subject": "[dpdk-dev] [PATCH 02/44] event/octeontx2: add init and fini for\n\tocteontx2 SSO object", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Pavan Nikhilesh <pbhagavatula@marvell.com>\n\nSSO object needs to be initialized to communicate with the kernel AF\ndriver through mbox using the common API's.\nAlso, initialize the internal eventdev structure to defaults.\nAttach NPA lf to the PF if needed.\n\nSigned-off-by: Jerin Jacob <jerinj@marvell.com>\nSigned-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>\nSigned-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>\n---\n drivers/event/octeontx2/Makefile | 2 +-\n drivers/event/octeontx2/meson.build | 2 +-\n drivers/event/octeontx2/otx2_evdev.c | 85 +++++++++++++++++++++++++++-\n drivers/event/octeontx2/otx2_evdev.h | 22 ++++++-\n 4 files changed, 106 insertions(+), 5 deletions(-)", "diff": "diff --git a/drivers/event/octeontx2/Makefile b/drivers/event/octeontx2/Makefile\nindex dbf6ec22d..36f0b2b12 100644\n--- a/drivers/event/octeontx2/Makefile\n+++ b/drivers/event/octeontx2/Makefile\n@@ -34,6 +34,6 @@ SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_EVENTDEV) += otx2_evdev.c\n \n LDLIBS += -lrte_eal -lrte_bus_pci -lrte_pci\n LDLIBS += -lrte_eventdev\n-LDLIBS += -lrte_common_octeontx2\n+LDLIBS += -lrte_common_octeontx2 -lrte_mempool_octeontx2\n \n include $(RTE_SDK)/mk/rte.lib.mk\ndiff --git a/drivers/event/octeontx2/meson.build b/drivers/event/octeontx2/meson.build\nindex c4f442174..3fc96421d 100644\n--- a/drivers/event/octeontx2/meson.build\n+++ b/drivers/event/octeontx2/meson.build\n@@ -18,4 +18,4 @@ foreach flag: extra_flags\n \tendif\n endforeach\n \n-deps += ['bus_pci', 'common_octeontx2']\n+deps += ['bus_pci', 'common_octeontx2', 'mempool_octeontx2']\ndiff --git a/drivers/event/octeontx2/otx2_evdev.c b/drivers/event/octeontx2/otx2_evdev.c\nindex faffd3f0c..15190af9e 100644\n--- a/drivers/event/octeontx2/otx2_evdev.c\n+++ b/drivers/event/octeontx2/otx2_evdev.c\n@@ -46,22 +46,103 @@ static struct rte_pci_driver pci_sso = {\n int\n otx2_sso_init(struct rte_eventdev *event_dev)\n {\n-\tRTE_SET_USED(event_dev);\n+\tstruct free_rsrcs_rsp *rsrc_cnt;\n+\tstruct rte_pci_device *pci_dev;\n+\tstruct otx2_sso_evdev *dev;\n+\tint rc;\n+\n \t/* For secondary processes, the primary has done all the work */\n \tif (rte_eal_process_type() != RTE_PROC_PRIMARY)\n \t\treturn 0;\n \n+\tdev = sso_pmd_priv(event_dev);\n+\n+\tpci_dev = container_of(event_dev->dev, struct rte_pci_device, device);\n+\n+\t/* Initialize the base otx2_dev object */\n+\trc = otx2_dev_init(pci_dev, dev);\n+\tif (rc < 0) {\n+\t\totx2_err(\"failed to initialize otx2_dev rc=%d\", rc);\n+\t\tgoto error;\n+\t}\n+\n+\t/* Get SSO and SSOW MSIX rsrc cnt */\n+\totx2_mbox_alloc_msg_free_rsrc_cnt(dev->mbox);\n+\trc = otx2_mbox_process_msg(dev->mbox, (void *)&rsrc_cnt);\n+\tif (rc < 0) {\n+\t\totx2_err(\"unable to get free rsrc count\");\n+\t\tgoto otx2_dev_uninit;\n+\t}\n+\totx2_sso_dbg(\"sso %d ssow %d npalf %d provisioned\", rsrc_cnt->sso,\n+\t\t rsrc_cnt->ssow, rsrc_cnt->npa);\n+\n+\tdev->max_event_ports = RTE_MIN(rsrc_cnt->ssow, OTX2_SSO_MAX_VHWS);\n+\tdev->max_event_queues = RTE_MIN(rsrc_cnt->sso, OTX2_SSO_MAX_VHGRP);\n+\t/* Grab the NPA LF if required */\n+\trc = otx2_npa_lf_init(pci_dev, dev);\n+\tif (rc < 0) {\n+\t\totx2_err(\"unable to init npalf. It might not be provisioned\");\n+\t\tgoto otx2_dev_uninit;\n+\t}\n+\n+\tdev->drv_inited = true;\n+\tdev->is_timeout_deq = 0;\n+\tdev->min_dequeue_timeout_ns = USEC2NSEC(1);\n+\tdev->max_dequeue_timeout_ns = USEC2NSEC(0x3FF);\n+\tdev->max_num_events = -1;\n+\tdev->nb_event_queues = 0;\n+\tdev->nb_event_ports = 0;\n+\n+\tif (!dev->max_event_ports || !dev->max_event_queues) {\n+\t\totx2_err(\"not enough eventdev resource queues=%d ports=%d\",\n+\t\t\t dev->max_event_queues, dev->max_event_ports);\n+\t\trc = -ENODEV;\n+\t\tgoto otx2_npa_lf_uninit;\n+\t}\n+\n+\totx2_sso_pf_func_set(dev->pf_func);\n+\totx2_sso_dbg(\"initializing %s max_queues=%d max_ports=%d\",\n+\t\t event_dev->data->name, dev->max_event_queues,\n+\t\t dev->max_event_ports);\n+\n+\n \treturn 0;\n+\n+otx2_npa_lf_uninit:\n+\totx2_npa_lf_fini();\n+otx2_dev_uninit:\n+\totx2_dev_fini(pci_dev, dev);\n+error:\n+\treturn rc;\n }\n \n int\n otx2_sso_fini(struct rte_eventdev *event_dev)\n {\n-\tRTE_SET_USED(event_dev);\n+\tstruct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);\n+\tstruct rte_pci_device *pci_dev;\n+\n \t/* For secondary processes, nothing to be done */\n \tif (rte_eal_process_type() != RTE_PROC_PRIMARY)\n \t\treturn 0;\n \n+\tpci_dev = container_of(event_dev->dev, struct rte_pci_device, device);\n+\n+\tif (!dev->drv_inited)\n+\t\tgoto dev_fini;\n+\n+\tdev->drv_inited = false;\n+\totx2_npa_lf_fini();\n+\n+dev_fini:\n+\tif (otx2_npa_lf_active(dev)) {\n+\t\totx2_info(\"%s: common resource in use by other devices\",\n+\t\t\t pci_dev->name);\n+\t\treturn -EAGAIN;\n+\t}\n+\n+\totx2_dev_fini(pci_dev, dev);\n+\n \treturn 0;\n }\n \ndiff --git a/drivers/event/octeontx2/otx2_evdev.h b/drivers/event/octeontx2/otx2_evdev.h\nindex 1df233293..4427efcad 100644\n--- a/drivers/event/octeontx2/otx2_evdev.h\n+++ b/drivers/event/octeontx2/otx2_evdev.h\n@@ -8,6 +8,8 @@\n #include <rte_eventdev.h>\n \n #include \"otx2_common.h\"\n+#include \"otx2_dev.h\"\n+#include \"otx2_mempool.h\"\n \n #define EVENTDEV_NAME_OCTEONTX2_PMD otx2_eventdev\n \n@@ -16,8 +18,26 @@\n #define OTX2_SSO_MAX_VHGRP RTE_EVENT_MAX_QUEUES_PER_DEV\n #define OTX2_SSO_MAX_VHWS (UINT8_MAX)\n \n+#define USEC2NSEC(__us) ((__us) * 1E3)\n+\n struct otx2_sso_evdev {\n-};\n+\tOTX2_DEV; /* Base class */\n+\tuint8_t max_event_queues;\n+\tuint8_t max_event_ports;\n+\tuint8_t is_timeout_deq;\n+\tuint8_t nb_event_queues;\n+\tuint8_t nb_event_ports;\n+\tuint32_t deq_tmo_ns;\n+\tuint32_t min_dequeue_timeout_ns;\n+\tuint32_t max_dequeue_timeout_ns;\n+\tint32_t max_num_events;\n+} __rte_cache_aligned;\n+\n+static inline struct otx2_sso_evdev *\n+sso_pmd_priv(const struct rte_eventdev *event_dev)\n+{\n+\treturn event_dev->data->dev_private;\n+}\n \n /* Init and Fini API's */\n int otx2_sso_init(struct rte_eventdev *event_dev);\n", "prefixes": [ "02/44" ] }