Patch Detail

HTTP 200 OK
Allow: GET, PUT, PATCH, HEAD, OPTIONS
Content-Type: application/json
Vary: Accept

{
    "id": 54005,
    "url": "http://patches.dpdk.org/api/patches/54005/?format=api",
    "web_url": "http://patches.dpdk.org/project/dpdk/patch/20190601182030.8282-5-jerinj@marvell.com/",
    "project": {
        "id": 1,
        "url": "http://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<20190601182030.8282-5-jerinj@marvell.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/20190601182030.8282-5-jerinj@marvell.com",
    "date": "2019-06-01T18:20:25",
    "name": "[v1,4/9] raw/octeontx2_dma: add device close operation",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": true,
    "hash": "51c6e764c917488cad253c77b5d22da4ff01bd5d",
    "submitter": {
        "id": 1188,
        "url": "http://patches.dpdk.org/api/people/1188/?format=api",
        "name": "Jerin Jacob Kollanukkaran",
        "email": "jerinj@marvell.com"
    },
    "delegate": null,
    "mbox": "http://patches.dpdk.org/project/dpdk/patch/20190601182030.8282-5-jerinj@marvell.com/mbox/",
    "series": [
        {
            "id": 4846,
            "url": "http://patches.dpdk.org/api/series/4846/?format=api",
            "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=4846",
            "date": "2019-06-01T18:20:21",
            "name": "OCTEON TX2 DMA driver",
            "version": 1,
            "mbox": "http://patches.dpdk.org/series/4846/mbox/"
        }
    ],
    "comments": "http://patches.dpdk.org/api/patches/54005/comments/",
    "check": "fail",
    "checks": "http://patches.dpdk.org/api/patches/54005/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@dpdk.org",
        "Delivered-To": "patchwork@dpdk.org",
        "Received": [
            "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id DCB431B95A;\n\tSat,  1 Jun 2019 20:20:33 +0200 (CEST)",
            "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n\t[67.231.148.174]) by dpdk.org (Postfix) with ESMTP id 0A12E1B959\n\tfor <dev@dpdk.org>; Sat,  1 Jun 2019 20:20:31 +0200 (CEST)",
            "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n\tby mx0a-0016f401.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id\n\tx51IKArr002841 for <dev@dpdk.org>; Sat, 1 Jun 2019 11:20:31 -0700",
            "from sc-exch02.marvell.com ([199.233.58.182])\n\tby mx0a-0016f401.pphosted.com with ESMTP id 2supqksde6-1\n\t(version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n\tfor <dev@dpdk.org>; Sat, 01 Jun 2019 11:20:31 -0700",
            "from SC-EXCH03.marvell.com (10.93.176.83) by SC-EXCH02.marvell.com\n\t(10.93.176.82) with Microsoft SMTP Server (TLS) id 15.0.1367.3;\n\tSat, 1 Jun 2019 11:20:30 -0700",
            "from maili.marvell.com (10.93.176.43) by SC-EXCH03.marvell.com\n\t(10.93.176.83) with Microsoft SMTP Server id 15.0.1367.3 via Frontend\n\tTransport; Sat, 1 Jun 2019 11:20:30 -0700",
            "from jerin-lab.marvell.com (jerin-lab.marvell.com [10.28.34.14])\n\tby maili.marvell.com (Postfix) with ESMTP id 6EB8D3F703F;\n\tSat,  1 Jun 2019 11:20:29 -0700 (PDT)"
        ],
        "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n\th=from : to : cc :\n\tsubject : date : message-id : in-reply-to : references : mime-version\n\t: content-transfer-encoding : content-type; s=pfpt0818;\n\tbh=cN56tGQqZtqSBiHwB67xRDl0akepeHjywvwnxrdluTs=;\n\tb=rjBfivYleqoyHsFKYj3irNolSW5Z7FWTbMwjafm12MFUx6ExCae6Oj43D5lpK53K2P09\n\tK1LlDfKTUW7H166S6ekqUa5uFzgpx3DoA+xvSDIbqQqHJiETKU1w4Mi4L0wZaIVcYB5e\n\t86+AkxBTtXDe69yiSmBHpy855qtQNj6Y07dDn1iEtJ1gXWh+1zrAQIvA3YJZRslXxQjI\n\tkJbh66mCTAS8fzITDXEfEVSbpaKZmcrlQDcXysVtN2wwDTR2G77ZfZnbCuOL17558/Qt\n\taCpd1TMbrka8yU7YjGgRG0S46hFQ1f6Ng8J5NpHFqcWih9KtquvrKtxjqOS1CjKlNSeQ\n\tkg== ",
        "From": "<jerinj@marvell.com>",
        "To": "<dev@dpdk.org>",
        "CC": "<skoteshwar@marvell.com>, Vamsi Attunuru <vattunuru@marvell.com>",
        "Date": "Sat, 1 Jun 2019 23:50:25 +0530",
        "Message-ID": "<20190601182030.8282-5-jerinj@marvell.com>",
        "X-Mailer": "git-send-email 2.21.0",
        "In-Reply-To": "<20190601182030.8282-1-jerinj@marvell.com>",
        "References": "<20190601182030.8282-1-jerinj@marvell.com>",
        "MIME-Version": "1.0",
        "Content-Transfer-Encoding": "8bit",
        "Content-Type": "text/plain",
        "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:, ,\n\tdefinitions=2019-06-01_13:, , signatures=0",
        "Subject": "[dpdk-dev] [PATCH v1 4/9] raw/octeontx2_dma: add device close\n\toperation",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.15",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "From: Satha Rao <skoteshwar@marvell.com>\n\nSend message to PF to stop DMA queue when device close is\ncalled from application.\nDefined the required data structures to support enqueue and\ndequeue APIs.\n\nSigned-off-by: Satha Rao <skoteshwar@marvell.com>\nSigned-off-by: Vamsi Attunuru <vattunuru@marvell.com>\n---\n drivers/raw/octeontx2_dma/otx2_dpi_rawdev.c |  33 +++++\n drivers/raw/octeontx2_dma/otx2_dpi_rawdev.h | 133 ++++++++++++++++++++\n 2 files changed, 166 insertions(+)",
    "diff": "diff --git a/drivers/raw/octeontx2_dma/otx2_dpi_rawdev.c b/drivers/raw/octeontx2_dma/otx2_dpi_rawdev.c\nindex b418dc5bb..e7e30825f 100644\n--- a/drivers/raw/octeontx2_dma/otx2_dpi_rawdev.c\n+++ b/drivers/raw/octeontx2_dma/otx2_dpi_rawdev.c\n@@ -41,6 +41,34 @@ dma_engine_enb_dis(struct dpi_vf_s *dpivf, const bool enb)\n \treturn DPI_DMA_QUEUE_SUCCESS;\n }\n \n+/* Free DMA Queue instruction buffers, and send close notification to PF */\n+static inline int\n+dma_queue_finish(struct dpi_vf_s *dpivf)\n+{\n+\tuint32_t timeout = 0, sleep = 1;\n+\tuint64_t reg = 0ULL;\n+\n+\t/* Wait for SADDR to become idle */\n+\treg = otx2_read64(dpivf->vf_bar0 + DPI_VDMA_SADDR);\n+\twhile (!(reg & BIT_ULL(DPI_VDMA_SADDR_REQ_IDLE))) {\n+\t\trte_delay_ms(sleep);\n+\t\ttimeout++;\n+\t\tif (timeout >= DPI_QFINISH_TIMEOUT) {\n+\t\t\totx2_dpi_dbg(\"Timeout!!! Closing Forcibly\");\n+\t\t\tbreak;\n+\t\t}\n+\t\treg = otx2_read64(dpivf->vf_bar0 + DPI_VDMA_SADDR);\n+\t}\n+\n+\tif (otx2_dpi_queue_close(dpivf->vf_id) < 0)\n+\t\treturn -EACCES;\n+\n+\trte_mempool_put(dpivf->chunk_pool, dpivf->base_ptr);\n+\tdpivf->vf_bar0 = (uintptr_t)NULL;\n+\n+\treturn DPI_DMA_QUEUE_SUCCESS;\n+}\n+\n static int\n otx2_dpi_rawdev_configure(const struct rte_rawdev *dev, rte_rawdev_obj_t config)\n {\n@@ -140,6 +168,7 @@ otx2_dpi_rawdev_remove(struct rte_pci_device *pci_dev)\n {\n \tchar name[RTE_RAWDEV_NAME_MAX_LEN];\n \tstruct rte_rawdev *rawdev;\n+\tstruct dpi_vf_s *dpivf;\n \n \tif (pci_dev == NULL) {\n \t\totx2_dpi_dbg(\"Invalid pci_dev of the device!\");\n@@ -157,6 +186,10 @@ otx2_dpi_rawdev_remove(struct rte_pci_device *pci_dev)\n \t\treturn -EINVAL;\n \t}\n \n+\tdpivf = (struct dpi_vf_s *)rawdev->dev_private;\n+\tdma_engine_enb_dis(dpivf, false);\n+\tdma_queue_finish(dpivf);\n+\n \t/* rte_rawdev_close is called by pmd_release */\n \treturn rte_rawdev_pmd_release(rawdev);\n }\ndiff --git a/drivers/raw/octeontx2_dma/otx2_dpi_rawdev.h b/drivers/raw/octeontx2_dma/otx2_dpi_rawdev.h\nindex 918ae725a..f59bab97f 100644\n--- a/drivers/raw/octeontx2_dma/otx2_dpi_rawdev.h\n+++ b/drivers/raw/octeontx2_dma/otx2_dpi_rawdev.h\n@@ -31,6 +31,32 @@\n #define DPI_QUEUE_STOP\t\t0x0\n #define DPI_QUEUE_START\t\t0x1\n \n+#define DPI_VDMA_SADDR_REQ_IDLE\t63\n+#define DPI_MAX_POINTER\t\t15\n+#define STRM_INC(s)\t((s)->tail = ((s)->tail + 1) % (s)->max_cnt)\n+#define DPI_QFINISH_TIMEOUT\t(10 * 1000)\n+\n+/* DPI Transfer Type, pointer type in DPI_DMA_INSTR_HDR_S[XTYPE] */\n+#define DPI_XTYPE_OUTBOUND      (0)\n+#define DPI_XTYPE_INBOUND       (1)\n+#define DPI_XTYPE_INTERNAL_ONLY (2)\n+#define DPI_XTYPE_EXTERNAL_ONLY (3)\n+#define DPI_XTYPE_MASK\t\t0x3\n+#define DPI_HDR_PT_ZBW_CA\t0x0\n+#define DPI_HDR_PT_ZBW_NC\t0x1\n+#define DPI_HDR_PT_WQP\t\t0x2\n+#define DPI_HDR_PT_WQP_NOSTATUS\t0x0\n+#define DPI_HDR_PT_WQP_STATUSCA\t0x1\n+#define DPI_HDR_PT_WQP_STATUSNC\t0x3\n+#define DPI_HDR_PT_CNT\t\t0x3\n+#define DPI_HDR_PT_MASK\t\t0x3\n+#define DPI_W0_TT_MASK\t\t0x3\n+#define DPI_W0_GRP_MASK\t\t0x3FF\n+/* Set Completion data to 0xFF when request submitted,\n+ * upon successful request completion engine reset to completion status\n+ */\n+#define DPI_REQ_CDATA\t\t0xFF\n+\n struct dpi_vf_s {\n \tstruct rte_pci_device *dev;\n \tuint8_t state;\n@@ -56,6 +82,113 @@ enum dpi_dma_queue_result_e {\n \tDPI_DMA_QUEUE_INVALID_PARAM = -2,\n };\n \n+struct dpi_dma_req_compl_s {\n+\tuint64_t cdata;\n+\tvoid (*compl_cb)(void *dev, void *arg);\n+\tvoid *cb_data;\n+};\n+\n+union dpi_dma_ptr_u {\n+\tuint64_t u[2];\n+\tstruct dpi_dma_s {\n+\t\tuint64_t length:16;\n+\t\tuint64_t reserved:44;\n+\t\tuint64_t bed:1; /* Big-Endian */\n+\t\tuint64_t alloc_l2:1;\n+\t\tuint64_t full_write:1;\n+\t\tuint64_t invert:1;\n+\t\tuint64_t ptr;\n+\t} s;\n+};\n+\n+struct dpi_dma_buf_ptr_s {\n+\tunion dpi_dma_ptr_u *rptr[DPI_MAX_POINTER]; /* Read From pointer list */\n+\tunion dpi_dma_ptr_u *wptr[DPI_MAX_POINTER]; /* Write to pointer list */\n+\tuint8_t rptr_cnt;\n+\tuint8_t wptr_cnt;\n+\tstruct dpi_dma_req_compl_s *comp_ptr;\n+};\n+\n+struct dpi_cring_data_s {\n+\tstruct dpi_dma_req_compl_s **compl_data;\n+\tuint16_t max_cnt;\n+\tuint16_t head;\n+\tuint16_t tail;\n+};\n+\n+struct dpi_dma_queue_ctx_s {\n+\tuint16_t xtype:2;\n+\n+\t/* Completion pointer type */\n+\tuint16_t pt:2;\n+\n+\t/* Completion updated using WQE */\n+\tuint16_t tt:2;\n+\tuint16_t grp:10;\n+\tuint32_t tag;\n+\n+\t/* Valid only for Outbound only mode */\n+\tuint16_t aura:12;\n+\tuint16_t csel:1;\n+\tuint16_t ca:1;\n+\tuint16_t fi:1;\n+\tuint16_t ii:1;\n+\tuint16_t fl:1;\n+\n+\tuint16_t pvfe:1;\n+\tuint16_t dealloce:1;\n+\tuint16_t req_type:2;\n+\tuint16_t use_lock:1;\n+\tuint16_t deallocv;\n+\n+\tstruct dpi_cring_data_s *c_ring;\n+};\n+\n+/* DPI DMA Instruction Header Format */\n+union dpi_dma_instr_hdr_u {\n+\tuint64_t u[4];\n+\n+\tstruct dpi_dma_instr_hdr_s_s {\n+\t\tuint64_t tag:32;\n+\t\tuint64_t tt:2;\n+\t\tuint64_t grp:10;\n+\t\tuint64_t reserved_44_47:4;\n+\t\tuint64_t nfst:4;\n+\t\tuint64_t reserved_52_53:2;\n+\t\tuint64_t nlst:4;\n+\t\tuint64_t reserved_58_63:6;\n+\t\t/* Word 0 - End */\n+\n+\t\tuint64_t aura:12;\n+\t\tuint64_t reserved_76_79:4;\n+\t\tuint64_t deallocv:16;\n+\t\tuint64_t dealloce:1;\n+\t\tuint64_t pvfe:1;\n+\t\tuint64_t reserved_98_99:2;\n+\t\tuint64_t pt:2;\n+\t\tuint64_t reserved_102_103:2;\n+\t\tuint64_t fl:1;\n+\t\tuint64_t ii:1;\n+\t\tuint64_t fi:1;\n+\t\tuint64_t ca:1;\n+\t\tuint64_t csel:1;\n+\t\tuint64_t reserved_109_111:3;\n+\t\tuint64_t xtype:2;\n+\t\tuint64_t reserved_114_119:6;\n+\t\tuint64_t fport:2;\n+\t\tuint64_t reserved_122_123:2;\n+\t\tuint64_t lport:2;\n+\t\tuint64_t reserved_126_127:2;\n+\t\t/* Word 1 - End */\n+\n+\t\tuint64_t ptr:64;\n+\t\t/* Word 2 - End */\n+\n+\t\tuint64_t reserved_192_255:64;\n+\t\t/* Word 3 - End */\n+\t} s;\n+};\n+\n int otx2_dpi_queue_open(uint16_t vf_id, uint32_t size, uint32_t gaura);\n int otx2_dpi_queue_close(uint16_t vf_id);\n \n",
    "prefixes": [
        "v1",
        "4/9"
    ]
}