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GET /api/patches/53991/?format=api
HTTP 200 OK
Allow: GET, PUT, PATCH, HEAD, OPTIONS
Content-Type: application/json
Vary: Accept

{
    "id": 53991,
    "url": "http://patches.dpdk.org/api/patches/53991/?format=api",
    "web_url": "http://patches.dpdk.org/project/dpdk/patch/20190601014905.45531-21-jerinj@marvell.com/",
    "project": {
        "id": 1,
        "url": "http://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<20190601014905.45531-21-jerinj@marvell.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/20190601014905.45531-21-jerinj@marvell.com",
    "date": "2019-06-01T01:48:58",
    "name": "[v2,20/27] mempool/octeontx2: add context dump support",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": true,
    "hash": "22322aeb18e2ca9dadb1a15973d9709a5bd2cc82",
    "submitter": {
        "id": 1188,
        "url": "http://patches.dpdk.org/api/people/1188/?format=api",
        "name": "Jerin Jacob Kollanukkaran",
        "email": "jerinj@marvell.com"
    },
    "delegate": {
        "id": 1,
        "url": "http://patches.dpdk.org/api/users/1/?format=api",
        "username": "tmonjalo",
        "first_name": "Thomas",
        "last_name": "Monjalon",
        "email": "thomas@monjalon.net"
    },
    "mbox": "http://patches.dpdk.org/project/dpdk/patch/20190601014905.45531-21-jerinj@marvell.com/mbox/",
    "series": [
        {
            "id": 4844,
            "url": "http://patches.dpdk.org/api/series/4844/?format=api",
            "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=4844",
            "date": "2019-06-01T01:48:38",
            "name": "OCTEON TX2 common and mempool driver",
            "version": 2,
            "mbox": "http://patches.dpdk.org/series/4844/mbox/"
        }
    ],
    "comments": "http://patches.dpdk.org/api/patches/53991/comments/",
    "check": "fail",
    "checks": "http://patches.dpdk.org/api/patches/53991/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@dpdk.org",
        "Delivered-To": "patchwork@dpdk.org",
        "Received": [
            "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 3FA8A1B9F1;\n\tSat,  1 Jun 2019 03:50:18 +0200 (CEST)",
            "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n\t[67.231.148.174]) by dpdk.org (Postfix) with ESMTP id 9C48B1B9E1\n\tfor <dev@dpdk.org>; Sat,  1 Jun 2019 03:50:14 +0200 (CEST)",
            "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n\tby mx0a-0016f401.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id\n\tx511n5Tj003398 for <dev@dpdk.org>; Fri, 31 May 2019 18:50:13 -0700",
            "from sc-exch01.marvell.com ([199.233.58.181])\n\tby mx0a-0016f401.pphosted.com with ESMTP id 2sufgn82yt-1\n\t(version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n\tfor <dev@dpdk.org>; Fri, 31 May 2019 18:50:13 -0700",
            "from SC-EXCH01.marvell.com (10.93.176.81) by SC-EXCH01.marvell.com\n\t(10.93.176.81) with Microsoft SMTP Server (TLS) id 15.0.1367.3;\n\tFri, 31 May 2019 18:50:13 -0700",
            "from maili.marvell.com (10.93.176.43) by SC-EXCH01.marvell.com\n\t(10.93.176.81) with Microsoft SMTP Server id 15.0.1367.3 via Frontend\n\tTransport; Fri, 31 May 2019 18:50:13 -0700",
            "from jerin-lab.marvell.com (jerin-lab.marvell.com [10.28.34.14])\n\tby maili.marvell.com (Postfix) with ESMTP id D0EDC3F703F;\n\tFri, 31 May 2019 18:50:11 -0700 (PDT)"
        ],
        "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n\th=from : to : cc :\n\tsubject : date : message-id : in-reply-to : references : mime-version\n\t: content-transfer-encoding : content-type; s=pfpt0818;\n\tbh=G4nlfOxso1ngdfC0SLJcrdhE4szTn8su5va4DJPtkVo=;\n\tb=s0MAO9naCzf8AVmBp24a7CfhbgtBEdudqpLL3XH0N1Rmie5cwWeOlfueYE83n6rGMttm\n\tf9MXw3EhJ7RWWy0yOq76BeCZ9xAhdKDNcsQxiZDNs1mmHf6GYxJpErAd/sjtQgPAMYVJ\n\tGjF/Cp+UtNUWVwiNuch1tGdO3RRLQP4EEufDwZkHpaJc5Qhgi59L33OHniAPyFHFV1IQ\n\tb1z80rWQItn8cyYzupmTxlp8WLrMY+xVbvhQ6ne4kWRN0tvX3GJgTTv12IrKFbegtw+m\n\tIWNS+89BYqWOcv6BBZmTr1sGjpeAw2RQsDanoePAMdLMN+6bUz38SmsdobiPuMwmFs1r\n\tZg== ",
        "From": "<jerinj@marvell.com>",
        "To": "<dev@dpdk.org>, Jerin Jacob <jerinj@marvell.com>, Nithin Dabilpuram\n\t<ndabilpuram@marvell.com>, Vamsi Attunuru <vattunuru@marvell.com>",
        "CC": "Vivek Sharma <viveksharma@marvell.com>",
        "Date": "Sat, 1 Jun 2019 07:18:58 +0530",
        "Message-ID": "<20190601014905.45531-21-jerinj@marvell.com>",
        "X-Mailer": "git-send-email 2.21.0",
        "In-Reply-To": "<20190601014905.45531-1-jerinj@marvell.com>",
        "References": "<20190523081339.56348-1-jerinj@marvell.com>\n\t<20190601014905.45531-1-jerinj@marvell.com>",
        "MIME-Version": "1.0",
        "Content-Transfer-Encoding": "8bit",
        "Content-Type": "text/plain",
        "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:, ,\n\tdefinitions=2019-06-01_02:, , signatures=0",
        "Subject": "[dpdk-dev] [PATCH v2 20/27] mempool/octeontx2: add context dump\n\tsupport",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.15",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "From: Jerin Jacob <jerinj@marvell.com>\n\nAdd a helper function to dump aura and pool context for NPA debugging.\n\nSigned-off-by: Jerin Jacob <jerinj@marvell.com>\nSigned-off-by: Vivek Sharma <viveksharma@marvell.com>\n---\n drivers/mempool/octeontx2/Makefile            |   3 +-\n drivers/mempool/octeontx2/meson.build         |   1 +\n drivers/mempool/octeontx2/otx2_mempool.h      |   3 +\n .../mempool/octeontx2/otx2_mempool_debug.c    | 135 ++++++++++++++++++\n drivers/mempool/octeontx2/otx2_mempool_irq.c  |   1 +\n 5 files changed, 142 insertions(+), 1 deletion(-)\n create mode 100644 drivers/mempool/octeontx2/otx2_mempool_debug.c",
    "diff": "diff --git a/drivers/mempool/octeontx2/Makefile b/drivers/mempool/octeontx2/Makefile\nindex 86950b270..b86d469f4 100644\n--- a/drivers/mempool/octeontx2/Makefile\n+++ b/drivers/mempool/octeontx2/Makefile\n@@ -29,7 +29,8 @@ LIBABIVER := 1\n #\n SRCS-$(CONFIG_RTE_LIBRTE_OCTEONTX2_MEMPOOL) += \\\n \totx2_mempool.c \t\t\\\n-\totx2_mempool_irq.c\n+\totx2_mempool_irq.c\t\\\n+\totx2_mempool_debug.c\n \n LDLIBS += -lrte_eal -lrte_mempool -lrte_mbuf\n LDLIBS += -lrte_common_octeontx2 -lrte_kvargs -lrte_bus_pci\ndiff --git a/drivers/mempool/octeontx2/meson.build b/drivers/mempool/octeontx2/meson.build\nindex 3f93b509d..ab306b729 100644\n--- a/drivers/mempool/octeontx2/meson.build\n+++ b/drivers/mempool/octeontx2/meson.build\n@@ -4,6 +4,7 @@\n \n sources = files('otx2_mempool.c',\n \t\t'otx2_mempool_irq.c',\n+\t\t'otx2_mempool_debug.c'\n \t\t)\n \n extra_flags = []\ndiff --git a/drivers/mempool/octeontx2/otx2_mempool.h b/drivers/mempool/octeontx2/otx2_mempool.h\nindex 41542cf89..efaa308b3 100644\n--- a/drivers/mempool/octeontx2/otx2_mempool.h\n+++ b/drivers/mempool/octeontx2/otx2_mempool.h\n@@ -202,4 +202,7 @@ int otx2_npa_lf_fini(void);\n int otx2_npa_register_irqs(struct otx2_npa_lf *lf);\n void otx2_npa_unregister_irqs(struct otx2_npa_lf *lf);\n \n+/* Debug */\n+int otx2_mempool_ctx_dump(struct otx2_npa_lf *lf);\n+\n #endif /* __OTX2_MEMPOOL_H__ */\ndiff --git a/drivers/mempool/octeontx2/otx2_mempool_debug.c b/drivers/mempool/octeontx2/otx2_mempool_debug.c\nnew file mode 100644\nindex 000000000..eef61ef07\n--- /dev/null\n+++ b/drivers/mempool/octeontx2/otx2_mempool_debug.c\n@@ -0,0 +1,135 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2019 Marvell International Ltd.\n+ */\n+\n+#include \"otx2_mempool.h\"\n+\n+#define npa_dump(fmt, ...) fprintf(stderr, fmt \"\\n\", ##__VA_ARGS__)\n+\n+static inline void\n+npa_lf_pool_dump(struct npa_pool_s *pool)\n+{\n+\tnpa_dump(\"W0: Stack base\\t\\t0x%\"PRIx64\"\", pool->stack_base);\n+\tnpa_dump(\"W1: ena \\t\\t%d\\nW1: nat_align \\t\\t%d\\nW1: stack_caching \\t%d\",\n+\t\tpool->ena, pool->nat_align, pool->stack_caching);\n+\tnpa_dump(\"W1: stack_way_mask\\t%d\\nW1: buf_offset\\t\\t%d\",\n+\t\tpool->stack_way_mask, pool->buf_offset);\n+\tnpa_dump(\"W1: buf_size \\t\\t%d\", pool->buf_size);\n+\n+\tnpa_dump(\"W2: stack_max_pages \\t%d\\nW2: stack_pages\\t\\t%d\",\n+\t\tpool->stack_max_pages, pool->stack_pages);\n+\n+\tnpa_dump(\"W3: op_pc \\t\\t0x%\"PRIx64\"\", (uint64_t)pool->op_pc);\n+\n+\tnpa_dump(\"W4: stack_offset\\t%d\\nW4: shift\\t\\t%d\\nW4: avg_level\\t\\t%d\",\n+\t\tpool->stack_offset, pool->shift, pool->avg_level);\n+\tnpa_dump(\"W4: avg_con \\t\\t%d\\nW4: fc_ena\\t\\t%d\\nW4: fc_stype\\t\\t%d\",\n+\t\tpool->avg_con, pool->fc_ena, pool->fc_stype);\n+\tnpa_dump(\"W4: fc_hyst_bits\\t%d\\nW4: fc_up_crossing\\t%d\",\n+\t\tpool->fc_hyst_bits, pool->fc_up_crossing);\n+\tnpa_dump(\"W4: update_time\\t\\t%d\\n\", pool->update_time);\n+\n+\tnpa_dump(\"W5: fc_addr\\t\\t0x%\"PRIx64\"\\n\", pool->fc_addr);\n+\n+\tnpa_dump(\"W6: ptr_start\\t\\t0x%\"PRIx64\"\\n\", pool->ptr_start);\n+\n+\tnpa_dump(\"W7: ptr_end\\t\\t0x%\"PRIx64\"\\n\", pool->ptr_end);\n+\tnpa_dump(\"W8: err_int\\t\\t%d\\nW8: err_int_ena\\t\\t%d\",\n+\t\tpool->err_int, pool->err_int_ena);\n+\tnpa_dump(\"W8: thresh_int\\t\\t%d\", pool->thresh_int);\n+\n+\tnpa_dump(\"W8: thresh_int_ena\\t%d\\nW8: thresh_up\\t\\t%d\",\n+\t\tpool->thresh_int_ena, pool->thresh_up);\n+\tnpa_dump(\"W8: thresh_qint_idx\\t%d\\nW8: err_qint_idx\\t%d\",\n+\t\tpool->thresh_qint_idx, pool->err_qint_idx);\n+}\n+\n+static inline void\n+npa_lf_aura_dump(struct npa_aura_s *aura)\n+{\n+\tnpa_dump(\"W0: Pool addr\\t\\t0x%\"PRIx64\"\\n\", aura->pool_addr);\n+\n+\tnpa_dump(\"W1: ena\\t\\t\\t%d\\nW1: pool caching\\t%d\\nW1: pool way mask\\t%d\",\n+\t\taura->ena, aura->pool_caching, aura->pool_way_mask);\n+\tnpa_dump(\"W1: avg con\\t\\t%d\\nW1: pool drop ena\\t%d\",\n+\t\taura->avg_con, aura->pool_drop_ena);\n+\tnpa_dump(\"W1: aura drop ena\\t%d\", aura->aura_drop_ena);\n+\tnpa_dump(\"W1: bp_ena\\t\\t%d\\nW1: aura drop\\t\\t%d\\nW1: aura shift\\t\\t%d\",\n+\t\taura->bp_ena, aura->aura_drop, aura->shift);\n+\tnpa_dump(\"W1: avg_level\\t\\t%d\\n\", aura->avg_level);\n+\n+\tnpa_dump(\"W2: count\\t\\t%\"PRIx64\"\\nW2: nix0_bpid\\t\\t%d\",\n+\t\t(uint64_t)aura->count, aura->nix0_bpid);\n+\tnpa_dump(\"W2: nix1_bpid\\t\\t%d\", aura->nix1_bpid);\n+\n+\tnpa_dump(\"W3: limit\\t\\t%\"PRIx64\"\\nW3: bp\\t\\t\\t%d\\nW3: fc_ena\\t\\t%d\\n\",\n+\t\t(uint64_t)aura->limit, aura->bp, aura->fc_ena);\n+\tnpa_dump(\"W3: fc_up_crossing\\t%d\\nW3: fc_stype\\t\\t%d\",\n+\t\taura->fc_up_crossing, aura->fc_stype);\n+\n+\tnpa_dump(\"W3: fc_hyst_bits\\t%d\", aura->fc_hyst_bits);\n+\n+\tnpa_dump(\"W4: fc_addr\\t\\t0x%\"PRIx64\"\\n\", aura->fc_addr);\n+\n+\tnpa_dump(\"W5: pool_drop\\t\\t%d\\nW5: update_time\\t\\t%d\",\n+\t\taura->pool_drop, aura->update_time);\n+\tnpa_dump(\"W5: err_int\\t\\t%d\",  aura->err_int);\n+\tnpa_dump(\"W5: err_int_ena\\t\\t%d\\nW5: thresh_int\\t\\t%d\",\n+\t\taura->err_int_ena, aura->thresh_int);\n+\tnpa_dump(\"W5: thresh_int_ena\\t%d\", aura->thresh_int_ena);\n+\n+\tnpa_dump(\"W5: thresh_up\\t\\t%d\\nW5: thresh_qint_idx\\t%d\",\n+\t\taura->thresh_up, aura->thresh_qint_idx);\n+\tnpa_dump(\"W5: err_qint_idx\\t%d\", aura->err_qint_idx);\n+\n+\tnpa_dump(\"W6: thresh\\t\\t%\"PRIx64\"\\n\", (uint64_t)aura->thresh);\n+}\n+\n+int\n+otx2_mempool_ctx_dump(struct otx2_npa_lf *lf)\n+{\n+\tstruct npa_aq_enq_req *aq;\n+\tstruct npa_aq_enq_rsp *rsp;\n+\tuint32_t q;\n+\tint rc;\n+\n+\tfor (q = 0; q < lf->nr_pools; q++) {\n+\t\t/* Skip disabled POOL */\n+\t\tif (rte_bitmap_get(lf->npa_bmp, q))\n+\t\t\tcontinue;\n+\n+\t\taq = otx2_mbox_alloc_msg_npa_aq_enq(lf->mbox);\n+\t\taq->aura_id = q;\n+\t\taq->ctype = NPA_AQ_CTYPE_POOL;\n+\t\taq->op = NPA_AQ_INSTOP_READ;\n+\n+\t\trc = otx2_mbox_process_msg(lf->mbox, (void *)&rsp);\n+\t\tif (rc) {\n+\t\t\totx2_err(\"Failed to get pool(%d) context\", q);\n+\t\t\treturn rc;\n+\t\t}\n+\t\tnpa_dump(\"============== pool=%d ===============\\n\", q);\n+\t\tnpa_lf_pool_dump(&rsp->pool);\n+\t}\n+\n+\tfor (q = 0; q < lf->nr_pools; q++) {\n+\t\t/* Skip disabled AURA */\n+\t\tif (rte_bitmap_get(lf->npa_bmp, q))\n+\t\t\tcontinue;\n+\n+\t\taq = otx2_mbox_alloc_msg_npa_aq_enq(lf->mbox);\n+\t\taq->aura_id = q;\n+\t\taq->ctype = NPA_AQ_CTYPE_AURA;\n+\t\taq->op = NPA_AQ_INSTOP_READ;\n+\n+\t\trc = otx2_mbox_process_msg(lf->mbox, (void *)&rsp);\n+\t\tif (rc) {\n+\t\t\totx2_err(\"Failed to get aura(%d) context\", q);\n+\t\t\treturn rc;\n+\t\t}\n+\t\tnpa_dump(\"============== aura=%d ===============\\n\", q);\n+\t\tnpa_lf_aura_dump(&rsp->aura);\n+\t}\n+\n+\treturn rc;\n+}\ndiff --git a/drivers/mempool/octeontx2/otx2_mempool_irq.c b/drivers/mempool/octeontx2/otx2_mempool_irq.c\nindex 510d3e994..f8a01a696 100644\n--- a/drivers/mempool/octeontx2/otx2_mempool_irq.c\n+++ b/drivers/mempool/octeontx2/otx2_mempool_irq.c\n@@ -203,6 +203,7 @@ npa_lf_q_irq(void *param)\n \n \t/* Clear interrupt */\n \totx2_write64(intr, lf->base + NPA_LF_QINTX_INT(qintx));\n+\totx2_mempool_ctx_dump(lf);\n \trte_panic(\"npa_lf_q_interrupt\\n\");\n }\n \n",
    "prefixes": [
        "v2",
        "20/27"
    ]
}