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GET /api/patches/53983/?format=api
{ "id": 53983, "url": "http://patches.dpdk.org/api/patches/53983/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20190601014905.45531-13-jerinj@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20190601014905.45531-13-jerinj@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20190601014905.45531-13-jerinj@marvell.com", "date": "2019-06-01T01:48:50", "name": "[v2,12/27] common/octeontx2: add VF mailbox IRQ and msg handler", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "a040aea51b542ee401723612a085f909eb6a772a", "submitter": { "id": 1188, "url": "http://patches.dpdk.org/api/people/1188/?format=api", "name": "Jerin Jacob Kollanukkaran", "email": "jerinj@marvell.com" }, "delegate": { "id": 1, "url": "http://patches.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20190601014905.45531-13-jerinj@marvell.com/mbox/", "series": [ { "id": 4844, "url": "http://patches.dpdk.org/api/series/4844/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=4844", "date": "2019-06-01T01:48:38", "name": "OCTEON TX2 common and mempool driver", "version": 2, "mbox": "http://patches.dpdk.org/series/4844/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/53983/comments/", "check": "fail", "checks": "http://patches.dpdk.org/api/patches/53983/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 80C8B1B996;\n\tSat, 1 Jun 2019 03:49:53 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n\t[67.231.156.173]) by dpdk.org (Postfix) with ESMTP id 9806E1B9C2\n\tfor <dev@dpdk.org>; Sat, 1 Jun 2019 03:49:51 +0200 (CEST)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n\tby mx0b-0016f401.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id\n\tx511lrtJ003370 for <dev@dpdk.org>; Fri, 31 May 2019 18:49:50 -0700", "from sc-exch01.marvell.com ([199.233.58.181])\n\tby mx0b-0016f401.pphosted.com with ESMTP id 2su5xh2buc-1\n\t(version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n\tfor <dev@dpdk.org>; Fri, 31 May 2019 18:49:50 -0700", "from SC-EXCH03.marvell.com (10.93.176.83) by SC-EXCH01.marvell.com\n\t(10.93.176.81) with Microsoft SMTP Server (TLS) id 15.0.1367.3;\n\tFri, 31 May 2019 18:49:48 -0700", "from maili.marvell.com (10.93.176.43) by SC-EXCH03.marvell.com\n\t(10.93.176.83) with Microsoft SMTP Server id 15.0.1367.3 via Frontend\n\tTransport; Fri, 31 May 2019 18:49:48 -0700", "from jerin-lab.marvell.com (jerin-lab.marvell.com [10.28.34.14])\n\tby maili.marvell.com (Postfix) with ESMTP id 89AE53F703F;\n\tFri, 31 May 2019 18:49:47 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n\th=from : to : subject\n\t: date : message-id : in-reply-to : references : mime-version :\n\tcontent-transfer-encoding : content-type; s=pfpt0818;\n\tbh=WAl8SU44vpOIw1JhEAKYSSMa6ZtwUo132f7v5ZDp5Hc=;\n\tb=euJ3KmY2iG7i9WykGjxKocUCFKFIadYhJrxgOeJmMsdQgBwrp1aKH+WxfIliXapcCamQ\n\thyCm1gRxJikw/llZrL2cKRpeAsZiPJeXzHNqwfnogewknUxnoLfwQacuyR2q/noPWQdE\n\tRPnDYYa/hirhYhNsUYeBDA12LuZhQn4R/mBdaDLgdwLkZ7A9v+MCe1y+crKexVgmgHno\n\t7D81hSyUc5/kcYIjKm3HrxLtYZKc3OggFOIgwVaig1Q87OWx8JAw2+ciJ+eLgzQW5u++\n\tq/yNrFGYkxUx98t99L5bEgVO4vxi8OQ3i6AKFTkMuDA/5l8Zc8I8IY68O7JlMWPpSDal\n\tdQ== ", "From": "<jerinj@marvell.com>", "To": "<dev@dpdk.org>, Jerin Jacob <jerinj@marvell.com>, Nithin Dabilpuram\n\t<ndabilpuram@marvell.com>, Vamsi Attunuru <vattunuru@marvell.com>", "Date": "Sat, 1 Jun 2019 07:18:50 +0530", "Message-ID": "<20190601014905.45531-13-jerinj@marvell.com>", "X-Mailer": "git-send-email 2.21.0", "In-Reply-To": "<20190601014905.45531-1-jerinj@marvell.com>", "References": "<20190523081339.56348-1-jerinj@marvell.com>\n\t<20190601014905.45531-1-jerinj@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:, ,\n\tdefinitions=2019-06-01_02:, , signatures=0", "Subject": "[dpdk-dev] [PATCH v2 12/27] common/octeontx2: add VF mailbox IRQ\n\tand msg handler", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Jerin Jacob <jerinj@marvell.com>\n\nThis patch adds support for PF <-> VF mailbox interrupt\nmailbox message interrupt handling.\n\nSigned-off-by: Jerin Jacob <jerinj@marvell.com>\n---\n drivers/common/octeontx2/otx2_dev.c | 78 ++++++++++++++++++++++++++++-\n 1 file changed, 76 insertions(+), 2 deletions(-)", "diff": "diff --git a/drivers/common/octeontx2/otx2_dev.c b/drivers/common/octeontx2/otx2_dev.c\nindex 09b551819..fc6dca624 100644\n--- a/drivers/common/octeontx2/otx2_dev.c\n+++ b/drivers/common/octeontx2/otx2_dev.c\n@@ -291,6 +291,24 @@ otx2_process_msgs(struct otx2_dev *dev, struct otx2_mbox *mbox)\n \trte_wmb();\n }\n \n+static void\n+otx2_pf_vf_mbox_irq(void *param)\n+{\n+\tstruct otx2_dev *dev = param;\n+\tuint64_t intr;\n+\n+\tintr = otx2_read64(dev->bar2 + RVU_VF_INT);\n+\tif (intr == 0)\n+\t\treturn;\n+\n+\totx2_write64(intr, dev->bar2 + RVU_VF_INT);\n+\totx2_base_dbg(\"Irq 0x%\" PRIx64 \"(pf:%d,vf:%d)\", intr, dev->pf, dev->vf);\n+\tif (intr)\n+\t\t/* First process all configuration messages */\n+\t\totx2_process_msgs(dev, dev->mbox);\n+\n+}\n+\n static void\n otx2_af_pf_mbox_irq(void *param)\n {\n@@ -310,7 +328,7 @@ otx2_af_pf_mbox_irq(void *param)\n }\n \n static int\n-mbox_register_irq(struct rte_pci_device *pci_dev, struct otx2_dev *dev)\n+mbox_register_pf_irq(struct rte_pci_device *pci_dev, struct otx2_dev *dev)\n {\n \tstruct rte_intr_handle *intr_handle = &pci_dev->intr_handle;\n \tint i, rc;\n@@ -359,8 +377,41 @@ mbox_register_irq(struct rte_pci_device *pci_dev, struct otx2_dev *dev)\n \treturn rc;\n }\n \n+static int\n+mbox_register_vf_irq(struct rte_pci_device *pci_dev, struct otx2_dev *dev)\n+{\n+\tstruct rte_intr_handle *intr_handle = &pci_dev->intr_handle;\n+\tint rc;\n+\n+\t/* Clear irq */\n+\totx2_write64(~0ull, dev->bar2 + RVU_VF_INT_ENA_W1C);\n+\n+\t/* MBOX interrupt PF <-> VF */\n+\trc = otx2_register_irq(intr_handle, otx2_pf_vf_mbox_irq,\n+\t\t\t dev, RVU_VF_INT_VEC_MBOX);\n+\tif (rc) {\n+\t\totx2_err(\"Fail to register PF<->VF mbox irq\");\n+\t\treturn rc;\n+\t}\n+\n+\t/* HW enable intr */\n+\totx2_write64(~0ull, dev->bar2 + RVU_VF_INT);\n+\totx2_write64(~0ull, dev->bar2 + RVU_VF_INT_ENA_W1S);\n+\n+\treturn rc;\n+}\n+\n+static int\n+mbox_register_irq(struct rte_pci_device *pci_dev, struct otx2_dev *dev)\n+{\n+\tif (otx2_dev_is_vf(dev))\n+\t\treturn mbox_register_vf_irq(pci_dev, dev);\n+\telse\n+\t\treturn mbox_register_pf_irq(pci_dev, dev);\n+}\n+\n static void\n-mbox_unregister_irq(struct rte_pci_device *pci_dev, struct otx2_dev *dev)\n+mbox_unregister_pf_irq(struct rte_pci_device *pci_dev, struct otx2_dev *dev)\n {\n \tstruct rte_intr_handle *intr_handle = &pci_dev->intr_handle;\n \tint i;\n@@ -388,6 +439,29 @@ mbox_unregister_irq(struct rte_pci_device *pci_dev, struct otx2_dev *dev)\n \t/* MBOX interrupt AF <-> PF */\n \totx2_unregister_irq(intr_handle, otx2_af_pf_mbox_irq, dev,\n \t\t\t RVU_PF_INT_VEC_AFPF_MBOX);\n+\n+}\n+\n+static void\n+mbox_unregister_vf_irq(struct rte_pci_device *pci_dev, struct otx2_dev *dev)\n+{\n+\tstruct rte_intr_handle *intr_handle = &pci_dev->intr_handle;\n+\n+\t/* Clear irq */\n+\totx2_write64(~0ull, dev->bar2 + RVU_VF_INT_ENA_W1C);\n+\n+\t/* Unregister the interrupt handler */\n+\totx2_unregister_irq(intr_handle, otx2_pf_vf_mbox_irq, dev,\n+\t\t\t RVU_VF_INT_VEC_MBOX);\n+}\n+\n+static void\n+mbox_unregister_irq(struct rte_pci_device *pci_dev, struct otx2_dev *dev)\n+{\n+\tif (otx2_dev_is_vf(dev))\n+\t\treturn mbox_unregister_vf_irq(pci_dev, dev);\n+\telse\n+\t\treturn mbox_unregister_pf_irq(pci_dev, dev);\n }\n \n static void\n", "prefixes": [ "v2", "12/27" ] }