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GET /api/patches/53979/?format=api
HTTP 200 OK
Allow: GET, PUT, PATCH, HEAD, OPTIONS
Content-Type: application/json
Vary: Accept

{
    "id": 53979,
    "url": "http://patches.dpdk.org/api/patches/53979/?format=api",
    "web_url": "http://patches.dpdk.org/project/dpdk/patch/20190601014905.45531-9-jerinj@marvell.com/",
    "project": {
        "id": 1,
        "url": "http://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<20190601014905.45531-9-jerinj@marvell.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/20190601014905.45531-9-jerinj@marvell.com",
    "date": "2019-06-01T01:48:46",
    "name": "[v2,08/27] common/octeontx2: introduce irq handling functions",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": true,
    "hash": "ed197e2a58cc627b9b6d2b5e4e040ac3d7be008e",
    "submitter": {
        "id": 1188,
        "url": "http://patches.dpdk.org/api/people/1188/?format=api",
        "name": "Jerin Jacob Kollanukkaran",
        "email": "jerinj@marvell.com"
    },
    "delegate": {
        "id": 1,
        "url": "http://patches.dpdk.org/api/users/1/?format=api",
        "username": "tmonjalo",
        "first_name": "Thomas",
        "last_name": "Monjalon",
        "email": "thomas@monjalon.net"
    },
    "mbox": "http://patches.dpdk.org/project/dpdk/patch/20190601014905.45531-9-jerinj@marvell.com/mbox/",
    "series": [
        {
            "id": 4844,
            "url": "http://patches.dpdk.org/api/series/4844/?format=api",
            "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=4844",
            "date": "2019-06-01T01:48:38",
            "name": "OCTEON TX2 common and mempool driver",
            "version": 2,
            "mbox": "http://patches.dpdk.org/series/4844/mbox/"
        }
    ],
    "comments": "http://patches.dpdk.org/api/patches/53979/comments/",
    "check": "fail",
    "checks": "http://patches.dpdk.org/api/patches/53979/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@dpdk.org",
        "Delivered-To": "patchwork@dpdk.org",
        "Received": [
            "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 21B601B99F;\n\tSat,  1 Jun 2019 03:49:42 +0200 (CEST)",
            "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n\t[67.231.148.174]) by dpdk.org (Postfix) with ESMTP id 013FD1B9A8\n\tfor <dev@dpdk.org>; Sat,  1 Jun 2019 03:49:39 +0200 (CEST)",
            "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n\tby mx0a-0016f401.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id\n\tx511n5Tg003398 for <dev@dpdk.org>; Fri, 31 May 2019 18:49:39 -0700",
            "from sc-exch01.marvell.com ([199.233.58.181])\n\tby mx0a-0016f401.pphosted.com with ESMTP id 2sufgn82wa-1\n\t(version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n\tfor <dev@dpdk.org>; Fri, 31 May 2019 18:49:39 -0700",
            "from SC-EXCH03.marvell.com (10.93.176.83) by SC-EXCH01.marvell.com\n\t(10.93.176.81) with Microsoft SMTP Server (TLS) id 15.0.1367.3;\n\tFri, 31 May 2019 18:49:38 -0700",
            "from maili.marvell.com (10.93.176.43) by SC-EXCH03.marvell.com\n\t(10.93.176.83) with Microsoft SMTP Server id 15.0.1367.3 via Frontend\n\tTransport; Fri, 31 May 2019 18:49:38 -0700",
            "from jerin-lab.marvell.com (jerin-lab.marvell.com [10.28.34.14])\n\tby maili.marvell.com (Postfix) with ESMTP id B946F3F703F;\n\tFri, 31 May 2019 18:49:36 -0700 (PDT)"
        ],
        "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n\th=from : to : cc :\n\tsubject : date : message-id : in-reply-to : references : mime-version\n\t: content-transfer-encoding : content-type; s=pfpt0818;\n\tbh=lrLmQDJXx2xyswvixYurPpVAvQW37cMnXLh9xIhjRNc=;\n\tb=qg0aOJrxKnEOwxIDZ7TxwWu2PhOihDLQgbW0vkHfcpzWTpFgktU2JmGFj8pPt6SAe+X8\n\tXURh1rZN0Bq0jq5AD2GYGKT2NK2esxyNvFg98iVFoZsjZ8wmjhYBaUSyXLPvMdfGMytf\n\tN0ikgWE+877H21eCITd4n6TPdz2DhHKWAPBQOO4tPS06KUtGup1nQVpuudUqPNh8nwuA\n\t1QQBqQgCAjl1+PUG7mLJJTr7pOIkkMzP+Dn7t0tPku2Fni+T8dd52CwMH1FJ45D9EY/d\n\ti0/YNw9FuPTLZ1dKHVgsNatSnNveHrz0kcwfTMvaFisZYuYPpGwrLtnidXnhX4LCVImu\n\t5Q== ",
        "From": "<jerinj@marvell.com>",
        "To": "<dev@dpdk.org>, Jerin Jacob <jerinj@marvell.com>, Nithin Dabilpuram\n\t<ndabilpuram@marvell.com>, Vamsi Attunuru <vattunuru@marvell.com>",
        "CC": "Krzysztof Kanas <kkanas@marvell.com>",
        "Date": "Sat, 1 Jun 2019 07:18:46 +0530",
        "Message-ID": "<20190601014905.45531-9-jerinj@marvell.com>",
        "X-Mailer": "git-send-email 2.21.0",
        "In-Reply-To": "<20190601014905.45531-1-jerinj@marvell.com>",
        "References": "<20190523081339.56348-1-jerinj@marvell.com>\n\t<20190601014905.45531-1-jerinj@marvell.com>",
        "MIME-Version": "1.0",
        "Content-Transfer-Encoding": "8bit",
        "Content-Type": "text/plain",
        "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:, ,\n\tdefinitions=2019-06-01_02:, , signatures=0",
        "Subject": "[dpdk-dev] [PATCH v2 08/27] common/octeontx2: introduce irq\n\thandling functions",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.15",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "From: Jerin Jacob <jerinj@marvell.com>\n\nAll PCIe drivers(ethdev, mempool, cryptodev and eventdev) in octeontx2,\nneeds to handle interrupt for mailbox and error handling.\nCreate a helper function over rte interrupt API to register,\nunregister, disable interrupts.\n\nSigned-off-by: Jerin Jacob <jerinj@marvell.com>\nSigned-off-by: Vamsi Attunuru <vattunuru@marvell.com>\nSigned-off-by: Krzysztof Kanas <kkanas@marvell.com>\n---\n drivers/common/octeontx2/Makefile             |   1 +\n drivers/common/octeontx2/meson.build          |   1 +\n drivers/common/octeontx2/otx2_irq.c           | 254 ++++++++++++++++++\n drivers/common/octeontx2/otx2_irq.h           |   6 +\n .../rte_common_octeontx2_version.map          |   4 +\n 5 files changed, 266 insertions(+)\n create mode 100644 drivers/common/octeontx2/otx2_irq.c",
    "diff": "diff --git a/drivers/common/octeontx2/Makefile b/drivers/common/octeontx2/Makefile\nindex a6f94553d..78243e555 100644\n--- a/drivers/common/octeontx2/Makefile\n+++ b/drivers/common/octeontx2/Makefile\n@@ -26,6 +26,7 @@ LIBABIVER := 1\n # all source are stored in SRCS-y\n #\n SRCS-y += otx2_dev.c\n+SRCS-y += otx2_irq.c\n SRCS-y += otx2_mbox.c\n SRCS-y += otx2_common.c\n \ndiff --git a/drivers/common/octeontx2/meson.build b/drivers/common/octeontx2/meson.build\nindex feaf75d92..44ac90085 100644\n--- a/drivers/common/octeontx2/meson.build\n+++ b/drivers/common/octeontx2/meson.build\n@@ -3,6 +3,7 @@\n #\n \n sources= files('otx2_dev.c',\n+\t\t'otx2_irq.c',\n \t\t'otx2_mbox.c',\n \t\t'otx2_common.c',\n \t       )\ndiff --git a/drivers/common/octeontx2/otx2_irq.c b/drivers/common/octeontx2/otx2_irq.c\nnew file mode 100644\nindex 000000000..fa3206af5\n--- /dev/null\n+++ b/drivers/common/octeontx2/otx2_irq.c\n@@ -0,0 +1,254 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2019 Marvell International Ltd.\n+ */\n+\n+#include <rte_alarm.h>\n+#include <rte_common.h>\n+#include <rte_eal.h>\n+#include <rte_interrupts.h>\n+\n+#include \"otx2_common.h\"\n+#include \"otx2_irq.h\"\n+\n+#ifdef RTE_EAL_VFIO\n+\n+#include <inttypes.h>\n+#include <linux/vfio.h>\n+#include <sys/eventfd.h>\n+#include <sys/ioctl.h>\n+#include <unistd.h>\n+\n+#define MAX_INTR_VEC_ID RTE_MAX_RXTX_INTR_VEC_ID\n+#define MSIX_IRQ_SET_BUF_LEN (sizeof(struct vfio_irq_set) + \\\n+\t\t\t      sizeof(int) * (MAX_INTR_VEC_ID))\n+\n+static int\n+irq_get_info(struct rte_intr_handle *intr_handle)\n+{\n+\tstruct vfio_irq_info irq = { .argsz = sizeof(irq) };\n+\tint rc;\n+\n+\tirq.index = VFIO_PCI_MSIX_IRQ_INDEX;\n+\n+\trc = ioctl(intr_handle->vfio_dev_fd, VFIO_DEVICE_GET_IRQ_INFO, &irq);\n+\tif (rc < 0) {\n+\t\totx2_err(\"Failed to get IRQ info rc=%d errno=%d\", rc, errno);\n+\t\treturn rc;\n+\t}\n+\n+\totx2_base_dbg(\"Flags=0x%x index=0x%x count=0x%x max_intr_vec_id=0x%x\",\n+\t\t      irq.flags, irq.index, irq.count, MAX_INTR_VEC_ID);\n+\n+\tif (irq.count > MAX_INTR_VEC_ID) {\n+\t\totx2_err(\"HW max=%d > MAX_INTR_VEC_ID: %d\",\n+\t\t\t intr_handle->max_intr, MAX_INTR_VEC_ID);\n+\t\tintr_handle->max_intr = MAX_INTR_VEC_ID;\n+\t} else {\n+\t\tintr_handle->max_intr = irq.count;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int\n+irq_config(struct rte_intr_handle *intr_handle, unsigned int vec)\n+{\n+\tchar irq_set_buf[MSIX_IRQ_SET_BUF_LEN];\n+\tstruct vfio_irq_set *irq_set;\n+\tint32_t *fd_ptr;\n+\tint len, rc;\n+\n+\tif (vec > intr_handle->max_intr) {\n+\t\totx2_err(\"vector=%d greater than max_intr=%d\", vec,\n+\t\t\t\tintr_handle->max_intr);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tlen = sizeof(struct vfio_irq_set) + sizeof(int32_t);\n+\n+\tirq_set = (struct vfio_irq_set *)irq_set_buf;\n+\tirq_set->argsz = len;\n+\n+\tirq_set->start = vec;\n+\tirq_set->count = 1;\n+\tirq_set->flags = VFIO_IRQ_SET_DATA_EVENTFD |\n+\t\t\tVFIO_IRQ_SET_ACTION_TRIGGER;\n+\tirq_set->index = VFIO_PCI_MSIX_IRQ_INDEX;\n+\n+\t/* Use vec fd to set interrupt vectors */\n+\tfd_ptr = (int32_t *)&irq_set->data[0];\n+\tfd_ptr[0] = intr_handle->efds[vec];\n+\n+\trc = ioctl(intr_handle->vfio_dev_fd, VFIO_DEVICE_SET_IRQS, irq_set);\n+\tif (rc)\n+\t\totx2_err(\"Failed to set_irqs vector=0x%x rc=%d\", vec, rc);\n+\n+\treturn rc;\n+}\n+\n+static int\n+irq_init(struct rte_intr_handle *intr_handle)\n+{\n+\tchar irq_set_buf[MSIX_IRQ_SET_BUF_LEN];\n+\tstruct vfio_irq_set *irq_set;\n+\tint32_t *fd_ptr;\n+\tint len, rc;\n+\tuint32_t i;\n+\n+\tif (intr_handle->max_intr > MAX_INTR_VEC_ID) {\n+\t\totx2_err(\"Max_intr=%d greater than MAX_INTR_VEC_ID=%d\",\n+\t\t\t\tintr_handle->max_intr, MAX_INTR_VEC_ID);\n+\t\treturn -ERANGE;\n+\t}\n+\n+\tlen = sizeof(struct vfio_irq_set) +\n+\t\tsizeof(int32_t) * intr_handle->max_intr;\n+\n+\tirq_set = (struct vfio_irq_set *)irq_set_buf;\n+\tirq_set->argsz = len;\n+\tirq_set->start = 0;\n+\tirq_set->count = intr_handle->max_intr;\n+\tirq_set->flags = VFIO_IRQ_SET_DATA_EVENTFD |\n+\t\t\tVFIO_IRQ_SET_ACTION_TRIGGER;\n+\tirq_set->index = VFIO_PCI_MSIX_IRQ_INDEX;\n+\n+\tfd_ptr = (int32_t *)&irq_set->data[0];\n+\tfor (i = 0; i < irq_set->count; i++)\n+\t\tfd_ptr[i] = -1;\n+\n+\trc = ioctl(intr_handle->vfio_dev_fd, VFIO_DEVICE_SET_IRQS, irq_set);\n+\tif (rc)\n+\t\totx2_err(\"Failed to set irqs vector rc=%d\", rc);\n+\n+\treturn rc;\n+}\n+\n+/**\n+ * @internal\n+ * Disable IRQ\n+ */\n+int\n+otx2_disable_irqs(struct rte_intr_handle *intr_handle)\n+{\n+\t/* Clear max_intr to indicate re-init next time */\n+\tintr_handle->max_intr = 0;\n+\treturn rte_intr_disable(intr_handle);\n+}\n+\n+/**\n+ * @internal\n+ * Register IRQ\n+ */\n+int\n+otx2_register_irq(struct rte_intr_handle *intr_handle,\n+\t\t  rte_intr_callback_fn cb, void *data, unsigned int vec)\n+{\n+\tstruct rte_intr_handle tmp_handle;\n+\tint rc;\n+\n+\t/* If no max_intr read from VFIO */\n+\tif (intr_handle->max_intr == 0) {\n+\t\tirq_get_info(intr_handle);\n+\t\tirq_init(intr_handle);\n+\t}\n+\n+\tif (vec > intr_handle->max_intr) {\n+\t\totx2_err(\"Vector=%d greater than max_intr=%d\", vec,\n+\t\t\t\t intr_handle->max_intr);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\ttmp_handle = *intr_handle;\n+\t/* Create new eventfd for interrupt vector */\n+\ttmp_handle.fd = eventfd(0, EFD_NONBLOCK | EFD_CLOEXEC);\n+\tif (tmp_handle.fd == -1)\n+\t\treturn -ENODEV;\n+\n+\t/* Register vector interrupt callback */\n+\trc = rte_intr_callback_register(&tmp_handle, cb, data);\n+\tif (rc) {\n+\t\totx2_err(\"Failed to register vector:0x%x irq callback.\", vec);\n+\t\treturn rc;\n+\t}\n+\n+\tintr_handle->efds[vec] = tmp_handle.fd;\n+\tintr_handle->nb_efd = (vec > intr_handle->nb_efd) ?\n+\t\t\tvec : intr_handle->nb_efd;\n+\tif ((intr_handle->nb_efd + 1) > intr_handle->max_intr)\n+\t\tintr_handle->max_intr = intr_handle->nb_efd + 1;\n+\n+\totx2_base_dbg(\"Enable vector:0x%x for vfio (efds: %d, max:%d)\",\n+\t\tvec, intr_handle->nb_efd, intr_handle->max_intr);\n+\n+\t/* Enable MSIX vectors to VFIO */\n+\treturn irq_config(intr_handle, vec);\n+}\n+\n+/**\n+ * @internal\n+ * Unregister IRQ\n+ */\n+void\n+otx2_unregister_irq(struct rte_intr_handle *intr_handle,\n+\t\t    rte_intr_callback_fn cb, void *data, unsigned int vec)\n+{\n+\tstruct rte_intr_handle tmp_handle;\n+\n+\tif (vec > intr_handle->max_intr) {\n+\t\totx2_err(\"Error unregistering MSI-X interrupts vec:%d > %d\",\n+\t\t\tvec, intr_handle->max_intr);\n+\t\treturn;\n+\t}\n+\n+\ttmp_handle = *intr_handle;\n+\ttmp_handle.fd = intr_handle->efds[vec];\n+\tif (tmp_handle.fd == -1)\n+\t\treturn;\n+\n+\t/* Un-register callback func from eal lib */\n+\trte_intr_callback_unregister(&tmp_handle, cb, data);\n+\n+\totx2_base_dbg(\"Disable vector:0x%x for vfio (efds: %d, max:%d)\",\n+\t\t\tvec, intr_handle->nb_efd, intr_handle->max_intr);\n+\n+\tif (intr_handle->efds[vec] != -1)\n+\t\tclose(intr_handle->efds[vec]);\n+\t/* Disable MSIX vectors from VFIO */\n+\tintr_handle->efds[vec] = -1;\n+\tirq_config(intr_handle, vec);\n+}\n+\n+#else\n+\n+/**\n+ * @internal\n+ * Register IRQ\n+ */\n+int otx2_register_irq(__rte_unused struct rte_intr_handle *intr_handle,\n+\t\t      __rte_unused rte_intr_callback_fn cb,\n+\t\t      __rte_unused void *data, __rte_unused unsigned int vec)\n+{\n+\treturn -ENOTSUP;\n+}\n+\n+\n+/**\n+ * @internal\n+ * Unregister IRQ\n+ */\n+void otx2_unregister_irq(__rte_unused struct rte_intr_handle *intr_handle,\n+\t\t\t __rte_unused rte_intr_callback_fn cb,\n+\t\t\t __rte_unused void *data, __rte_unused unsigned int vec)\n+{\n+}\n+\n+/**\n+ * @internal\n+ * Disable IRQ\n+ */\n+int otx2_disable_irqs(__rte_unused struct rte_intr_handle *intr_handle)\n+{\n+\treturn -ENOTSUP;\n+}\n+\n+#endif /* RTE_EAL_VFIO */\ndiff --git a/drivers/common/octeontx2/otx2_irq.h b/drivers/common/octeontx2/otx2_irq.h\nindex df44ddfba..9d326276e 100644\n--- a/drivers/common/octeontx2/otx2_irq.h\n+++ b/drivers/common/octeontx2/otx2_irq.h\n@@ -16,4 +16,10 @@ typedef struct {\n \tuint64_t bits[MAX_VFPF_DWORD_BITS];\n } otx2_intr_t;\n \n+int otx2_register_irq(struct rte_intr_handle *intr_handle,\n+\t\t      rte_intr_callback_fn cb, void *data, unsigned int vec);\n+void otx2_unregister_irq(struct rte_intr_handle *intr_handle,\n+\t\t\t rte_intr_callback_fn cb, void *data, unsigned int vec);\n+int otx2_disable_irqs(struct rte_intr_handle *intr_handle);\n+\n #endif /* _OTX2_IRQ_H_ */\ndiff --git a/drivers/common/octeontx2/rte_common_octeontx2_version.map b/drivers/common/octeontx2/rte_common_octeontx2_version.map\nindex f4b49fb74..2f8a607ee 100644\n--- a/drivers/common/octeontx2/rte_common_octeontx2_version.map\n+++ b/drivers/common/octeontx2/rte_common_octeontx2_version.map\n@@ -21,5 +21,9 @@ DPDK_19.05 {\n \totx2_mbox_msg_send;\n \totx2_mbox_wait_for_rsp;\n \n+\totx2_disable_irqs;\n+\totx2_unregister_irq;\n+\totx2_register_irq;\n+\n \tlocal: *;\n };\n",
    "prefixes": [
        "v2",
        "08/27"
    ]
}