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GET /api/patches/53978/?format=api
{ "id": 53978, "url": "http://patches.dpdk.org/api/patches/53978/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20190601014905.45531-8-jerinj@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20190601014905.45531-8-jerinj@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20190601014905.45531-8-jerinj@marvell.com", "date": "2019-06-01T01:48:45", "name": "[v2,07/27] common/octeontx2: introduce common device class", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "a788831fd8843a7178429a520971173a244b4283", "submitter": { "id": 1188, "url": "http://patches.dpdk.org/api/people/1188/?format=api", "name": "Jerin Jacob Kollanukkaran", "email": "jerinj@marvell.com" }, "delegate": { "id": 1, "url": "http://patches.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20190601014905.45531-8-jerinj@marvell.com/mbox/", "series": [ { "id": 4844, "url": "http://patches.dpdk.org/api/series/4844/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=4844", "date": "2019-06-01T01:48:38", "name": "OCTEON TX2 common and mempool driver", "version": 2, "mbox": "http://patches.dpdk.org/series/4844/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/53978/comments/", "check": "fail", "checks": "http://patches.dpdk.org/api/patches/53978/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 845651B9A5;\n\tSat, 1 Jun 2019 03:49:39 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n\t[67.231.148.174]) by dpdk.org (Postfix) with ESMTP id 34C511B95C\n\tfor <dev@dpdk.org>; Sat, 1 Jun 2019 03:49:37 +0200 (CEST)", "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n\tby mx0a-0016f401.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id\n\tx511kFUn001055 for <dev@dpdk.org>; Fri, 31 May 2019 18:49:36 -0700", "from sc-exch02.marvell.com ([199.233.58.182])\n\tby mx0a-0016f401.pphosted.com with ESMTP id 2sufgn82w5-1\n\t(version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n\tfor <dev@dpdk.org>; Fri, 31 May 2019 18:49:36 -0700", "from SC-EXCH01.marvell.com (10.93.176.81) by SC-EXCH02.marvell.com\n\t(10.93.176.82) with Microsoft SMTP Server (TLS) id 15.0.1367.3;\n\tFri, 31 May 2019 18:49:35 -0700", "from maili.marvell.com (10.93.176.43) by SC-EXCH01.marvell.com\n\t(10.93.176.81) with Microsoft SMTP Server id 15.0.1367.3 via Frontend\n\tTransport; Fri, 31 May 2019 18:49:35 -0700", "from jerin-lab.marvell.com (jerin-lab.marvell.com [10.28.34.14])\n\tby maili.marvell.com (Postfix) with ESMTP id 2C95E3F703F;\n\tFri, 31 May 2019 18:49:33 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n\th=from : to : subject\n\t: date : message-id : in-reply-to : references : mime-version :\n\tcontent-transfer-encoding : content-type; s=pfpt0818;\n\tbh=4LRLRb04NjH5wmeiBLgd+9QSbrnkbkTPUKfBv7S/ES0=;\n\tb=scUNRzN6JnIr3tve4jo6NQXSQVkqJCJJWKtoLocCRIymlh/zScAW/+xBgVzWTNZ2kfFG\n\tE6++7uRKzJwWD2UxHloV98SjFuhYcE5An/udX4BO3k1mUEDw13N2rYmnwhlz4yymeyfb\n\t075MLPfzwUL5dVNaVSQJ4BzxvFiQ2MdLsVM968U6FmenqVpjjV67T+IRYpXfgcl0IJTi\n\tAgTrauYl13ZJUVDoLZlTWACIVyFtW1z11Y0y2fT3LhpP8uFjK6wpDLhJ5783bX3XyH5Y\n\t843R8vB8Mn59AUU/STrZiAiLmTliK3ly/KqA5sXivsRftiCF3gj9RSKxGAyshw8v15Y5\n\ttQ== ", "From": "<jerinj@marvell.com>", "To": "<dev@dpdk.org>, Jerin Jacob <jerinj@marvell.com>, Nithin Dabilpuram\n\t<ndabilpuram@marvell.com>, Vamsi Attunuru <vattunuru@marvell.com>", "Date": "Sat, 1 Jun 2019 07:18:45 +0530", "Message-ID": "<20190601014905.45531-8-jerinj@marvell.com>", "X-Mailer": "git-send-email 2.21.0", "In-Reply-To": "<20190601014905.45531-1-jerinj@marvell.com>", "References": "<20190523081339.56348-1-jerinj@marvell.com>\n\t<20190601014905.45531-1-jerinj@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:, ,\n\tdefinitions=2019-06-01_02:, , signatures=0", "Subject": "[dpdk-dev] [PATCH v2 07/27] common/octeontx2: introduce common\n\tdevice class", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Jerin Jacob <jerinj@marvell.com>\n\nIntroduce otx2_dev class to hold octeontx2 PCIe device specific\ninformation and operations.\n\nAll PCIe drivers(ethdev, mempool, cryptodev and eventdev) in octeontx2,\ninherits this base object to avail the common functionalities such\nas mailbox creation, interrupt registration, etc of the PCIe device.\n\nSigned-off-by: Jerin Jacob <jerinj@marvell.com>\nSigned-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>\n---\n drivers/common/octeontx2/Makefile | 2 +\n drivers/common/octeontx2/meson.build | 4 +-\n drivers/common/octeontx2/otx2_common.h | 14 ++\n drivers/common/octeontx2/otx2_dev.c | 197 ++++++++++++++++++\n drivers/common/octeontx2/otx2_dev.h | 84 ++++++++\n drivers/common/octeontx2/otx2_irq.h | 19 ++\n .../rte_common_octeontx2_version.map | 3 +\n 7 files changed, 321 insertions(+), 2 deletions(-)\n create mode 100644 drivers/common/octeontx2/otx2_dev.c\n create mode 100644 drivers/common/octeontx2/otx2_dev.h\n create mode 100644 drivers/common/octeontx2/otx2_irq.h", "diff": "diff --git a/drivers/common/octeontx2/Makefile b/drivers/common/octeontx2/Makefile\nindex 3fd67f0ab..a6f94553d 100644\n--- a/drivers/common/octeontx2/Makefile\n+++ b/drivers/common/octeontx2/Makefile\n@@ -11,6 +11,7 @@ LIB = librte_common_octeontx2.a\n \n CFLAGS += $(WERROR_FLAGS)\n CFLAGS += -I$(RTE_SDK)/drivers/common/octeontx2\n+CFLAGS += -I$(RTE_SDK)/drivers/bus/pci\n \n ifneq ($(CONFIG_RTE_ARCH_64),y)\n CFLAGS += -Wno-int-to-pointer-cast\n@@ -24,6 +25,7 @@ LIBABIVER := 1\n #\n # all source are stored in SRCS-y\n #\n+SRCS-y += otx2_dev.c\n SRCS-y += otx2_mbox.c\n SRCS-y += otx2_common.c\n \ndiff --git a/drivers/common/octeontx2/meson.build b/drivers/common/octeontx2/meson.build\nindex 4771b1942..feaf75d92 100644\n--- a/drivers/common/octeontx2/meson.build\n+++ b/drivers/common/octeontx2/meson.build\n@@ -2,7 +2,7 @@\n # Copyright(C) 2019 Marvell International Ltd.\n #\n \n-sources= files(\n+sources= files('otx2_dev.c',\n \t\t'otx2_mbox.c',\n \t\t'otx2_common.c',\n \t )\n@@ -19,6 +19,6 @@ foreach flag: extra_flags\n \tendif\n endforeach\n \n-deps = ['eal', 'ethdev']\n+deps = ['eal', 'pci', 'ethdev']\n includes += include_directories('../../common/octeontx2',\n \t\t'../../bus/pci')\ndiff --git a/drivers/common/octeontx2/otx2_common.h b/drivers/common/octeontx2/otx2_common.h\nindex 58fcf5a41..b9e7a7f8d 100644\n--- a/drivers/common/octeontx2/otx2_common.h\n+++ b/drivers/common/octeontx2/otx2_common.h\n@@ -69,6 +69,20 @@ extern int otx2_logtype_dpi;\n #define otx2_tim_dbg(fmt, ...) otx2_dbg(tim, fmt, ##__VA_ARGS__)\n #define otx2_dpi_dbg(fmt, ...) otx2_dbg(dpi, fmt, ##__VA_ARGS__)\n \n+/* PCI IDs */\n+#define PCI_VENDOR_ID_CAVIUM\t\t\t0x177D\n+#define PCI_DEVID_OCTEONTX2_RVU_PF 0xA063\n+#define PCI_DEVID_OCTEONTX2_RVU_VF\t\t0xA064\n+#define PCI_DEVID_OCTEONTX2_RVU_AF\t\t0xA065\n+#define PCI_DEVID_OCTEONTX2_RVU_SSO_TIM_PF\t0xA0F9\n+#define PCI_DEVID_OCTEONTX2_RVU_SSO_TIM_VF\t0xA0FA\n+#define PCI_DEVID_OCTEONTX2_RVU_NPA_PF\t\t0xA0FB\n+#define PCI_DEVID_OCTEONTX2_RVU_NPA_VF\t\t0xA0FC\n+#define PCI_DEVID_OCTEONTX2_RVU_CPT_PF\t\t0xA0FD\n+#define PCI_DEVID_OCTEONTX2_RVU_CPT_VF\t\t0xA0FE\n+#define PCI_DEVID_OCTEONTX2_RVU_AF_VF\t\t0xA0f8\n+#define PCI_DEVID_OCTEONTX2_DPI_VF\t\t0xA081\n+\n /* IO Access */\n #define otx2_read64(addr) rte_read64_relaxed((void *)(addr))\n #define otx2_write64(val, addr) rte_write64_relaxed((val), (void *)(addr))\ndiff --git a/drivers/common/octeontx2/otx2_dev.c b/drivers/common/octeontx2/otx2_dev.c\nnew file mode 100644\nindex 000000000..ccdb2df78\n--- /dev/null\n+++ b/drivers/common/octeontx2/otx2_dev.c\n@@ -0,0 +1,197 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2019 Marvell International Ltd.\n+ */\n+\n+#include <fcntl.h>\n+#include <inttypes.h>\n+#include <sys/mman.h>\n+#include <unistd.h>\n+\n+#include <rte_common.h>\n+#include <rte_eal.h>\n+#include <rte_memcpy.h>\n+\n+#include \"otx2_dev.h\"\n+#include \"otx2_mbox.h\"\n+\n+/* PF/VF message handling timer */\n+#define VF_PF_MBOX_TIMER_MS\t(20 * 1000)\n+\n+static void *\n+mbox_mem_map(off_t off, size_t size)\n+{\n+\tvoid *va = MAP_FAILED;\n+\tint mem_fd;\n+\n+\tif (size <= 0)\n+\t\tgoto error;\n+\n+\tmem_fd = open(\"/dev/mem\", O_RDWR);\n+\tif (mem_fd < 0)\n+\t\tgoto error;\n+\n+\tva = mmap(NULL, size, PROT_READ | PROT_WRITE, MAP_SHARED, mem_fd, off);\n+\tclose(mem_fd);\n+\n+\tif (va == MAP_FAILED)\n+\t\totx2_err(\"Failed to mmap sz=0x%zx, fd=%d, off=%ld\",\n+\t\t\t size, mem_fd, off);\n+error:\n+\treturn va;\n+}\n+\n+static void\n+mbox_mem_unmap(void *va, size_t size)\n+{\n+\tif (va)\n+\t\tmunmap(va, size);\n+}\n+\n+static void\n+otx2_update_pass_hwcap(struct rte_pci_device *pci_dev, struct otx2_dev *dev)\n+{\n+\tRTE_SET_USED(pci_dev);\n+\n+\t/* Update this logic when we have A1 */\n+\tdev->hwcap |= OTX2_HWCAP_F_A0;\n+}\n+\n+static void\n+otx2_update_vf_hwcap(struct rte_pci_device *pci_dev, struct otx2_dev *dev)\n+{\n+\tdev->hwcap = 0;\n+\n+\tswitch (pci_dev->id.device_id) {\n+\tcase PCI_DEVID_OCTEONTX2_RVU_PF:\n+\t\tbreak;\n+\tcase PCI_DEVID_OCTEONTX2_RVU_SSO_TIM_VF:\n+\tcase PCI_DEVID_OCTEONTX2_RVU_NPA_VF:\n+\tcase PCI_DEVID_OCTEONTX2_RVU_CPT_VF:\n+\tcase PCI_DEVID_OCTEONTX2_RVU_AF_VF:\n+\tcase PCI_DEVID_OCTEONTX2_RVU_VF:\n+\t\tdev->hwcap |= OTX2_HWCAP_F_VF;\n+\t\tbreak;\n+\t}\n+}\n+\n+/**\n+ * @internal\n+ * Initialize the otx2 device\n+ */\n+int\n+otx2_dev_init(struct rte_pci_device *pci_dev, void *otx2_dev)\n+{\n+\tint up_direction = MBOX_DIR_PFAF_UP;\n+\tint rc, direction = MBOX_DIR_PFAF;\n+\tstruct otx2_dev *dev = otx2_dev;\n+\tuintptr_t bar2, bar4;\n+\tuint64_t bar4_addr;\n+\tvoid *hwbase;\n+\n+\tbar2 = (uintptr_t)pci_dev->mem_resource[2].addr;\n+\tbar4 = (uintptr_t)pci_dev->mem_resource[4].addr;\n+\n+\tif (bar2 == 0 || bar4 == 0) {\n+\t\totx2_err(\"Failed to get pci bars\");\n+\t\trc = -ENODEV;\n+\t\tgoto error;\n+\t}\n+\n+\tdev->node = pci_dev->device.numa_node;\n+\tdev->maxvf = pci_dev->max_vfs;\n+\tdev->bar2 = bar2;\n+\tdev->bar4 = bar4;\n+\n+\totx2_update_vf_hwcap(pci_dev, dev);\n+\totx2_update_pass_hwcap(pci_dev, dev);\n+\n+\tif (otx2_dev_is_vf(dev)) {\n+\t\tdirection = MBOX_DIR_VFPF;\n+\t\tup_direction = MBOX_DIR_VFPF_UP;\n+\t}\n+\n+\t/* Initialize the local mbox */\n+\trc = otx2_mbox_init(&dev->mbox_local, bar4, bar2, direction, 1);\n+\tif (rc)\n+\t\tgoto error;\n+\tdev->mbox = &dev->mbox_local;\n+\n+\trc = otx2_mbox_init(&dev->mbox_up, bar4, bar2, up_direction, 1);\n+\tif (rc)\n+\t\tgoto error;\n+\n+\t/* Check the readiness of PF/VF */\n+\trc = otx2_send_ready_msg(dev->mbox, &dev->pf_func);\n+\tif (rc)\n+\t\tgoto mbox_fini;\n+\n+\tdev->pf = otx2_get_pf(dev->pf_func);\n+\tdev->vf = otx2_get_vf(dev->pf_func);\n+\tmemset(&dev->active_vfs, 0, sizeof(dev->active_vfs));\n+\n+\t/* Found VF devices in a PF device */\n+\tif (pci_dev->max_vfs > 0) {\n+\n+\t\t/* Remap mbox area for all vf's */\n+\t\tbar4_addr = otx2_read64(bar2 + RVU_PF_VF_BAR4_ADDR);\n+\t\tif (bar4_addr == 0) {\n+\t\t\trc = -ENODEV;\n+\t\t\tgoto mbox_fini;\n+\t\t}\n+\n+\t\thwbase = mbox_mem_map(bar4_addr, MBOX_SIZE * pci_dev->max_vfs);\n+\t\tif (hwbase == MAP_FAILED) {\n+\t\t\trc = -ENOMEM;\n+\t\t\tgoto mbox_fini;\n+\t\t}\n+\t\t/* Init mbox object */\n+\t\trc = otx2_mbox_init(&dev->mbox_vfpf, (uintptr_t)hwbase,\n+\t\t\t\t bar2, MBOX_DIR_PFVF, pci_dev->max_vfs);\n+\t\tif (rc)\n+\t\t\tgoto iounmap;\n+\n+\t\t/* PF -> VF UP messages */\n+\t\trc = otx2_mbox_init(&dev->mbox_vfpf_up, (uintptr_t)hwbase,\n+\t\t\t\t bar2, MBOX_DIR_PFVF_UP, pci_dev->max_vfs);\n+\t\tif (rc)\n+\t\t\tgoto mbox_fini;\n+\t}\n+\n+\tdev->mbox_active = 1;\n+\treturn rc;\n+\n+iounmap:\n+\tmbox_mem_unmap(hwbase, MBOX_SIZE * pci_dev->max_vfs);\n+mbox_fini:\n+\totx2_mbox_fini(dev->mbox);\n+\totx2_mbox_fini(&dev->mbox_up);\n+error:\n+\treturn rc;\n+}\n+\n+/**\n+ * @internal\n+ * Finalize the otx2 device\n+ */\n+void\n+otx2_dev_fini(struct rte_pci_device *pci_dev, void *otx2_dev)\n+{\n+\tstruct otx2_dev *dev = otx2_dev;\n+\tstruct otx2_mbox *mbox;\n+\n+\t/* Release PF - VF */\n+\tmbox = &dev->mbox_vfpf;\n+\tif (mbox->hwbase && mbox->dev)\n+\t\tmbox_mem_unmap((void *)mbox->hwbase,\n+\t\t\t MBOX_SIZE * pci_dev->max_vfs);\n+\totx2_mbox_fini(mbox);\n+\tmbox = &dev->mbox_vfpf_up;\n+\totx2_mbox_fini(mbox);\n+\n+\t/* Release PF - AF */\n+\tmbox = dev->mbox;\n+\totx2_mbox_fini(mbox);\n+\tmbox = &dev->mbox_up;\n+\totx2_mbox_fini(mbox);\n+\tdev->mbox_active = 0;\n+}\ndiff --git a/drivers/common/octeontx2/otx2_dev.h b/drivers/common/octeontx2/otx2_dev.h\nnew file mode 100644\nindex 000000000..a89570b62\n--- /dev/null\n+++ b/drivers/common/octeontx2/otx2_dev.h\n@@ -0,0 +1,84 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2019 Marvell International Ltd.\n+ */\n+\n+#ifndef _OTX2_DEV_H\n+#define _OTX2_DEV_H\n+\n+#include <rte_bus_pci.h>\n+\n+#include \"otx2_common.h\"\n+#include \"otx2_irq.h\"\n+#include \"otx2_mbox.h\"\n+\n+/* Common HWCAP flags. Use from LSB bits */\n+#define OTX2_HWCAP_F_VF\t\tBIT_ULL(0) /* VF device */\n+#define otx2_dev_is_vf(dev)\t(dev->hwcap & OTX2_HWCAP_F_VF)\n+#define otx2_dev_is_pf(dev)\t(!(dev->hwcap & OTX2_HWCAP_F_VF))\n+#define otx2_dev_is_lbk(dev)\t((dev->hwcap & OTX2_HWCAP_F_VF) && \\\n+\t\t\t\t (dev->tx_chan_base < 0x700))\n+\n+#define OTX2_HWCAP_F_A0\t\tBIT_ULL(1) /* A0 device */\n+#define otx2_dev_is_A0(dev)\t(dev->hwcap & OTX2_HWCAP_F_A0)\n+\n+struct otx2_dev;\n+\n+#define OTX2_DEV\t\t\t\t\t\\\n+\tint node __rte_cache_aligned;\t\t\t\\\n+\tuint16_t pf;\t\t\t\t\t\\\n+\tint16_t vf;\t\t\t\t\t\\\n+\tuint16_t pf_func;\t\t\t\t\\\n+\tuint8_t mbox_active;\t\t\t\t\\\n+\tbool drv_inited;\t\t\t\t\\\n+\tuint64_t active_vfs[MAX_VFPF_DWORD_BITS];\t\\\n+\tuintptr_t bar2;\t\t\t\t\t\\\n+\tuintptr_t bar4;\t\t\t\t\t\\\n+\tstruct otx2_mbox mbox_local;\t\t\t\\\n+\tstruct otx2_mbox mbox_up;\t\t\t\\\n+\tstruct otx2_mbox mbox_vfpf;\t\t\t\\\n+\tstruct otx2_mbox mbox_vfpf_up;\t\t\t\\\n+\totx2_intr_t intr;\t\t\t\t\\\n+\tint timer_set;\t/* ~0 : no alarm handling */\t\\\n+\tuint64_t hwcap;\t\t\t\t\t\\\n+\tstruct otx2_mbox *mbox;\t\t\t\t\\\n+\tuint16_t maxvf;\t\t\t\t\t\\\n+\tconst struct otx2_dev_ops *ops\n+\n+struct otx2_dev {\n+\tOTX2_DEV;\n+};\n+\n+int otx2_dev_init(struct rte_pci_device *pci_dev, void *otx2_dev);\n+void otx2_dev_fini(struct rte_pci_device *pci_dev, void *otx2_dev);\n+int otx2_dev_active_vfs(void *otx2_dev);\n+\n+#define RVU_PFVF_PF_SHIFT\t10\n+#define RVU_PFVF_PF_MASK\t0x3F\n+#define RVU_PFVF_FUNC_SHIFT\t0\n+#define RVU_PFVF_FUNC_MASK\t0x3FF\n+\n+static inline int\n+otx2_get_vf(uint16_t pf_func)\n+{\n+\treturn (((pf_func >> RVU_PFVF_FUNC_SHIFT) & RVU_PFVF_FUNC_MASK) - 1);\n+}\n+\n+static inline int\n+otx2_get_pf(uint16_t pf_func)\n+{\n+\treturn (pf_func >> RVU_PFVF_PF_SHIFT) & RVU_PFVF_PF_MASK;\n+}\n+\n+static inline int\n+otx2_pfvf_func(int pf, int vf)\n+{\n+\treturn (pf << RVU_PFVF_PF_SHIFT) | ((vf << RVU_PFVF_FUNC_SHIFT) + 1);\n+}\n+\n+static inline int\n+otx2_is_afvf(uint16_t pf_func)\n+{\n+\treturn !(pf_func & ~RVU_PFVF_FUNC_MASK);\n+}\n+\n+#endif /* _OTX2_DEV_H */\ndiff --git a/drivers/common/octeontx2/otx2_irq.h b/drivers/common/octeontx2/otx2_irq.h\nnew file mode 100644\nindex 000000000..df44ddfba\n--- /dev/null\n+++ b/drivers/common/octeontx2/otx2_irq.h\n@@ -0,0 +1,19 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2019 Marvell International Ltd.\n+ */\n+\n+#ifndef _OTX2_IRQ_H_\n+#define _OTX2_IRQ_H_\n+\n+#include <rte_pci.h>\n+#include <rte_interrupts.h>\n+\n+#include \"otx2_common.h\"\n+\n+typedef struct {\n+/* 128 devices translate to two 64 bits dwords */\n+#define MAX_VFPF_DWORD_BITS 2\n+\tuint64_t bits[MAX_VFPF_DWORD_BITS];\n+} otx2_intr_t;\n+\n+#endif /* _OTX2_IRQ_H_ */\ndiff --git a/drivers/common/octeontx2/rte_common_octeontx2_version.map b/drivers/common/octeontx2/rte_common_octeontx2_version.map\nindex 4502088f2..f4b49fb74 100644\n--- a/drivers/common/octeontx2/rte_common_octeontx2_version.map\n+++ b/drivers/common/octeontx2/rte_common_octeontx2_version.map\n@@ -1,6 +1,9 @@\n DPDK_19.05 {\n \tglobal:\n \n+\totx2_dev_fini;\n+\totx2_dev_init;\n+\n \totx2_logtype_base;\n \totx2_logtype_dpi;\n \totx2_logtype_mbox;\n", "prefixes": [ "v2", "07/27" ] }