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{
    "id": 53603,
    "url": "http://patches.dpdk.org/api/patches/53603/?format=api",
    "web_url": "http://patches.dpdk.org/project/dpdk/patch/20190521213953.25425-9-ajit.khaparde@broadcom.com/",
    "project": {
        "id": 1,
        "url": "http://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<20190521213953.25425-9-ajit.khaparde@broadcom.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/20190521213953.25425-9-ajit.khaparde@broadcom.com",
    "date": "2019-05-21T21:39:50",
    "name": "[08/11] net/bnxt: update HWRM API",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": true,
    "hash": "e0f44468c06508cb1f8a9d51e94192dd36bd7823",
    "submitter": {
        "id": 501,
        "url": "http://patches.dpdk.org/api/people/501/?format=api",
        "name": "Ajit Khaparde",
        "email": "ajit.khaparde@broadcom.com"
    },
    "delegate": {
        "id": 319,
        "url": "http://patches.dpdk.org/api/users/319/?format=api",
        "username": "fyigit",
        "first_name": "Ferruh",
        "last_name": "Yigit",
        "email": "ferruh.yigit@amd.com"
    },
    "mbox": "http://patches.dpdk.org/project/dpdk/patch/20190521213953.25425-9-ajit.khaparde@broadcom.com/mbox/",
    "series": [
        {
            "id": 4736,
            "url": "http://patches.dpdk.org/api/series/4736/?format=api",
            "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=4736",
            "date": "2019-05-21T21:39:43",
            "name": "bnxt patchset",
            "version": 1,
            "mbox": "http://patches.dpdk.org/series/4736/mbox/"
        }
    ],
    "comments": "http://patches.dpdk.org/api/patches/53603/comments/",
    "check": "warning",
    "checks": "http://patches.dpdk.org/api/patches/53603/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@dpdk.org",
        "Delivered-To": "patchwork@dpdk.org",
        "Received": [
            "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 5F1937D4A;\n\tTue, 21 May 2019 23:40:27 +0200 (CEST)",
            "from rnd-relay.smtp.broadcom.com (rnd-relay.smtp.broadcom.com\n\t[192.19.229.170]) by dpdk.org (Postfix) with ESMTP id E023E4CA6\n\tfor <dev@dpdk.org>; Tue, 21 May 2019 23:39:58 +0200 (CEST)",
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        "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple; d=broadcom.com;\n\ts=dkimrelay; t=1558474796;\n\tbh=8MAEPG2/FmcVepo5heYZQhVsDt8t+1s7xWHlrjEeuNA=;\n\th=From:To:Cc:Subject:Date:In-Reply-To:References:From;\n\tb=bdh38Vs0/RqqSO+Fke/08Dng70jvkLgpbhWHKUpfikOabaN20zgxx5ZbTHzWtNzfg\n\to9ya371bguA9Ks27xHJWwlM9HiBYBCx9WvFQnGGf4mKDXe/zYNebX+uNXPFnjC42Wl\n\tJE8+w+L8AEfnyZKz7Q9LZE/skPLhataO0OkzcOww=",
        "From": "Ajit Khaparde <ajit.khaparde@broadcom.com>",
        "To": "dev@dpdk.org",
        "Cc": "ferruh.yigit@intel.com, Lance Richardson <lance.richardson@broadcom.com>",
        "Date": "Tue, 21 May 2019 14:39:50 -0700",
        "Message-Id": "<20190521213953.25425-9-ajit.khaparde@broadcom.com>",
        "X-Mailer": "git-send-email 2.20.1 (Apple Git-117)",
        "In-Reply-To": "<20190521213953.25425-1-ajit.khaparde@broadcom.com>",
        "References": "<20190521213953.25425-1-ajit.khaparde@broadcom.com>",
        "MIME-Version": "1.0",
        "Content-Type": "text/plain; charset=UTF-8",
        "Content-Transfer-Encoding": "8bit",
        "Subject": "[dpdk-dev] [PATCH 08/11] net/bnxt: update HWRM API",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.15",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
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        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "Update HWRM API to version 1.10.0.19\n\nSigned-off-by: Ajit Khaparde <ajit.khaparde@broadcom.com>\nReviewed-by: Lance Richardson <lance.richardson@broadcom.com>\n---\n drivers/net/bnxt/hsi_struct_def_dpdk.h | 3112 +++++++++++++++++++-----\n 1 file changed, 2514 insertions(+), 598 deletions(-)",
    "diff": "diff --git a/drivers/net/bnxt/hsi_struct_def_dpdk.h b/drivers/net/bnxt/hsi_struct_def_dpdk.h\nindex e80057936..ea9a7d40e 100644\n--- a/drivers/net/bnxt/hsi_struct_def_dpdk.h\n+++ b/drivers/net/bnxt/hsi_struct_def_dpdk.h\n@@ -1,5 +1,5 @@\n /* SPDX-License-Identifier: BSD-3-Clause\n- * Copyright (c) 2014-2018 Broadcom Limited\n+ * Copyright (c) 2014-2019 Broadcom Limited\n  * All rights reserved.\n  *\n  * DO NOT MODIFY!!! This file is automatically generated.\n@@ -68,9 +68,9 @@ struct hwrm_resp_hdr {\n /* RoCE slow path command */\n #define TLV_TYPE_ROCE_SP_COMMAND                 UINT32_C(0x3)\n /* RoCE slow path command to query CC Gen1 support. */\n-#define TLV_TYPE_QUERY_ROCE_CC_GEN1              UINT32_C(0xcommand 0x0005)\n+#define TLV_TYPE_QUERY_ROCE_CC_GEN1              UINT32_C(0x4)\n /* RoCE slow path command to modify CC Gen1 support. */\n-#define TLV_TYPE_MODIFY_ROCE_CC_GEN1             UINT32_C(0xcommand 0x0005)\n+#define TLV_TYPE_MODIFY_ROCE_CC_GEN1             UINT32_C(0x5)\n /* Engine CKV - The device's serial number. */\n #define TLV_TYPE_ENGINE_CKV_DEVICE_SERIAL_NUMBER UINT32_C(0x8001)\n /* Engine CKV - Per-function random nonce data. */\n@@ -366,6 +366,7 @@ struct cmd_nums {\n \t#define HWRM_TUNNEL_DST_PORT_QUERY                UINT32_C(0xa0)\n \t#define HWRM_TUNNEL_DST_PORT_ALLOC                UINT32_C(0xa1)\n \t#define HWRM_TUNNEL_DST_PORT_FREE                 UINT32_C(0xa2)\n+\t#define HWRM_STAT_CTX_ENG_QUERY                   UINT32_C(0xaf)\n \t#define HWRM_STAT_CTX_ALLOC                       UINT32_C(0xb0)\n \t#define HWRM_STAT_CTX_FREE                        UINT32_C(0xb1)\n \t#define HWRM_STAT_CTX_QUERY                       UINT32_C(0xb2)\n@@ -442,6 +443,14 @@ struct cmd_nums {\n \t#define HWRM_FW_IPC_MSG                           UINT32_C(0x110)\n \t#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO        UINT32_C(0x111)\n \t#define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE       UINT32_C(0x112)\n+\t/* Experimental */\n+\t#define HWRM_CFA_FLOW_AGING_TIMER_RESET           UINT32_C(0x113)\n+\t/* Experimental */\n+\t#define HWRM_CFA_FLOW_AGING_CFG                   UINT32_C(0x114)\n+\t/* Experimental */\n+\t#define HWRM_CFA_FLOW_AGING_QCFG                  UINT32_C(0x115)\n+\t/* Experimental */\n+\t#define HWRM_CFA_FLOW_AGING_QCAPS                 UINT32_C(0x116)\n \t/* Engine CKV - Ping the device and SRT firmware to get the public key. */\n \t#define HWRM_ENGINE_CKV_HELLO                     UINT32_C(0x12d)\n \t/* Engine CKV - Get the current allocation status of keys provisioned in the key vault. */\n@@ -591,61 +600,79 @@ struct cmd_nums {\n struct ret_codes {\n \tuint16_t\terror_code;\n \t/* Request was successfully executed by the HWRM. */\n-\t#define HWRM_ERR_CODE_SUCCESS                UINT32_C(0x0)\n+\t#define HWRM_ERR_CODE_SUCCESS                   UINT32_C(0x0)\n \t/* The HWRM failed to execute the request. */\n-\t#define HWRM_ERR_CODE_FAIL                   UINT32_C(0x1)\n+\t#define HWRM_ERR_CODE_FAIL                      UINT32_C(0x1)\n \t/*\n \t * The request contains invalid argument(s) or input\n \t * parameters.\n \t */\n-\t#define HWRM_ERR_CODE_INVALID_PARAMS         UINT32_C(0x2)\n+\t#define HWRM_ERR_CODE_INVALID_PARAMS            UINT32_C(0x2)\n \t/*\n \t * The requester is not allowed to access the requested\n \t * resource. This error code shall be provided in a\n \t * response to a request to query or modify an existing\n \t * resource that is not accessible by the requester.\n \t */\n-\t#define HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED UINT32_C(0x3)\n+\t#define HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED    UINT32_C(0x3)\n \t/*\n \t * The HWRM is unable to allocate the requested resource.\n \t * This code only applies to requests for HWRM resource\n \t * allocations.\n \t */\n-\t#define HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR   UINT32_C(0x4)\n+\t#define HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR      UINT32_C(0x4)\n \t/*\n \t * Invalid combination of flags is specified in the\n \t * request.\n \t */\n-\t#define HWRM_ERR_CODE_INVALID_FLAGS          UINT32_C(0x5)\n+\t#define HWRM_ERR_CODE_INVALID_FLAGS             UINT32_C(0x5)\n \t/*\n \t * Invalid combination of enables fields is specified in\n \t * the request.\n \t */\n-\t#define HWRM_ERR_CODE_INVALID_ENABLES        UINT32_C(0x6)\n+\t#define HWRM_ERR_CODE_INVALID_ENABLES           UINT32_C(0x6)\n \t/*\n \t * Request contains a required TLV that is not supported by\n \t * the installed version of firmware.\n \t */\n-\t#define HWRM_ERR_CODE_UNSUPPORTED_TLV        UINT32_C(0x7)\n+\t#define HWRM_ERR_CODE_UNSUPPORTED_TLV           UINT32_C(0x7)\n \t/*\n \t * No firmware buffer available to accept the request. Driver\n \t * should retry the request.\n \t */\n-\t#define HWRM_ERR_CODE_NO_BUFFER              UINT32_C(0x8)\n+\t#define HWRM_ERR_CODE_NO_BUFFER                 UINT32_C(0x8)\n \t/*\n \t * This error code is only reported by firmware when some\n \t * sub-option of a supported HWRM command is unsupported.\n \t */\n-\t#define HWRM_ERR_CODE_UNSUPPORTED_OPTION_ERR UINT32_C(0x9)\n+\t#define HWRM_ERR_CODE_UNSUPPORTED_OPTION_ERR    UINT32_C(0x9)\n+\t/*\n+\t * This error code is only reported by firmware when the specific\n+\t * request is not able to process when the HOT reset in progress.\n+\t */\n+\t#define HWRM_ERR_CODE_HOT_RESET_PROGRESS        UINT32_C(0xa)\n+\t/*\n+\t * This error code is only reported by firmware when the registered\n+\t * driver instances are not capable of hot reset.\n+\t */\n+\t#define HWRM_ERR_CODE_HOT_RESET_FAIL            UINT32_C(0xb)\n \t/*\n \t * Generic HWRM execution error that represents an\n \t * internal error.\n \t */\n-\t#define HWRM_ERR_CODE_HWRM_ERROR             UINT32_C(0xf)\n+\t#define HWRM_ERR_CODE_HWRM_ERROR                UINT32_C(0xf)\n+\t/*\n+\t * This value indicates that the HWRM response is in TLV format and\n+\t * should be interpreted as one or more TLVs starting with the\n+\t * hwrm_resp_hdr TLV. This value is not an indicatation of any error\n+\t * by itself, just an indicatation that the response should be parsed\n+\t * as TLV and the actual error code will be in the hwrm_resp_hdr TLV.\n+\t */\n+\t#define HWRM_ERR_CODE_TLV_ENCAPSULATED_RESPONSE UINT32_C(0x8000)\n \t/* Unknown error */\n-\t#define HWRM_ERR_CODE_UNKNOWN_ERR            UINT32_C(0xfffe)\n+\t#define HWRM_ERR_CODE_UNKNOWN_ERR               UINT32_C(0xfffe)\n \t/* Unsupported or invalid command */\n-\t#define HWRM_ERR_CODE_CMD_NOT_SUPPORTED      UINT32_C(0xffff)\n+\t#define HWRM_ERR_CODE_CMD_NOT_SUPPORTED         UINT32_C(0xffff)\n \t#define HWRM_ERR_CODE_LAST \\\n \t\tHWRM_ERR_CODE_CMD_NOT_SUPPORTED\n \tuint16_t\tunused_0[3];\n@@ -705,11 +732,11 @@ struct hwrm_err_output {\n /* valid key for HWRM response */\n #define HWRM_RESP_VALID_KEY 1\n #define HWRM_VERSION_MAJOR 1\n-#define HWRM_VERSION_MINOR 9\n-#define HWRM_VERSION_UPDATE 2\n+#define HWRM_VERSION_MINOR 10\n+#define HWRM_VERSION_UPDATE 0\n /* non-zero means beta version */\n-#define HWRM_VERSION_RSVD 53\n-#define HWRM_VERSION_STR \"1.9.2.53\"\n+#define HWRM_VERSION_RSVD 19\n+#define HWRM_VERSION_STR \"1.10.0.19\"\n \n /****************\n  * hwrm_ver_get *\n@@ -959,6 +986,13 @@ struct hwrm_ver_get_output {\n \t */\n \t#define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED \\\n \t\tUINT32_C(0x100)\n+\t/*\n+\t * If set to 1, firmware is capable to support flow aging.\n+\t * If set to 0, firmware is not capable to support flow aging.\n+\t * By default, this flag should be 0 for older version of core firmware.\n+\t */\n+\t#define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_FLOW_AGING_SUPPORTED \\\n+\t\tUINT32_C(0x200)\n \t/*\n \t * This field represents the major version of RoCE firmware.\n \t * A change in major version represents a major release.\n@@ -2031,7 +2065,7 @@ struct cmpl_base {\n \t#define CMPL_BASE_TYPE_SFT             0\n \t/*\n \t * TX L2 completion:\n-\t *  Completion of TX packet.  Length = 16B\n+\t * Completion of TX packet.  Length = 16B\n \t */\n \t#define CMPL_BASE_TYPE_TX_L2             UINT32_C(0x0)\n \t/*\n@@ -2116,7 +2150,7 @@ struct tx_cmpl {\n \t#define TX_CMPL_TYPE_SFT        0\n \t/*\n \t * TX L2 completion:\n-\t *  Completion of TX packet.  Length = 16B\n+\t * Completion of TX packet.  Length = 16B\n \t */\n \t#define TX_CMPL_TYPE_TX_L2        UINT32_C(0x0)\n \t#define TX_CMPL_TYPE_LAST        TX_CMPL_TYPE_TX_L2\n@@ -2408,30 +2442,31 @@ struct rx_pkt_cmpl_hi {\n \t * inner packet and that the ip_cs_error field indicates if there\n \t * was an error.\n \t */\n-\t#define RX_PKT_CMPL_FLAGS2_IP_CS_CALC       UINT32_C(0x1)\n+\t#define RX_PKT_CMPL_FLAGS2_IP_CS_CALC                 UINT32_C(0x1)\n \t/*\n \t * This indicates that the TCP, UDP or ICMP checksum was\n \t * calculated for the inner packet and that the l4_cs_error field\n \t * indicates if there was an error.\n \t */\n-\t#define RX_PKT_CMPL_FLAGS2_L4_CS_CALC       UINT32_C(0x2)\n+\t#define RX_PKT_CMPL_FLAGS2_L4_CS_CALC                 UINT32_C(0x2)\n \t/*\n \t * This indicates that the ip checksum was calculated for the\n \t * tunnel header and that the t_ip_cs_error field indicates if there\n \t * was an error.\n \t */\n-\t#define RX_PKT_CMPL_FLAGS2_T_IP_CS_CALC     UINT32_C(0x4)\n+\t#define RX_PKT_CMPL_FLAGS2_T_IP_CS_CALC               UINT32_C(0x4)\n \t/*\n \t * This indicates that the UDP checksum was\n \t * calculated for the tunnel packet and that the t_l4_cs_error field\n \t * indicates if there was an error.\n \t */\n-\t#define RX_PKT_CMPL_FLAGS2_T_L4_CS_CALC     UINT32_C(0x8)\n+\t#define RX_PKT_CMPL_FLAGS2_T_L4_CS_CALC               UINT32_C(0x8)\n \t/* This value indicates what format the metadata field is. */\n-\t#define RX_PKT_CMPL_FLAGS2_META_FORMAT_MASK UINT32_C(0xf0)\n-\t#define RX_PKT_CMPL_FLAGS2_META_FORMAT_SFT  4\n+\t#define RX_PKT_CMPL_FLAGS2_META_FORMAT_MASK           UINT32_C(0xf0)\n+\t#define RX_PKT_CMPL_FLAGS2_META_FORMAT_SFT            4\n \t/* No metadata informtaion.  Value is zero. */\n-\t#define RX_PKT_CMPL_FLAGS2_META_FORMAT_NONE   (UINT32_C(0x0) << 4)\n+\t#define RX_PKT_CMPL_FLAGS2_META_FORMAT_NONE \\\n+\t\t(UINT32_C(0x0) << 4)\n \t/*\n \t * The metadata field contains the VLAN tag and TPID value.\n \t * - metadata[11:0] contains the vlan VID value.\n@@ -2439,16 +2474,70 @@ struct rx_pkt_cmpl_hi {\n \t * - metadata[15:13] contains the vlan PRI value.\n \t * - metadata[31:16] contains the vlan TPID value.\n \t */\n-\t#define RX_PKT_CMPL_FLAGS2_META_FORMAT_VLAN   (UINT32_C(0x1) << 4)\n+\t#define RX_PKT_CMPL_FLAGS2_META_FORMAT_VLAN \\\n+\t\t(UINT32_C(0x1) << 4)\n+\t/*\n+\t * If ext_meta_format is equal to 1, the metadata field\n+\t * contains the lower 16b of the tunnel ID value, justified\n+\t * to LSB\n+\t * - VXLAN = VNI[23:0] -> VXLAN Network ID\n+\t * - Geneve (NGE) = VNI[23:0] a-> Virtual Network Identifier.\n+\t * - NVGRE = TNI[23:0] -> Tenant Network ID\n+\t * - GRE = KEY[31:0 -> key fieled with bit mask. zero if K = 0\n+\t * - IPV4 = 0 (not populated)\n+\t * - IPV6 = Flow Label[19:0]\n+\t * - PPPoE = sessionID[15:0]\n+\t * - MPLs = Outer label[19:0]\n+\t * - UPAR = Selected[31:0] with bit mask\n+\t */\n+\t#define RX_PKT_CMPL_FLAGS2_META_FORMAT_TUNNEL_ID \\\n+\t\t(UINT32_C(0x2) << 4)\n+\t/*\n+\t * if ext_meta_format is equal to 1, metadata field contains\n+\t * 16b metadata from the prepended header (chdr_data).\n+\t */\n+\t#define RX_PKT_CMPL_FLAGS2_META_FORMAT_CHDR_DATA \\\n+\t\t(UINT32_C(0x3) << 4)\n+\t/*\n+\t * If ext_meta_format is equal to 1, the metadata field contains\n+\t * the outer_l3_offset, inner_l2_offset, inner_l3_offset and\n+\t * inner_l4_size.\n+\t * - metadata[8:0] contains the outer_l3_offset.\n+\t * - metadata[17:9] contains the inner_l2_offset.\n+\t * - metadata[26:18] contains the inner_l3_offset.\n+\t * - metadata[31:27] contains the inner_l4_size.\n+\t */\n+\t#define RX_PKT_CMPL_FLAGS2_META_FORMAT_HDR_OFFSET \\\n+\t\t(UINT32_C(0x4) << 4)\n \t#define RX_PKT_CMPL_FLAGS2_META_FORMAT_LAST \\\n-\t\tRX_PKT_CMPL_FLAGS2_META_FORMAT_VLAN\n+\t\tRX_PKT_CMPL_FLAGS2_META_FORMAT_HDR_OFFSET\n \t/*\n \t * This field indicates the IP type for the inner-most IP header.\n \t * A value of '0' indicates IPv4.  A value of '1' indicates IPv6.\n \t * This value is only valid if itype indicates a packet\n \t * with an IP header.\n \t */\n-\t#define RX_PKT_CMPL_FLAGS2_IP_TYPE          UINT32_C(0x100)\n+\t#define RX_PKT_CMPL_FLAGS2_IP_TYPE                    UINT32_C(0x100)\n+\t/*\n+\t * This indicates that the complete 1's complement checksum was\n+\t * calculated for the packet.\n+\t */\n+\t#define RX_PKT_CMPL_FLAGS2_COMPLETE_CHECKSUM_CALC     UINT32_C(0x200)\n+\t/*\n+\t * The combination of this value and meta_format indicated what\n+\t * format the metadata field is.\n+\t */\n+\t#define RX_PKT_CMPL_FLAGS2_EXT_META_FORMAT_MASK       UINT32_C(0xc00)\n+\t#define RX_PKT_CMPL_FLAGS2_EXT_META_FORMAT_SFT        10\n+\t/*\n+\t * This value is the complete 1's complement checksum calculated from\n+\t * the start of the outer L3 header to the end of the packet (not\n+\t * including the ethernet crc). It is valid when the\n+\t * 'complete_checksum_calc' flag is set.\n+\t */\n+\t#define RX_PKT_CMPL_FLAGS2_COMPLETE_CHECKSUM_MASK \\\n+\t\tUINT32_C(0xffff0000)\n+\t#define RX_PKT_CMPL_FLAGS2_COMPLETE_CHECKSUM_SFT      16\n \t/*\n \t * This is data from the CFA block as indicated by the meta_format\n \t * field.\n@@ -2511,8 +2600,14 @@ struct rx_pkt_cmpl_hi {\n \t */\n \t#define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT \\\n \t\t(UINT32_C(0x3) << 1)\n+\t/*\n+\t * Flush:\n+\t * There was a bad_format error on the previous operation\n+\t */\n+\t#define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_FLUSH \\\n+\t\t(UINT32_C(0x5) << 1)\n \t#define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_LAST \\\n-\t\tRX_PKT_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT\n+\t\tRX_PKT_CMPL_ERRORS_BUFFER_ERROR_FLUSH\n \t/*\n \t * This indicates that there was an error in the IP header\n \t * checksum.\n@@ -2553,7 +2648,7 @@ struct rx_pkt_cmpl_hi {\n \t#define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_SFT                    9\n \t/*\n \t * No additional error occurred on the tunnel portion\n-\t * of the packet of the packet does not have a tunnel.\n+\t * or the packet of the packet does not have a tunnel.\n \t */\n \t#define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_NO_ERROR \\\n \t\t(UINT32_C(0x0) << 9)\n@@ -2611,7 +2706,7 @@ struct rx_pkt_cmpl_hi {\n \t#define RX_PKT_CMPL_ERRORS_PKT_ERROR_SFT                      12\n \t/*\n \t * No additional error occurred on the tunnel portion\n-\t * of the packet of the packet does not have a tunnel.\n+\t * or the packet of the packet does not have a tunnel.\n \t */\n \t#define RX_PKT_CMPL_ERRORS_PKT_ERROR_NO_ERROR \\\n \t\t(UINT32_C(0x0) << 12)\n@@ -2854,28 +2949,33 @@ struct rx_tpa_start_cmpl_hi {\n \t * inner packet and that the sum passed for all segments\n \t * included in the aggregation.\n \t */\n-\t#define RX_TPA_START_CMPL_FLAGS2_IP_CS_CALC       UINT32_C(0x1)\n+\t#define RX_TPA_START_CMPL_FLAGS2_IP_CS_CALC \\\n+\t\tUINT32_C(0x1)\n \t/*\n \t * This indicates that the TCP, UDP or ICMP checksum was\n \t * calculated for the inner packet and that the sum passed\n \t * for all segments included in the aggregation.\n \t */\n-\t#define RX_TPA_START_CMPL_FLAGS2_L4_CS_CALC       UINT32_C(0x2)\n+\t#define RX_TPA_START_CMPL_FLAGS2_L4_CS_CALC \\\n+\t\tUINT32_C(0x2)\n \t/*\n \t * This indicates that the ip checksum was calculated for the\n \t * tunnel header and that the sum passed for all segments\n \t * included in the aggregation.\n \t */\n-\t#define RX_TPA_START_CMPL_FLAGS2_T_IP_CS_CALC     UINT32_C(0x4)\n+\t#define RX_TPA_START_CMPL_FLAGS2_T_IP_CS_CALC \\\n+\t\tUINT32_C(0x4)\n \t/*\n \t * This indicates that the UDP checksum was\n \t * calculated for the tunnel packet and that the sum passed for\n \t * all segments included in the aggregation.\n \t */\n-\t#define RX_TPA_START_CMPL_FLAGS2_T_L4_CS_CALC     UINT32_C(0x8)\n+\t#define RX_TPA_START_CMPL_FLAGS2_T_L4_CS_CALC \\\n+\t\tUINT32_C(0x8)\n \t/* This value indicates what format the metadata field is. */\n-\t#define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_MASK UINT32_C(0xf0)\n-\t#define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_SFT  4\n+\t#define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_MASK \\\n+\t\tUINT32_C(0xf0)\n+\t#define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_SFT            4\n \t/* No metadata informtaion.  Value is zero. */\n \t#define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_NONE \\\n \t\t(UINT32_C(0x0) << 4)\n@@ -2888,13 +2988,71 @@ struct rx_tpa_start_cmpl_hi {\n \t */\n \t#define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_VLAN \\\n \t\t(UINT32_C(0x1) << 4)\n+\t/*\n+\t * If ext_meta_format is equal to 1, the metadata field\n+\t * contains the lower 16b of the tunnel ID value, justified\n+\t * to LSB\n+\t * - VXLAN = VNI[23:0] -> VXLAN Network ID\n+\t * - Geneve (NGE) = VNI[23:0] a-> Virtual Network Identifier.\n+\t * - NVGRE = TNI[23:0] -> Tenant Network ID\n+\t * - GRE = KEY[31:0 -> key fieled with bit mask. zero if K = 0\n+\t * - IPV4 = 0 (not populated)\n+\t * - IPV6 = Flow Label[19:0]\n+\t * - PPPoE = sessionID[15:0]\n+\t * - MPLs = Outer label[19:0]\n+\t * - UPAR = Selected[31:0] with bit mask\n+\t */\n+\t#define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_TUNNEL_ID \\\n+\t\t(UINT32_C(0x2) << 4)\n+\t/*\n+\t * if ext_meta_format is equal to 1, metadata field contains\n+\t * 16b metadata from the prepended header (chdr_data).\n+\t */\n+\t#define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_CHDR_DATA \\\n+\t\t(UINT32_C(0x3) << 4)\n+\t/*\n+\t * If ext_meta_format is equal to 1, the metadata field contains\n+\t * the outer_l3_offset, inner_l2_offset, inner_l3_offset and\n+\t * inner_l4_size.\n+\t * - metadata[8:0] contains the outer_l3_offset.\n+\t * - metadata[17:9] contains the inner_l2_offset.\n+\t * - metadata[26:18] contains the inner_l3_offset.\n+\t * - metadata[31:27] contains the inner_l4_size.\n+\t */\n+\t#define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_HDR_OFFSET \\\n+\t\t(UINT32_C(0x4) << 4)\n \t#define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_LAST \\\n-\t\tRX_TPA_START_CMPL_FLAGS2_META_FORMAT_VLAN\n+\t\tRX_TPA_START_CMPL_FLAGS2_META_FORMAT_HDR_OFFSET\n \t/*\n \t * This field indicates the IP type for the inner-most IP header.\n \t * A value of '0' indicates IPv4.  A value of '1' indicates IPv6.\n \t */\n-\t#define RX_TPA_START_CMPL_FLAGS2_IP_TYPE          UINT32_C(0x100)\n+\t#define RX_TPA_START_CMPL_FLAGS2_IP_TYPE \\\n+\t\tUINT32_C(0x100)\n+\t/*\n+\t * This indicates that the complete 1's complement checksum was\n+\t * calculated for the packet.\n+\t */\n+\t#define RX_TPA_START_CMPL_FLAGS2_COMPLETE_CHECKSUM_CALC \\\n+\t\tUINT32_C(0x200)\n+\t/*\n+\t * The combination of this value and meta_format indicated what\n+\t * format the metadata field is.\n+\t */\n+\t#define RX_TPA_START_CMPL_FLAGS2_EXT_META_FORMAT_MASK \\\n+\t\tUINT32_C(0xc00)\n+\t#define RX_TPA_START_CMPL_FLAGS2_EXT_META_FORMAT_SFT        10\n+\t/*\n+\t * This value is the complete 1's complement checksum calculated from\n+\t * the start of the outer L3 header to the end of the packet (not\n+\t * including the ethernet crc). It is valid when the\n+\t * 'complete_checksum_calc' flag is set. For TPA Start completions,\n+\t * the complete checksum is calculated for the first packet in the\n+\t * aggregation only.\n+\t */\n+\t#define RX_TPA_START_CMPL_FLAGS2_COMPLETE_CHECKSUM_MASK \\\n+\t\tUINT32_C(0xffff0000)\n+\t#define RX_TPA_START_CMPL_FLAGS2_COMPLETE_CHECKSUM_SFT      16\n \t/*\n \t * This is data from the CFA block as indicated by the meta_format\n \t * field.\n@@ -2911,13 +3069,41 @@ struct rx_tpa_start_cmpl_hi {\n \t/* When meta_format=1, this value is the VLAN TPID. */\n \t#define RX_TPA_START_CMPL_METADATA_TPID_MASK UINT32_C(0xffff0000)\n \t#define RX_TPA_START_CMPL_METADATA_TPID_SFT 16\n-\tuint16_t\tv2;\n+\tuint16_t\terrors_v2;\n \t/*\n \t * This value is written by the NIC such that it will be different\n \t * for each pass through the completion queue.   The even passes\n \t * will write 1.  The odd passes will write 0.\n \t */\n-\t#define RX_TPA_START_CMPL_V2     UINT32_C(0x1)\n+\t#define RX_TPA_START_CMPL_V2                            UINT32_C(0x1)\n+\t#define RX_TPA_START_CMPL_ERRORS_MASK \\\n+\t\tUINT32_C(0xfffe)\n+\t#define RX_TPA_START_CMPL_ERRORS_SFT                    1\n+\t/*\n+\t * This error indicates that there was some sort of problem with\n+\t * the BDs for the packet that was found after part of the\n+\t * packet was already placed.  The packet should be treated as\n+\t * invalid.\n+\t */\n+\t#define RX_TPA_START_CMPL_ERRORS_BUFFER_ERROR_MASK       UINT32_C(0xe)\n+\t#define RX_TPA_START_CMPL_ERRORS_BUFFER_ERROR_SFT        1\n+\t/* No buffer error */\n+\t#define RX_TPA_START_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER \\\n+\t\t(UINT32_C(0x0) << 1)\n+\t/*\n+\t * Bad Format:\n+\t * BDs were not formatted correctly.\n+\t */\n+\t#define RX_TPA_START_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT \\\n+\t\t(UINT32_C(0x3) << 1)\n+\t/*\n+\t * Flush:\n+\t * There was a bad_format error on the previous operation\n+\t */\n+\t#define RX_TPA_START_CMPL_ERRORS_BUFFER_ERROR_FLUSH \\\n+\t\t(UINT32_C(0x5) << 1)\n+\t#define RX_TPA_START_CMPL_ERRORS_BUFFER_ERROR_LAST \\\n+\t\tRX_TPA_START_CMPL_ERRORS_BUFFER_ERROR_FLUSH\n \t/*\n \t * This field identifies the CFA action rule that was used for this\n \t * packet.\n@@ -3034,11 +3220,11 @@ struct rx_tpa_end_cmpl {\n \t/*\n \t * This value indicates what the inner packet determined for the\n \t * packet was.\n-\t *  - 2 TCP Packet\n-\t *      Indicates that the packet was IP and TCP.  This indicates\n-\t *      that the ip_cs field is valid and that the tcp_udp_cs\n-\t *      field is valid and contains the TCP checksum.\n-\t *      This also indicates that the payload_offset field is valid.\n+\t * - 2 TCP Packet\n+\t *     Indicates that the packet was IP and TCP.  This indicates\n+\t *     that the ip_cs field is valid and that the tcp_udp_cs\n+\t *     field is valid and contains the TCP checksum.\n+\t *     This also indicates that the payload_offset field is valid.\n \t */\n \t#define RX_TPA_END_CMPL_FLAGS_ITYPE_MASK          UINT32_C(0xf000)\n \t#define RX_TPA_END_CMPL_FLAGS_ITYPE_SFT           12\n@@ -3117,13 +3303,28 @@ struct rx_tpa_end_cmpl_hi {\n \t * This value is the number of duplicate ACKs that have been\n \t * received as part of the TPA operation.\n \t */\n-\tuint32_t\ttpa_dup_acks;\n+\tuint16_t\ttpa_dup_acks;\n \t/*\n \t * This value is the number of duplicate ACKs that have been\n \t * received as part of the TPA operation.\n \t */\n \t#define RX_TPA_END_CMPL_TPA_DUP_ACKS_MASK UINT32_C(0xf)\n \t#define RX_TPA_END_CMPL_TPA_DUP_ACKS_SFT 0\n+\t/*\n+\t * This value indicated the offset in bytes from the beginning of\n+\t * the packet where the inner payload starts. This value is valid\n+\t * for TCP, UDP, FCoE and RoCE packets\n+\t */\n+\tuint8_t\tpayload_offset;\n+\t/*\n+\t * The value is the total number of aggregation buffers that were\n+\t * used in the TPA operation. All TPA aggregation buffer completions\n+\t * preceed the TPA End completion. If the value is zero, then the\n+\t * aggregation is completely contained in the buffer space provided\n+\t * in the aggregation start completion.\n+\t * Note that the field is simply provided as a cross check.\n+\t */\n+\tuint8_t\ttpa_agg_bufs;\n \t/*\n \t * This value is the valid when TPA completion is active.  It\n \t * indicates the length of the longest segment of the TPA operation\n@@ -3154,6 +3355,9 @@ struct rx_tpa_end_cmpl_hi {\n \t */\n \t#define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_MASK        UINT32_C(0xe)\n \t#define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_SFT         1\n+\t/* No buffer error */\n+\t#define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER \\\n+\t\t(UINT32_C(0x0) << 1)\n \t/*\n \t * This error occurs when there is a fatal HW problem in\n \t * the chip only.  It indicates that there were not\n@@ -3162,6 +3366,12 @@ struct rx_tpa_end_cmpl_hi {\n \t */\n \t#define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_NOT_ON_CHIP \\\n \t\t(UINT32_C(0x2) << 1)\n+\t/*\n+\t * Bad Format:\n+\t * BDs were not formatted correctly.\n+\t */\n+\t#define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT \\\n+\t\t(UINT32_C(0x3) << 1)\n \t/*\n \t * This error occurs when TPA block was not configured to\n \t * reserve adequate BDs for TPA operations on this RX\n@@ -3174,8 +3384,14 @@ struct rx_tpa_end_cmpl_hi {\n \t */\n \t#define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_RSV_ERROR \\\n \t\t(UINT32_C(0x4) << 1)\n+\t/*\n+\t * Flush:\n+\t * There was a bad_format error on the previous operation\n+\t */\n+\t#define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_FLUSH \\\n+\t\t(UINT32_C(0x5) << 1)\n \t#define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_LAST \\\n-\t\tRX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_RSV_ERROR\n+\t\tRX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_FLUSH\n \t/* unused5 is 16 b */\n \tuint16_t\tunused_4;\n \t/*\n@@ -3239,15 +3455,23 @@ struct eject_cmpl {\n \t * records.  Odd values indicate 32B\n \t * records.\n \t */\n-\t#define EJECT_CMPL_TYPE_MASK      UINT32_C(0x3f)\n-\t#define EJECT_CMPL_TYPE_SFT       0\n+\t#define EJECT_CMPL_TYPE_MASK       UINT32_C(0x3f)\n+\t#define EJECT_CMPL_TYPE_SFT        0\n \t/*\n \t * Statistics Ejection Completion:\n \t * Completion of statistics data ejection buffer.\n \t * Length = 16B\n \t */\n-\t#define EJECT_CMPL_TYPE_STAT_EJECT  UINT32_C(0x1a)\n-\t#define EJECT_CMPL_TYPE_LAST       EJECT_CMPL_TYPE_STAT_EJECT\n+\t#define EJECT_CMPL_TYPE_STAT_EJECT   UINT32_C(0x1a)\n+\t#define EJECT_CMPL_TYPE_LAST        EJECT_CMPL_TYPE_STAT_EJECT\n+\t#define EJECT_CMPL_FLAGS_MASK      UINT32_C(0xffc0)\n+\t#define EJECT_CMPL_FLAGS_SFT       6\n+\t/*\n+\t * When this bit is '1', it indicates a packet that has an\n+\t * error of some type.  Type of error is indicated in\n+\t * error_flags.\n+\t */\n+\t#define EJECT_CMPL_FLAGS_ERROR      UINT32_C(0x40)\n \t/*\n \t * This is the length of the statistics data stored in this\n \t * buffer.\n@@ -3258,13 +3482,47 @@ struct eject_cmpl {\n \t * buffer corresponds to.\n \t */\n \tuint32_t\topaque;\n-\tuint32_t\tv;\n+\tuint16_t\tv;\n \t/*\n \t * This value is written by the NIC such that it will be different\n \t * for each pass through the completion queue.   The even passes\n \t * will write 1.  The odd passes will write 0.\n \t */\n-\t#define EJECT_CMPL_V     UINT32_C(0x1)\n+\t#define EJECT_CMPL_V                              UINT32_C(0x1)\n+\t#define EJECT_CMPL_ERRORS_MASK                    UINT32_C(0xfffe)\n+\t#define EJECT_CMPL_ERRORS_SFT                     1\n+\t/*\n+\t * This error indicates that there was some sort of problem with\n+\t * the BDs for statistics ejection. The statistics ejection should\n+\t * be treated as invalid\n+\t */\n+\t#define EJECT_CMPL_ERRORS_BUFFER_ERROR_MASK        UINT32_C(0xe)\n+\t#define EJECT_CMPL_ERRORS_BUFFER_ERROR_SFT         1\n+\t/* No buffer error */\n+\t#define EJECT_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER \\\n+\t\t(UINT32_C(0x0) << 1)\n+\t/*\n+\t * Did Not Fit:\n+\t * Statistics did not fit into aggregation buffer provided.\n+\t */\n+\t#define EJECT_CMPL_ERRORS_BUFFER_ERROR_DID_NOT_FIT \\\n+\t\t(UINT32_C(0x1) << 1)\n+\t/*\n+\t * Bad Format:\n+\t * BDs were not formatted correctly.\n+\t */\n+\t#define EJECT_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT \\\n+\t\t(UINT32_C(0x3) << 1)\n+\t/*\n+\t * Flush:\n+\t * There was a bad_format error on the previous operation\n+\t */\n+\t#define EJECT_CMPL_ERRORS_BUFFER_ERROR_FLUSH \\\n+\t\t(UINT32_C(0x5) << 1)\n+\t#define EJECT_CMPL_ERRORS_BUFFER_ERROR_LAST \\\n+\t\tEJECT_CMPL_ERRORS_BUFFER_ERROR_FLUSH\n+\t/* reserved16 is 16 b */\n+\tuint16_t\treserved16;\n \t/* unused3 is 32 b */\n \tuint32_t\tunused_2;\n } __attribute__((packed));\n@@ -3470,6 +3728,24 @@ struct hwrm_async_event_cmpl {\n \t/* Default VNIC Configuration Change */\n \t#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_DEFAULT_VNIC_CHANGE \\\n \t\tUINT32_C(0x35)\n+\t/* HW flow aged */\n+\t#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_HW_FLOW_AGED \\\n+\t\tUINT32_C(0x36)\n+\t/*\n+\t * A debug notification being posted to the driver. These\n+\t * notifications are purely for diagnostic purpose and should not be\n+\t * used for functional purpose. The driver is not supposed to act\n+\t * on these messages except to log/record it.\n+\t */\n+\t#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_DEBUG_NOTIFICATION \\\n+\t\tUINT32_C(0x37)\n+\t/*\n+\t * A trace log message. This contains firmware trace logs string\n+\t * embedded in the asynchronous message. This is an experimental\n+\t * event, not meant for production use at this time.\n+\t */\n+\t#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_FW_TRACE_MSG \\\n+\t\tUINT32_C(0xfe)\n \t/* HWRM Error */\n \t#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR \\\n \t\tUINT32_C(0xff)\n@@ -4111,9 +4387,19 @@ struct hwrm_async_event_cmpl_reset_notify {\n \t/* opaque is 7 b */\n \t#define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_OPAQUE_MASK UINT32_C(0xfe)\n \t#define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_OPAQUE_SFT 1\n-\t/* 8-lsb timestamp from POR (100-msec resolution) */\n+\t/*\n+\t * 8-lsb timestamp (100-msec resolution)\n+\t * The Minimum time required for the Firmware readiness after sending this\n+\t * notification to the driver instances.\n+\t */\n \tuint8_t\ttimestamp_lo;\n-\t/* 16-lsb timestamp from POR (100-msec resolution) */\n+\t/*\n+\t * 16-lsb timestamp (100-msec resolution)\n+\t * The Maximum Firmware Reset bail out value in the order of 100\n+\t * milli seconds. The driver instances will use this value to re-initiate the\n+\t * registration process again if the core firmware didn’t set the ready\n+\t * state bit.\n+\t */\n \tuint16_t\ttimestamp_hi;\n \t/* Event specific data */\n \tuint32_t\tevent_data1;\n@@ -4829,6 +5115,73 @@ struct hwrm_async_event_cmpl_default_vnic_change {\n \t\t10\n } __attribute__((packed));\n \n+/* hwrm_async_event_cmpl_hw_flow_aged (size:128b/16B) */\n+struct hwrm_async_event_cmpl_hw_flow_aged {\n+\tuint16_t\ttype;\n+\t/*\n+\t * This field indicates the exact type of the completion.\n+\t * By convention, the LSB identifies the length of the\n+\t * record in 16B units.  Even values indicate 16B\n+\t * records.  Odd values indicate 32B\n+\t * records.\n+\t */\n+\t#define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_MASK \\\n+\t\tUINT32_C(0x3f)\n+\t#define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_SFT             0\n+\t/* HWRM Asynchronous Event Information */\n+\t#define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_HWRM_ASYNC_EVENT \\\n+\t\tUINT32_C(0x2e)\n+\t#define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_LAST \\\n+\t\tHWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_HWRM_ASYNC_EVENT\n+\t/* Identifiers of events. */\n+\tuint16_t\tevent_id;\n+\t/* Notification of a hw flow aged */\n+\t#define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_HW_FLOW_AGED \\\n+\t\tUINT32_C(0x36)\n+\t#define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_LAST \\\n+\t\tHWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_HW_FLOW_AGED\n+\t/* Event specific data */\n+\tuint32_t\tevent_data2;\n+\tuint8_t\topaque_v;\n+\t/*\n+\t * This value is written by the NIC such that it will be different\n+\t * for each pass through the completion queue.   The even passes\n+\t * will write 1.  The odd passes will write 0.\n+\t */\n+\t#define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_V          UINT32_C(0x1)\n+\t/* opaque is 7 b */\n+\t#define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_OPAQUE_MASK UINT32_C(0xfe)\n+\t#define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_OPAQUE_SFT 1\n+\t/* 8-lsb timestamp from POR (100-msec resolution) */\n+\tuint8_t\ttimestamp_lo;\n+\t/* 16-lsb timestamp from POR (100-msec resolution) */\n+\tuint16_t\ttimestamp_hi;\n+\t/* Event specific data */\n+\tuint32_t\tevent_data1;\n+\t/* Indicates flow ID this event occured on. */\n+\t#define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_ID_MASK \\\n+\t\tUINT32_C(0x7fffffff)\n+\t#define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_ID_SFT \\\n+\t\t0\n+\t/* Indicates flow direction this event occured on. */\n+\t#define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION \\\n+\t\tUINT32_C(0x80000000)\n+\t/*\n+\t * If this bit set to 0, then it indicates that the aged\n+\t * event was rx flow.\n+\t */\n+\t#define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_RX \\\n+\t\t(UINT32_C(0x0) << 31)\n+\t/*\n+\t * If this bit is set to 1, then it indicates that the aged\n+\t * event was tx flow.\n+\t */\n+\t#define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_TX \\\n+\t\t(UINT32_C(0x1) << 31)\n+\t#define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_LAST \\\n+\t\tHWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_TX\n+} __attribute__((packed));\n+\n /* hwrm_async_event_cmpl_hwrm_error (size:128b/16B) */\n struct hwrm_async_event_cmpl_hwrm_error {\n \tuint16_t\ttype;\n@@ -5682,7 +6035,7 @@ struct hwrm_func_qcaps_output {\n \t/*\n \t * If the query is for a VF, then this flag shall be ignored,\n \t * If this query is for a PF and this flag is set to 1,\n-\t * then the PF has the capability to administer another PF.\n+\t * then the PF has the administrative privilege to configure another PF\n \t */\n \t#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ADMIN_PF_SUPPORTED \\\n \t\tUINT32_C(0x40000)\n@@ -5700,6 +6053,19 @@ struct hwrm_func_qcaps_output {\n \t */\n \t#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_WCB_PUSH_MODE \\\n \t\tUINT32_C(0x100000)\n+\t/*\n+\t * If 1, then FW has capability to allocate TX rings dynamically\n+\t * in ring alloc even if PF reserved pool is zero.\n+\t * This bit will be used only for PFs.\n+\t */\n+\t#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_DYNAMIC_TX_RING_ALLOC \\\n+\t\tUINT32_C(0x200000)\n+\t/*\n+\t * When this bit is '1', it indicates that core firmware is\n+\t * capable of Hot Reset.\n+\t */\n+\t#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_HOT_RESET_CAPABLE \\\n+\t\tUINT32_C(0x400000)\n \t/*\n \t * This value is current MAC address configured for this\n \t * function. A value of 00-00-00-00-00-00 indicates no\n@@ -5864,7 +6230,7 @@ struct hwrm_func_qcfg_input {\n \tuint8_t\tunused_0[6];\n } __attribute__((packed));\n \n-/* hwrm_func_qcfg_output (size:640b/80B) */\n+/* hwrm_func_qcfg_output (size:704b/88B) */\n struct hwrm_func_qcfg_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n@@ -5951,6 +6317,13 @@ struct hwrm_func_qcfg_output {\n \t */\n \t#define HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF \\\n \t\tUINT32_C(0x40)\n+\t/*\n+\t * If set to 1, then secure mode is enabled for this function or device.\n+\t * If set to 0, then secure mode is disabled (or normal mode) for this\n+\t * function or device.\n+\t */\n+\t#define HWRM_FUNC_QCFG_OUTPUT_FLAGS_SECURE_MODE_ENABLED \\\n+\t\tUINT32_C(0x80)\n \t/*\n \t * This value is current MAC address configured for this\n \t * function. A value of 00-00-00-00-00-00 indicates no\n@@ -5995,7 +6368,8 @@ struct hwrm_func_qcfg_output {\n \tuint16_t\talloc_vnics;\n \t/*\n \t * The maximum transmission unit of the function.\n-\t * For rings allocated on this function, this default\n+\t * If the reported mtu value is non-zero then it will used for the\n+\t * rings allocated on this function. otherwise the default\n \t * value is used if ring MTU is not specified.\n \t */\n \tuint16_t\tmtu;\n@@ -6222,7 +6596,27 @@ struct hwrm_func_qcfg_output {\n \t * reserved for itself (since the NQs must be contiguous in HW).\n \t */\n \tuint16_t\talloc_msix;\n-\tuint8_t\tunused_2[5];\n+\t/*\n+\t * The number of registered VF’s associated with the PF. This field\n+\t * should be ignored when the request received on the VF interface.\n+\t * This field will be updated on the PF interface to initiate\n+\t * the unregister request on PF in the HOT Reset Process.\n+\t */\n+\tuint16_t\tregistered_vfs;\n+\tuint8_t\tunused_1[3];\n+\t/*\n+\t * For backward compatibility this field must be set to 1.\n+\t * Older drivers might look for this field to be 1 before\n+\t * processing the message.\n+\t */\n+\tuint8_t\talways_1;\n+\t/*\n+\t * This GRC address location is used by the Host driver interfaces to poll\n+\t * the adapter ready state to re-initiate the registration process again\n+\t * after receiving the RESET Notify event.\n+\t */\n+\tuint32_t\treset_addr_poll;\n+\tuint8_t\tunused_2[3];\n \t/*\n \t * This field is used in Output records to indicate that the output\n \t * is completely written to RAM.  This field should be read as '1'\n@@ -6424,6 +6818,13 @@ struct hwrm_func_cfg_input {\n \t */\n \t#define HWRM_FUNC_CFG_INPUT_FLAGS_TRUSTED_VF_ENABLE \\\n \t\tUINT32_C(0x200000)\n+\t/*\n+\t * When this bit it set, even if PF reserved pool size is zero,\n+\t * FW will allow driver to create TX rings in ring alloc,\n+\t * by reserving TX ring, S3 node dynamically.\n+\t */\n+\t#define HWRM_FUNC_CFG_INPUT_FLAGS_DYNAMIC_TX_RING_ALLOC \\\n+\t\tUINT32_C(0x400000)\n \tuint32_t\tenables;\n \t/*\n \t * This bit must be '1' for the mtu field to be\n@@ -7181,6 +7582,17 @@ struct hwrm_func_drv_rgtr_input {\n \t */\n \t#define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FLOW_HANDLE_64BIT_MODE \\\n \t\tUINT32_C(0x8)\n+\t/*\n+\t * When this bit is '1', the function is indicating support of\n+\t * Hot Reset. The driver interface will destroy the resources,\n+\t * unregister the function and register again up on receiving\n+\t * the RESET_NOTIFY Async notification from the core firmware.\n+\t * The core firmware will this use flag and trigger the Hot Reset\n+\t * process only if all the registered driver instances are capable\n+\t * of this support.\n+\t */\n+\t#define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_HOT_RESET_SUPPORT \\\n+\t\tUINT32_C(0x10)\n \tuint32_t\tenables;\n \t/*\n \t * This bit must be '1' for the os_type field to be\n@@ -10774,6 +11186,8 @@ struct hwrm_port_phy_cfg_input {\n \t#define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB  UINT32_C(0x1f4)\n \t/* 100Gb link speed */\n \t#define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100GB UINT32_C(0x3e8)\n+\t/* 200Gb link speed */\n+\t#define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_200GB UINT32_C(0x7d0)\n \t/* 10Mb link speed */\n \t#define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10MB  UINT32_C(0xffff)\n \t#define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_LAST \\\n@@ -10878,6 +11292,8 @@ struct hwrm_port_phy_cfg_input {\n \t#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_50GB  UINT32_C(0x1f4)\n \t/* 100Gb link speed */\n \t#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100GB UINT32_C(0x3e8)\n+\t/* 200Gb link speed */\n+\t#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_200GB UINT32_C(0x7d0)\n \t/* 10Mb link speed */\n \t#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_10MB  UINT32_C(0xffff)\n \t#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_LAST \\\n@@ -10930,6 +11346,9 @@ struct hwrm_port_phy_cfg_input {\n \t/* 10Mb link speed (Full-duplex) */\n \t#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10MB \\\n \t\tUINT32_C(0x2000)\n+\t/* 200Gb link speed */\n+\t#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_200GB \\\n+\t\tUINT32_C(0x4000)\n \t/* This value controls the wirespeed feature. */\n \tuint8_t\twirespeed;\n \t/* Wirespeed feature is disabled. */\n@@ -11159,6 +11578,8 @@ struct hwrm_port_phy_qcfg_output {\n \t#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB  UINT32_C(0x1f4)\n \t/* 100Gb link speed */\n \t#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100GB UINT32_C(0x3e8)\n+\t/* 200Gb link speed */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_200GB UINT32_C(0x7d0)\n \t/* 10Mb link speed */\n \t#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10MB  UINT32_C(0xffff)\n \t#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_LAST \\\n@@ -11238,6 +11659,9 @@ struct hwrm_port_phy_qcfg_output {\n \t/* 10Mb link speed (Full-duplex) */\n \t#define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10MB \\\n \t\tUINT32_C(0x2000)\n+\t/* 200Gb link speed */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_200GB \\\n+\t\tUINT32_C(0x4000)\n \t/*\n \t * Current setting of forced link speed.\n \t * When the link speed is not being forced, this\n@@ -11267,6 +11691,9 @@ struct hwrm_port_phy_qcfg_output {\n \t/* 100Gb link speed */\n \t#define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_100GB \\\n \t\tUINT32_C(0x3e8)\n+\t/* 200Gb link speed */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_200GB \\\n+\t\tUINT32_C(0x7d0)\n \t/* 10Mb link speed */\n \t#define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_10MB \\\n \t\tUINT32_C(0xffff)\n@@ -11353,6 +11780,8 @@ struct hwrm_port_phy_qcfg_output {\n \t#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_50GB  UINT32_C(0x1f4)\n \t/* 100Gb link speed */\n \t#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_100GB UINT32_C(0x3e8)\n+\t/* 200Gb link speed */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_200GB UINT32_C(0x7d0)\n \t/* 10Mb link speed */\n \t#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_10MB \\\n \t\tUINT32_C(0xffff)\n@@ -11408,6 +11837,9 @@ struct hwrm_port_phy_qcfg_output {\n \t/* 10Mb link speed (Full-duplex) */\n \t#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_10MB \\\n \t\tUINT32_C(0x2000)\n+\t/* 200Gb link speed */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_200GB \\\n+\t\tUINT32_C(0x4000)\n \t/* Current setting for wirespeed. */\n \tuint8_t\twirespeed;\n \t/* Wirespeed feature is disabled. */\n@@ -11574,8 +12006,20 @@ struct hwrm_port_phy_qcfg_output {\n \t/* 1G_baseCX */\n \t#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_1G_BASECX \\\n \t\tUINT32_C(0x1b)\n+\t/* 100G_BASECR4 */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASECR4 \\\n+\t\tUINT32_C(0x1c)\n+\t/* 100G_BASESR4 */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASESR4 \\\n+\t\tUINT32_C(0x1d)\n+\t/* 100G_BASELR4 */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASELR4 \\\n+\t\tUINT32_C(0x1e)\n+\t/* 100G_BASEER4 */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASEER4 \\\n+\t\tUINT32_C(0x1f)\n \t#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_LAST \\\n-\t\tHWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_1G_BASECX\n+\t\tHWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASEER4\n \t/* This value represents a media type. */\n \tuint8_t\tmedia_type;\n \t/* Unknown */\n@@ -21081,6 +21525,15 @@ struct hwrm_cfa_l2_filter_alloc_input {\n \t/* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */\n \t#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \\\n \t\tUINT32_C(0x9)\n+\t/* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */\n+\t#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \\\n+\t\tUINT32_C(0xa)\n+\t/* Use fixed layer 2 ether type of 0xFFFF */\n+\t#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \\\n+\t\tUINT32_C(0xb)\n+\t/* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */\n+\t#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \\\n+\t\tUINT32_C(0xc)\n \t/* Any tunneled traffic */\n \t#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \\\n \t\tUINT32_C(0xff)\n@@ -21887,6 +22340,15 @@ struct hwrm_cfa_tunnel_filter_alloc_input {\n \t/* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */\n \t#define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \\\n \t\tUINT32_C(0x9)\n+\t/* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */\n+\t#define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \\\n+\t\tUINT32_C(0xa)\n+\t/* Use fixed layer 2 ether type of 0xFFFF */\n+\t#define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \\\n+\t\tUINT32_C(0xb)\n+\t/* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */\n+\t#define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \\\n+\t\tUINT32_C(0xc)\n \t/* Any tunneled traffic */\n \t#define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \\\n \t\tUINT32_C(0xff)\n@@ -22107,6 +22569,12 @@ struct hwrm_cfa_redirect_tunnel_type_alloc_input {\n \t/* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */\n \t#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \\\n \t\tUINT32_C(0xa)\n+\t/* Use fixed layer 2 ether type of 0xFFFF */\n+\t#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \\\n+\t\tUINT32_C(0xb)\n+\t/* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */\n+\t#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \\\n+\t\tUINT32_C(0xc)\n \t/* Any tunneled traffic */\n \t#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \\\n \t\tUINT32_C(0xff)\n@@ -22212,6 +22680,12 @@ struct hwrm_cfa_redirect_tunnel_type_free_input {\n \t/* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */\n \t#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_IPGRE_V1 \\\n \t\tUINT32_C(0xa)\n+\t/* Use fixed layer 2 ether type of 0xFFFF */\n+\t#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_L2_ETYPE \\\n+\t\tUINT32_C(0xb)\n+\t/* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */\n+\t#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \\\n+\t\tUINT32_C(0xc)\n \t/* Any tunneled traffic */\n \t#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_ANYTUNNEL \\\n \t\tUINT32_C(0xff)\n@@ -22312,6 +22786,12 @@ struct hwrm_cfa_redirect_tunnel_type_info_input {\n \t/* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */\n \t#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_IPGRE_V1 \\\n \t\tUINT32_C(0xa)\n+\t/* Use fixed layer 2 ether type of 0xFFFF */\n+\t#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_L2_ETYPE \\\n+\t\tUINT32_C(0xb)\n+\t/* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */\n+\t#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \\\n+\t\tUINT32_C(0xc)\n \t/* Any tunneled traffic */\n \t#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_ANYTUNNEL \\\n \t\tUINT32_C(0xff)\n@@ -22517,8 +22997,14 @@ struct hwrm_cfa_encap_record_alloc_input {\n \t/* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */\n \t#define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VXLAN_V4 \\\n \t\tUINT32_C(0x9)\n+\t/* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */\n+\t#define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_IPGRE_V1 \\\n+\t\tUINT32_C(0xa)\n+\t/* Use fixed layer 2 ether type of 0xFFFF */\n+\t#define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_L2_ETYPE \\\n+\t\tUINT32_C(0xb)\n \t#define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_LAST \\\n-\t\tHWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VXLAN_V4\n+\t\tHWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_L2_ETYPE\n \tuint8_t\tunused_0[3];\n \t/* This value is encap data used for the given encap type. */\n \tuint32_t\tencap_data[20];\n@@ -22872,6 +23358,15 @@ struct hwrm_cfa_ntuple_filter_alloc_input {\n \t/* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */\n \t#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \\\n \t\tUINT32_C(0x9)\n+\t/* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */\n+\t#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \\\n+\t\tUINT32_C(0xa)\n+\t/* Use fixed layer 2 ether type of 0xFFFF */\n+\t#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \\\n+\t\tUINT32_C(0xb)\n+\t/* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */\n+\t#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \\\n+\t\tUINT32_C(0xc)\n \t/* Any tunneled traffic */\n \t#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \\\n \t\tUINT32_C(0xff)\n@@ -23381,6 +23876,15 @@ struct hwrm_cfa_em_flow_alloc_input {\n \t/* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */\n \t#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \\\n \t\tUINT32_C(0x9)\n+\t/* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */\n+\t#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \\\n+\t\tUINT32_C(0xa)\n+\t/* Use fixed layer 2 ether type of 0xFFFF */\n+\t#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \\\n+\t\tUINT32_C(0xb)\n+\t/* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */\n+\t#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \\\n+\t\tUINT32_C(0xc)\n \t/* Any tunneled traffic */\n \t#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \\\n \t\tUINT32_C(0xff)\n@@ -23586,13 +24090,13 @@ struct hwrm_cfa_em_flow_free_output {\n \tuint8_t\tvalid;\n } __attribute__((packed));\n \n-/*******************************\n- * hwrm_cfa_decap_filter_alloc *\n- *******************************/\n+/********************************\n+ * hwrm_cfa_meter_profile_alloc *\n+ ********************************/\n \n \n-/* hwrm_cfa_decap_filter_alloc_input (size:832b/104B) */\n-struct hwrm_cfa_decap_filter_alloc_input {\n+/* hwrm_cfa_meter_profile_alloc_input (size:320b/40B) */\n+struct hwrm_cfa_meter_profile_alloc_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n \t/*\n@@ -23620,266 +24124,1670 @@ struct hwrm_cfa_decap_filter_alloc_input {\n \t * point to a physically contiguous block of memory.\n \t */\n \tuint64_t\tresp_addr;\n-\tuint32_t\tflags;\n-\t/* ovs_tunnel is 1 b */\n-\t#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_FLAGS_OVS_TUNNEL \\\n-\t\tUINT32_C(0x1)\n-\tuint32_t\tenables;\n+\tuint8_t\tflags;\n \t/*\n-\t * This bit must be '1' for the tunnel_type field to be\n-\t * configured.\n+\t * Enumeration denoting the RX, TX type of the resource.\n+\t * This enumeration is used for resources that are similar for both\n+\t * TX and RX paths of the chip.\n \t */\n-\t#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \\\n+\t#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH     UINT32_C(0x1)\n+\t/* tx path */\n+\t#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH_TX \\\n+\t\tUINT32_C(0x0)\n+\t/* rx path */\n+\t#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH_RX \\\n \t\tUINT32_C(0x1)\n-\t/*\n-\t * This bit must be '1' for the tunnel_id field to be\n-\t * configured.\n-\t */\n-\t#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_ID \\\n+\t#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH_LAST \\\n+\t\tHWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH_RX\n+\t/* The meter algorithm type. */\n+\tuint8_t\tmeter_type;\n+\t/* RFC 2697 (srTCM) */\n+\t#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_RFC2697 \\\n+\t\tUINT32_C(0x0)\n+\t/* RFC 2698 (trTCM) */\n+\t#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_RFC2698 \\\n+\t\tUINT32_C(0x1)\n+\t/* RFC 4115 (trTCM) */\n+\t#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_RFC4115 \\\n \t\tUINT32_C(0x2)\n+\t#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_LAST \\\n+\t\tHWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_RFC4115\n \t/*\n-\t * This bit must be '1' for the src_macaddr field to be\n-\t * configured.\n+\t * This field is reserved for the future use.\n+\t * It shall be set to 0.\n \t */\n-\t#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR \\\n-\t\tUINT32_C(0x4)\n+\tuint16_t\treserved1;\n \t/*\n-\t * This bit must be '1' for the dst_macaddr field to be\n-\t * configured.\n+\t * This field is reserved for the future use.\n+\t * It shall be set to 0.\n \t */\n-\t#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_MACADDR \\\n-\t\tUINT32_C(0x8)\n-\t/*\n+\tuint32_t\treserved2;\n+\t/* A meter rate specified in bytes-per-second. */\n+\tuint32_t\tcommit_rate;\n+\t/* The bandwidth value. */\n+\t#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_MASK \\\n+\t\tUINT32_C(0xfffffff)\n+\t#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_SFT \\\n+\t\t0\n+\t/* The granularity of the value (bits or bytes). */\n+\t#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE \\\n+\t\tUINT32_C(0x10000000)\n+\t/* Value is in bits. */\n+\t#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE_BITS \\\n+\t\t(UINT32_C(0x0) << 28)\n+\t/* Value is in bytes. */\n+\t#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE_BYTES \\\n+\t\t(UINT32_C(0x1) << 28)\n+\t#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE_LAST \\\n+\t\tHWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE_BYTES\n+\t/* bw_value_unit is 3 b */\n+\t#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_MASK \\\n+\t\tUINT32_C(0xe0000000)\n+\t#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_SFT \\\n+\t\t29\n+\t/* Value is in Mb or MB (base 10). */\n+\t#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_MEGA \\\n+\t\t(UINT32_C(0x0) << 29)\n+\t/* Value is in Kb or KB (base 10). */\n+\t#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_KILO \\\n+\t\t(UINT32_C(0x2) << 29)\n+\t/* Value is in bits or bytes. */\n+\t#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_BASE \\\n+\t\t(UINT32_C(0x4) << 29)\n+\t/* Value is in Gb or GB (base 10). */\n+\t#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_GIGA \\\n+\t\t(UINT32_C(0x6) << 29)\n+\t/* Value is in 1/100th of a percentage of total bandwidth. */\n+\t#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_PERCENT1_100 \\\n+\t\t(UINT32_C(0x1) << 29)\n+\t/* Invalid unit */\n+\t#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_INVALID \\\n+\t\t(UINT32_C(0x7) << 29)\n+\t#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_LAST \\\n+\t\tHWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_INVALID\n+\t/* A meter burst size specified in bytes. */\n+\tuint32_t\tcommit_burst;\n+\t/* The bandwidth value. */\n+\t#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_MASK \\\n+\t\tUINT32_C(0xfffffff)\n+\t#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_SFT \\\n+\t\t0\n+\t/* The granularity of the value (bits or bytes). */\n+\t#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE \\\n+\t\tUINT32_C(0x10000000)\n+\t/* Value is in bits. */\n+\t#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE_BITS \\\n+\t\t(UINT32_C(0x0) << 28)\n+\t/* Value is in bytes. */\n+\t#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE_BYTES \\\n+\t\t(UINT32_C(0x1) << 28)\n+\t#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE_LAST \\\n+\t\tHWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE_BYTES\n+\t/* bw_value_unit is 3 b */\n+\t#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_MASK \\\n+\t\tUINT32_C(0xe0000000)\n+\t#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_SFT \\\n+\t\t29\n+\t/* Value is in Mb or MB (base 10). */\n+\t#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_MEGA \\\n+\t\t(UINT32_C(0x0) << 29)\n+\t/* Value is in Kb or KB (base 10). */\n+\t#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_KILO \\\n+\t\t(UINT32_C(0x2) << 29)\n+\t/* Value is in bits or bytes. */\n+\t#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_BASE \\\n+\t\t(UINT32_C(0x4) << 29)\n+\t/* Value is in Gb or GB (base 10). */\n+\t#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_GIGA \\\n+\t\t(UINT32_C(0x6) << 29)\n+\t/* Value is in 1/100th of a percentage of total bandwidth. */\n+\t#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_PERCENT1_100 \\\n+\t\t(UINT32_C(0x1) << 29)\n+\t/* Invalid unit */\n+\t#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_INVALID \\\n+\t\t(UINT32_C(0x7) << 29)\n+\t#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_LAST \\\n+\t\tHWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_INVALID\n+\t/* A meter rate specified in bytes-per-second. */\n+\tuint32_t\texcess_peak_rate;\n+\t/* The bandwidth value. */\n+\t#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_MASK \\\n+\t\tUINT32_C(0xfffffff)\n+\t#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_SFT \\\n+\t\t0\n+\t/* The granularity of the value (bits or bytes). */\n+\t#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE \\\n+\t\tUINT32_C(0x10000000)\n+\t/* Value is in bits. */\n+\t#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE_BITS \\\n+\t\t(UINT32_C(0x0) << 28)\n+\t/* Value is in bytes. */\n+\t#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE_BYTES \\\n+\t\t(UINT32_C(0x1) << 28)\n+\t#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE_LAST \\\n+\t\tHWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE_BYTES\n+\t/* bw_value_unit is 3 b */\n+\t#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_MASK \\\n+\t\tUINT32_C(0xe0000000)\n+\t#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_SFT \\\n+\t\t29\n+\t/* Value is in Mb or MB (base 10). */\n+\t#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_MEGA \\\n+\t\t(UINT32_C(0x0) << 29)\n+\t/* Value is in Kb or KB (base 10). */\n+\t#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_KILO \\\n+\t\t(UINT32_C(0x2) << 29)\n+\t/* Value is in bits or bytes. */\n+\t#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_BASE \\\n+\t\t(UINT32_C(0x4) << 29)\n+\t/* Value is in Gb or GB (base 10). */\n+\t#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_GIGA \\\n+\t\t(UINT32_C(0x6) << 29)\n+\t/* Value is in 1/100th of a percentage of total bandwidth. */\n+\t#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_PERCENT1_100 \\\n+\t\t(UINT32_C(0x1) << 29)\n+\t/* Invalid unit */\n+\t#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_INVALID \\\n+\t\t(UINT32_C(0x7) << 29)\n+\t#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_LAST \\\n+\t\tHWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_INVALID\n+\t/* A meter burst size specified in bytes. */\n+\tuint32_t\texcess_peak_burst;\n+\t/* The bandwidth value. */\n+\t#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_MASK \\\n+\t\tUINT32_C(0xfffffff)\n+\t#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_SFT \\\n+\t\t0\n+\t/* The granularity of the value (bits or bytes). */\n+\t#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE \\\n+\t\tUINT32_C(0x10000000)\n+\t/* Value is in bits. */\n+\t#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE_BITS \\\n+\t\t(UINT32_C(0x0) << 28)\n+\t/* Value is in bytes. */\n+\t#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE_BYTES \\\n+\t\t(UINT32_C(0x1) << 28)\n+\t#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE_LAST \\\n+\t\tHWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE_BYTES\n+\t/* bw_value_unit is 3 b */\n+\t#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_MASK \\\n+\t\tUINT32_C(0xe0000000)\n+\t#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_SFT \\\n+\t\t29\n+\t/* Value is in Mb or MB (base 10). */\n+\t#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_MEGA \\\n+\t\t(UINT32_C(0x0) << 29)\n+\t/* Value is in Kb or KB (base 10). */\n+\t#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_KILO \\\n+\t\t(UINT32_C(0x2) << 29)\n+\t/* Value is in bits or bytes. */\n+\t#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_BASE \\\n+\t\t(UINT32_C(0x4) << 29)\n+\t/* Value is in Gb or GB (base 10). */\n+\t#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_GIGA \\\n+\t\t(UINT32_C(0x6) << 29)\n+\t/* Value is in 1/100th of a percentage of total bandwidth. */\n+\t#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_PERCENT1_100 \\\n+\t\t(UINT32_C(0x1) << 29)\n+\t/* Invalid unit */\n+\t#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_INVALID \\\n+\t\t(UINT32_C(0x7) << 29)\n+\t#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_LAST \\\n+\t\tHWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_INVALID\n+} __attribute__((packed));\n+\n+/* hwrm_cfa_meter_profile_alloc_output (size:128b/16B) */\n+struct hwrm_cfa_meter_profile_alloc_output {\n+\t/* The specific error status for the command. */\n+\tuint16_t\terror_code;\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/* The sequence ID from the original command. */\n+\tuint16_t\tseq_id;\n+\t/* The length of the response data in number of bytes. */\n+\tuint16_t\tresp_len;\n+\t/* This value identifies a meter profile in CFA. */\n+\tuint16_t\tmeter_profile_id;\n+\t/*\n+\t * A value of 0xfff is considered invalid and implies the\n+\t * profile is not configured.\n+\t */\n+\t#define HWRM_CFA_METER_PROFILE_ALLOC_OUTPUT_METER_PROFILE_ID_INVALID \\\n+\t\tUINT32_C(0xffff)\n+\t#define HWRM_CFA_METER_PROFILE_ALLOC_OUTPUT_METER_PROFILE_ID_LAST \\\n+\t\tHWRM_CFA_METER_PROFILE_ALLOC_OUTPUT_METER_PROFILE_ID_INVALID\n+\tuint8_t\tunused_0[5];\n+\t/*\n+\t * This field is used in Output records to indicate that the output\n+\t * is completely written to RAM.  This field should be read as '1'\n+\t * to indicate that the output has been completely written.\n+\t * When writing a command completion or response to an internal processor,\n+\t * the order of writes has to be such that this field is written last.\n+\t */\n+\tuint8_t\tvalid;\n+} __attribute__((packed));\n+\n+/*******************************\n+ * hwrm_cfa_meter_profile_free *\n+ *******************************/\n+\n+\n+/* hwrm_cfa_meter_profile_free_input (size:192b/24B) */\n+struct hwrm_cfa_meter_profile_free_input {\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/*\n+\t * The completion ring to send the completion event on. This should\n+\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n+\t */\n+\tuint16_t\tcmpl_ring;\n+\t/*\n+\t * The sequence ID is used by the driver for tracking multiple\n+\t * commands. This ID is treated as opaque data by the firmware and\n+\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n+\t */\n+\tuint16_t\tseq_id;\n+\t/*\n+\t * The target ID of the command:\n+\t * * 0x0-0xFFF8 - The function ID\n+\t * * 0xFFF8-0xFFFE - Reserved for internal processors\n+\t * * 0xFFFF - HWRM\n+\t */\n+\tuint16_t\ttarget_id;\n+\t/*\n+\t * A physical address pointer pointing to a host buffer that the\n+\t * command's response data will be written. This can be either a host\n+\t * physical address (HPA) or a guest physical address (GPA) and must\n+\t * point to a physically contiguous block of memory.\n+\t */\n+\tuint64_t\tresp_addr;\n+\tuint8_t\tflags;\n+\t/*\n+\t * Enumeration denoting the RX, TX type of the resource.\n+\t * This enumeration is used for resources that are similar for both\n+\t * TX and RX paths of the chip.\n+\t */\n+\t#define HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH     UINT32_C(0x1)\n+\t/* tx path */\n+\t#define HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH_TX \\\n+\t\tUINT32_C(0x0)\n+\t/* rx path */\n+\t#define HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH_RX \\\n+\t\tUINT32_C(0x1)\n+\t#define HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH_LAST \\\n+\t\tHWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH_RX\n+\tuint8_t\tunused_0;\n+\t/* This value identifies a meter profile in CFA. */\n+\tuint16_t\tmeter_profile_id;\n+\t/*\n+\t * A value of 0xfff is considered invalid and implies the\n+\t * profile is not configured.\n+\t */\n+\t#define HWRM_CFA_METER_PROFILE_FREE_INPUT_METER_PROFILE_ID_INVALID \\\n+\t\tUINT32_C(0xffff)\n+\t#define HWRM_CFA_METER_PROFILE_FREE_INPUT_METER_PROFILE_ID_LAST \\\n+\t\tHWRM_CFA_METER_PROFILE_FREE_INPUT_METER_PROFILE_ID_INVALID\n+\tuint8_t\tunused_1[4];\n+} __attribute__((packed));\n+\n+/* hwrm_cfa_meter_profile_free_output (size:128b/16B) */\n+struct hwrm_cfa_meter_profile_free_output {\n+\t/* The specific error status for the command. */\n+\tuint16_t\terror_code;\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/* The sequence ID from the original command. */\n+\tuint16_t\tseq_id;\n+\t/* The length of the response data in number of bytes. */\n+\tuint16_t\tresp_len;\n+\tuint8_t\tunused_0[7];\n+\t/*\n+\t * This field is used in Output records to indicate that the output\n+\t * is completely written to RAM.  This field should be read as '1'\n+\t * to indicate that the output has been completely written.\n+\t * When writing a command completion or response to an internal processor,\n+\t * the order of writes has to be such that this field is written last.\n+\t */\n+\tuint8_t\tvalid;\n+} __attribute__((packed));\n+\n+/******************************\n+ * hwrm_cfa_meter_profile_cfg *\n+ ******************************/\n+\n+\n+/* hwrm_cfa_meter_profile_cfg_input (size:320b/40B) */\n+struct hwrm_cfa_meter_profile_cfg_input {\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/*\n+\t * The completion ring to send the completion event on. This should\n+\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n+\t */\n+\tuint16_t\tcmpl_ring;\n+\t/*\n+\t * The sequence ID is used by the driver for tracking multiple\n+\t * commands. This ID is treated as opaque data by the firmware and\n+\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n+\t */\n+\tuint16_t\tseq_id;\n+\t/*\n+\t * The target ID of the command:\n+\t * * 0x0-0xFFF8 - The function ID\n+\t * * 0xFFF8-0xFFFE - Reserved for internal processors\n+\t * * 0xFFFF - HWRM\n+\t */\n+\tuint16_t\ttarget_id;\n+\t/*\n+\t * A physical address pointer pointing to a host buffer that the\n+\t * command's response data will be written. This can be either a host\n+\t * physical address (HPA) or a guest physical address (GPA) and must\n+\t * point to a physically contiguous block of memory.\n+\t */\n+\tuint64_t\tresp_addr;\n+\tuint8_t\tflags;\n+\t/*\n+\t * Enumeration denoting the RX, TX type of the resource.\n+\t * This enumeration is used for resources that are similar for both\n+\t * TX and RX paths of the chip.\n+\t */\n+\t#define HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH     UINT32_C(0x1)\n+\t/* tx path */\n+\t#define HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH_TX    UINT32_C(0x0)\n+\t/* rx path */\n+\t#define HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH_RX    UINT32_C(0x1)\n+\t#define HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH_LAST \\\n+\t\tHWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH_RX\n+\t/* The meter algorithm type. */\n+\tuint8_t\tmeter_type;\n+\t/* RFC 2697 (srTCM) */\n+\t#define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_RFC2697 \\\n+\t\tUINT32_C(0x0)\n+\t/* RFC 2698 (trTCM) */\n+\t#define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_RFC2698 \\\n+\t\tUINT32_C(0x1)\n+\t/* RFC 4115 (trTCM) */\n+\t#define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_RFC4115 \\\n+\t\tUINT32_C(0x2)\n+\t#define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_LAST \\\n+\t\tHWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_RFC4115\n+\t/* This value identifies a meter profile in CFA. */\n+\tuint16_t\tmeter_profile_id;\n+\t/*\n+\t * A value of 0xfff is considered invalid and implies the\n+\t * profile is not configured.\n+\t */\n+\t#define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_PROFILE_ID_INVALID \\\n+\t\tUINT32_C(0xffff)\n+\t#define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_PROFILE_ID_LAST \\\n+\t\tHWRM_CFA_METER_PROFILE_CFG_INPUT_METER_PROFILE_ID_INVALID\n+\t/*\n+\t * This field is reserved for the future use.\n+\t * It shall be set to 0.\n+\t */\n+\tuint32_t\treserved;\n+\t/* A meter rate specified in bytes-per-second. */\n+\tuint32_t\tcommit_rate;\n+\t/* The bandwidth value. */\n+\t#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_MASK \\\n+\t\tUINT32_C(0xfffffff)\n+\t#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_SFT \\\n+\t\t0\n+\t/* The granularity of the value (bits or bytes). */\n+\t#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE \\\n+\t\tUINT32_C(0x10000000)\n+\t/* Value is in bits. */\n+\t#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE_BITS \\\n+\t\t(UINT32_C(0x0) << 28)\n+\t/* Value is in bytes. */\n+\t#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE_BYTES \\\n+\t\t(UINT32_C(0x1) << 28)\n+\t#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE_LAST \\\n+\t\tHWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE_BYTES\n+\t/* bw_value_unit is 3 b */\n+\t#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_MASK \\\n+\t\tUINT32_C(0xe0000000)\n+\t#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_SFT \\\n+\t\t29\n+\t/* Value is in Mb or MB (base 10). */\n+\t#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_MEGA \\\n+\t\t(UINT32_C(0x0) << 29)\n+\t/* Value is in Kb or KB (base 10). */\n+\t#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_KILO \\\n+\t\t(UINT32_C(0x2) << 29)\n+\t/* Value is in bits or bytes. */\n+\t#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_BASE \\\n+\t\t(UINT32_C(0x4) << 29)\n+\t/* Value is in Gb or GB (base 10). */\n+\t#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_GIGA \\\n+\t\t(UINT32_C(0x6) << 29)\n+\t/* Value is in 1/100th of a percentage of total bandwidth. */\n+\t#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_PERCENT1_100 \\\n+\t\t(UINT32_C(0x1) << 29)\n+\t/* Invalid unit */\n+\t#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_INVALID \\\n+\t\t(UINT32_C(0x7) << 29)\n+\t#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_LAST \\\n+\t\tHWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_INVALID\n+\t/* A meter burst size specified in bytes. */\n+\tuint32_t\tcommit_burst;\n+\t/* The bandwidth value. */\n+\t#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_MASK \\\n+\t\tUINT32_C(0xfffffff)\n+\t#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_SFT \\\n+\t\t0\n+\t/* The granularity of the value (bits or bytes). */\n+\t#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE \\\n+\t\tUINT32_C(0x10000000)\n+\t/* Value is in bits. */\n+\t#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE_BITS \\\n+\t\t(UINT32_C(0x0) << 28)\n+\t/* Value is in bytes. */\n+\t#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE_BYTES \\\n+\t\t(UINT32_C(0x1) << 28)\n+\t#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE_LAST \\\n+\t\tHWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE_BYTES\n+\t/* bw_value_unit is 3 b */\n+\t#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_MASK \\\n+\t\tUINT32_C(0xe0000000)\n+\t#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_SFT \\\n+\t\t29\n+\t/* Value is in Mb or MB (base 10). */\n+\t#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_MEGA \\\n+\t\t(UINT32_C(0x0) << 29)\n+\t/* Value is in Kb or KB (base 10). */\n+\t#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_KILO \\\n+\t\t(UINT32_C(0x2) << 29)\n+\t/* Value is in bits or bytes. */\n+\t#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_BASE \\\n+\t\t(UINT32_C(0x4) << 29)\n+\t/* Value is in Gb or GB (base 10). */\n+\t#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_GIGA \\\n+\t\t(UINT32_C(0x6) << 29)\n+\t/* Value is in 1/100th of a percentage of total bandwidth. */\n+\t#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_PERCENT1_100 \\\n+\t\t(UINT32_C(0x1) << 29)\n+\t/* Invalid unit */\n+\t#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_INVALID \\\n+\t\t(UINT32_C(0x7) << 29)\n+\t#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_LAST \\\n+\t\tHWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_INVALID\n+\t/* A meter rate specified in bytes-per-second. */\n+\tuint32_t\texcess_peak_rate;\n+\t/* The bandwidth value. */\n+\t#define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_MASK \\\n+\t\tUINT32_C(0xfffffff)\n+\t#define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_SFT \\\n+\t\t0\n+\t/* The granularity of the value (bits or bytes). */\n+\t#define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE \\\n+\t\tUINT32_C(0x10000000)\n+\t/* Value is in bits. */\n+\t#define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE_BITS \\\n+\t\t(UINT32_C(0x0) << 28)\n+\t/* Value is in bytes. */\n+\t#define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE_BYTES \\\n+\t\t(UINT32_C(0x1) << 28)\n+\t#define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE_LAST \\\n+\t\tHWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE_BYTES\n+\t/* bw_value_unit is 3 b */\n+\t#define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_MASK \\\n+\t\tUINT32_C(0xe0000000)\n+\t#define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_SFT \\\n+\t\t29\n+\t/* Value is in Mb or MB (base 10). */\n+\t#define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_MEGA \\\n+\t\t(UINT32_C(0x0) << 29)\n+\t/* Value is in Kb or KB (base 10). */\n+\t#define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_KILO \\\n+\t\t(UINT32_C(0x2) << 29)\n+\t/* Value is in bits or bytes. */\n+\t#define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_BASE \\\n+\t\t(UINT32_C(0x4) << 29)\n+\t/* Value is in Gb or GB (base 10). */\n+\t#define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_GIGA \\\n+\t\t(UINT32_C(0x6) << 29)\n+\t/* Value is in 1/100th of a percentage of total bandwidth. */\n+\t#define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_PERCENT1_100 \\\n+\t\t(UINT32_C(0x1) << 29)\n+\t/* Invalid unit */\n+\t#define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_INVALID \\\n+\t\t(UINT32_C(0x7) << 29)\n+\t#define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_LAST \\\n+\t\tHWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_INVALID\n+\t/* A meter burst size specified in bytes. */\n+\tuint32_t\texcess_peak_burst;\n+\t/* The bandwidth value. */\n+\t#define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_MASK \\\n+\t\tUINT32_C(0xfffffff)\n+\t#define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_SFT \\\n+\t\t0\n+\t/* The granularity of the value (bits or bytes). */\n+\t#define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE \\\n+\t\tUINT32_C(0x10000000)\n+\t/* Value is in bits. */\n+\t#define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE_BITS \\\n+\t\t(UINT32_C(0x0) << 28)\n+\t/* Value is in bytes. */\n+\t#define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE_BYTES \\\n+\t\t(UINT32_C(0x1) << 28)\n+\t#define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE_LAST \\\n+\t\tHWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE_BYTES\n+\t/* bw_value_unit is 3 b */\n+\t#define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_MASK \\\n+\t\tUINT32_C(0xe0000000)\n+\t#define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_SFT \\\n+\t\t29\n+\t/* Value is in Mb or MB (base 10). */\n+\t#define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_MEGA \\\n+\t\t(UINT32_C(0x0) << 29)\n+\t/* Value is in Kb or KB (base 10). */\n+\t#define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_KILO \\\n+\t\t(UINT32_C(0x2) << 29)\n+\t/* Value is in bits or bytes. */\n+\t#define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_BASE \\\n+\t\t(UINT32_C(0x4) << 29)\n+\t/* Value is in Gb or GB (base 10). */\n+\t#define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_GIGA \\\n+\t\t(UINT32_C(0x6) << 29)\n+\t/* Value is in 1/100th of a percentage of total bandwidth. */\n+\t#define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_PERCENT1_100 \\\n+\t\t(UINT32_C(0x1) << 29)\n+\t/* Invalid unit */\n+\t#define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_INVALID \\\n+\t\t(UINT32_C(0x7) << 29)\n+\t#define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_LAST \\\n+\t\tHWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_INVALID\n+} __attribute__((packed));\n+\n+/* hwrm_cfa_meter_profile_cfg_output (size:128b/16B) */\n+struct hwrm_cfa_meter_profile_cfg_output {\n+\t/* The specific error status for the command. */\n+\tuint16_t\terror_code;\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/* The sequence ID from the original command. */\n+\tuint16_t\tseq_id;\n+\t/* The length of the response data in number of bytes. */\n+\tuint16_t\tresp_len;\n+\tuint8_t\tunused_0[7];\n+\t/*\n+\t * This field is used in Output records to indicate that the output\n+\t * is completely written to RAM.  This field should be read as '1'\n+\t * to indicate that the output has been completely written.\n+\t * When writing a command completion or response to an internal processor,\n+\t * the order of writes has to be such that this field is written last.\n+\t */\n+\tuint8_t\tvalid;\n+} __attribute__((packed));\n+\n+/*********************************\n+ * hwrm_cfa_meter_instance_alloc *\n+ *********************************/\n+\n+\n+/* hwrm_cfa_meter_instance_alloc_input (size:192b/24B) */\n+struct hwrm_cfa_meter_instance_alloc_input {\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/*\n+\t * The completion ring to send the completion event on. This should\n+\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n+\t */\n+\tuint16_t\tcmpl_ring;\n+\t/*\n+\t * The sequence ID is used by the driver for tracking multiple\n+\t * commands. This ID is treated as opaque data by the firmware and\n+\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n+\t */\n+\tuint16_t\tseq_id;\n+\t/*\n+\t * The target ID of the command:\n+\t * * 0x0-0xFFF8 - The function ID\n+\t * * 0xFFF8-0xFFFE - Reserved for internal processors\n+\t * * 0xFFFF - HWRM\n+\t */\n+\tuint16_t\ttarget_id;\n+\t/*\n+\t * A physical address pointer pointing to a host buffer that the\n+\t * command's response data will be written. This can be either a host\n+\t * physical address (HPA) or a guest physical address (GPA) and must\n+\t * point to a physically contiguous block of memory.\n+\t */\n+\tuint64_t\tresp_addr;\n+\tuint8_t\tflags;\n+\t/*\n+\t * Enumeration denoting the RX, TX type of the resource.\n+\t * This enumeration is used for resources that are similar for both\n+\t * TX and RX paths of the chip.\n+\t */\n+\t#define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH \\\n+\t\tUINT32_C(0x1)\n+\t/* tx path */\n+\t#define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH_TX \\\n+\t\tUINT32_C(0x0)\n+\t/* rx path */\n+\t#define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH_RX \\\n+\t\tUINT32_C(0x1)\n+\t#define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH_LAST \\\n+\t\tHWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH_RX\n+\tuint8_t\tunused_0;\n+\t/* This value identifies a meter profile in CFA. */\n+\tuint16_t\tmeter_profile_id;\n+\t/*\n+\t * A value of 0xfff is considered invalid and implies the\n+\t * profile is not configured.\n+\t */\n+\t#define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_METER_PROFILE_ID_INVALID \\\n+\t\tUINT32_C(0xffff)\n+\t#define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_METER_PROFILE_ID_LAST \\\n+\t\tHWRM_CFA_METER_INSTANCE_ALLOC_INPUT_METER_PROFILE_ID_INVALID\n+\tuint8_t\tunused_1[4];\n+} __attribute__((packed));\n+\n+/* hwrm_cfa_meter_instance_alloc_output (size:128b/16B) */\n+struct hwrm_cfa_meter_instance_alloc_output {\n+\t/* The specific error status for the command. */\n+\tuint16_t\terror_code;\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/* The sequence ID from the original command. */\n+\tuint16_t\tseq_id;\n+\t/* The length of the response data in number of bytes. */\n+\tuint16_t\tresp_len;\n+\t/* This value identifies a meter instance in CFA. */\n+\tuint16_t\tmeter_instance_id;\n+\t/*\n+\t * A value of 0xfff is considered invalid and implies the\n+\t * instance is not configured.\n+\t */\n+\t#define HWRM_CFA_METER_INSTANCE_ALLOC_OUTPUT_METER_INSTANCE_ID_INVALID \\\n+\t\tUINT32_C(0xffff)\n+\t#define HWRM_CFA_METER_INSTANCE_ALLOC_OUTPUT_METER_INSTANCE_ID_LAST \\\n+\t\tHWRM_CFA_METER_INSTANCE_ALLOC_OUTPUT_METER_INSTANCE_ID_INVALID\n+\tuint8_t\tunused_0[5];\n+\t/*\n+\t * This field is used in Output records to indicate that the output\n+\t * is completely written to RAM.  This field should be read as '1'\n+\t * to indicate that the output has been completely written.\n+\t * When writing a command completion or response to an internal processor,\n+\t * the order of writes has to be such that this field is written last.\n+\t */\n+\tuint8_t\tvalid;\n+} __attribute__((packed));\n+\n+/********************************\n+ * hwrm_cfa_meter_instance_free *\n+ ********************************/\n+\n+\n+/* hwrm_cfa_meter_instance_free_input (size:192b/24B) */\n+struct hwrm_cfa_meter_instance_free_input {\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/*\n+\t * The completion ring to send the completion event on. This should\n+\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n+\t */\n+\tuint16_t\tcmpl_ring;\n+\t/*\n+\t * The sequence ID is used by the driver for tracking multiple\n+\t * commands. This ID is treated as opaque data by the firmware and\n+\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n+\t */\n+\tuint16_t\tseq_id;\n+\t/*\n+\t * The target ID of the command:\n+\t * * 0x0-0xFFF8 - The function ID\n+\t * * 0xFFF8-0xFFFE - Reserved for internal processors\n+\t * * 0xFFFF - HWRM\n+\t */\n+\tuint16_t\ttarget_id;\n+\t/*\n+\t * A physical address pointer pointing to a host buffer that the\n+\t * command's response data will be written. This can be either a host\n+\t * physical address (HPA) or a guest physical address (GPA) and must\n+\t * point to a physically contiguous block of memory.\n+\t */\n+\tuint64_t\tresp_addr;\n+\tuint8_t\tflags;\n+\t/*\n+\t * Enumeration denoting the RX, TX type of the resource.\n+\t * This enumeration is used for resources that are similar for both\n+\t * TX and RX paths of the chip.\n+\t */\n+\t#define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH     UINT32_C(0x1)\n+\t/* tx path */\n+\t#define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_TX \\\n+\t\tUINT32_C(0x0)\n+\t/* rx path */\n+\t#define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_RX \\\n+\t\tUINT32_C(0x1)\n+\t#define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_LAST \\\n+\t\tHWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_RX\n+\tuint8_t\tunused_0;\n+\t/* This value identifies a meter instance in CFA. */\n+\tuint16_t\tmeter_instance_id;\n+\t/*\n+\t * A value of 0xfff is considered invalid and implies the\n+\t * instance is not configured.\n+\t */\n+\t#define HWRM_CFA_METER_INSTANCE_FREE_INPUT_METER_INSTANCE_ID_INVALID \\\n+\t\tUINT32_C(0xffff)\n+\t#define HWRM_CFA_METER_INSTANCE_FREE_INPUT_METER_INSTANCE_ID_LAST \\\n+\t\tHWRM_CFA_METER_INSTANCE_FREE_INPUT_METER_INSTANCE_ID_INVALID\n+\tuint8_t\tunused_1[4];\n+} __attribute__((packed));\n+\n+/* hwrm_cfa_meter_instance_free_output (size:128b/16B) */\n+struct hwrm_cfa_meter_instance_free_output {\n+\t/* The specific error status for the command. */\n+\tuint16_t\terror_code;\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/* The sequence ID from the original command. */\n+\tuint16_t\tseq_id;\n+\t/* The length of the response data in number of bytes. */\n+\tuint16_t\tresp_len;\n+\tuint8_t\tunused_0[7];\n+\t/*\n+\t * This field is used in Output records to indicate that the output\n+\t * is completely written to RAM.  This field should be read as '1'\n+\t * to indicate that the output has been completely written.\n+\t * When writing a command completion or response to an internal processor,\n+\t * the order of writes has to be such that this field is written last.\n+\t */\n+\tuint8_t\tvalid;\n+} __attribute__((packed));\n+\n+/*******************************\n+ * hwrm_cfa_decap_filter_alloc *\n+ *******************************/\n+\n+\n+/* hwrm_cfa_decap_filter_alloc_input (size:832b/104B) */\n+struct hwrm_cfa_decap_filter_alloc_input {\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/*\n+\t * The completion ring to send the completion event on. This should\n+\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n+\t */\n+\tuint16_t\tcmpl_ring;\n+\t/*\n+\t * The sequence ID is used by the driver for tracking multiple\n+\t * commands. This ID is treated as opaque data by the firmware and\n+\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n+\t */\n+\tuint16_t\tseq_id;\n+\t/*\n+\t * The target ID of the command:\n+\t * * 0x0-0xFFF8 - The function ID\n+\t * * 0xFFF8-0xFFFE - Reserved for internal processors\n+\t * * 0xFFFF - HWRM\n+\t */\n+\tuint16_t\ttarget_id;\n+\t/*\n+\t * A physical address pointer pointing to a host buffer that the\n+\t * command's response data will be written. This can be either a host\n+\t * physical address (HPA) or a guest physical address (GPA) and must\n+\t * point to a physically contiguous block of memory.\n+\t */\n+\tuint64_t\tresp_addr;\n+\tuint32_t\tflags;\n+\t/* ovs_tunnel is 1 b */\n+\t#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_FLAGS_OVS_TUNNEL \\\n+\t\tUINT32_C(0x1)\n+\tuint32_t\tenables;\n+\t/*\n+\t * This bit must be '1' for the tunnel_type field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \\\n+\t\tUINT32_C(0x1)\n+\t/*\n+\t * This bit must be '1' for the tunnel_id field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_ID \\\n+\t\tUINT32_C(0x2)\n+\t/*\n+\t * This bit must be '1' for the src_macaddr field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR \\\n+\t\tUINT32_C(0x4)\n+\t/*\n+\t * This bit must be '1' for the dst_macaddr field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_MACADDR \\\n+\t\tUINT32_C(0x8)\n+\t/*\n \t * This bit must be '1' for the ovlan_vid field to be\n \t * configured.\n \t */\n-\t#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_OVLAN_VID \\\n-\t\tUINT32_C(0x10)\n+\t#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_OVLAN_VID \\\n+\t\tUINT32_C(0x10)\n+\t/*\n+\t * This bit must be '1' for the ivlan_vid field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_IVLAN_VID \\\n+\t\tUINT32_C(0x20)\n+\t/*\n+\t * This bit must be '1' for the t_ovlan_vid field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_T_OVLAN_VID \\\n+\t\tUINT32_C(0x40)\n+\t/*\n+\t * This bit must be '1' for the t_ivlan_vid field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_T_IVLAN_VID \\\n+\t\tUINT32_C(0x80)\n+\t/*\n+\t * This bit must be '1' for the ethertype field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE \\\n+\t\tUINT32_C(0x100)\n+\t/*\n+\t * This bit must be '1' for the src_ipaddr field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR \\\n+\t\tUINT32_C(0x200)\n+\t/*\n+\t * This bit must be '1' for the dst_ipaddr field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR \\\n+\t\tUINT32_C(0x400)\n+\t/*\n+\t * This bit must be '1' for the ipaddr_type field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE \\\n+\t\tUINT32_C(0x800)\n+\t/*\n+\t * This bit must be '1' for the ip_protocol field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL \\\n+\t\tUINT32_C(0x1000)\n+\t/*\n+\t * This bit must be '1' for the src_port field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT \\\n+\t\tUINT32_C(0x2000)\n+\t/*\n+\t * This bit must be '1' for the dst_port field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_PORT \\\n+\t\tUINT32_C(0x4000)\n+\t/*\n+\t * This bit must be '1' for the dst_id field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_ID \\\n+\t\tUINT32_C(0x8000)\n+\t/*\n+\t * This bit must be '1' for the mirror_vnic_id field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID \\\n+\t\tUINT32_C(0x10000)\n+\t/*\n+\t * Tunnel identifier.\n+\t * Virtual Network Identifier (VNI). Only valid with\n+\t * tunnel_types VXLAN, NVGRE, and Geneve.\n+\t * Only lower 24-bits of VNI field are used\n+\t * in setting up the filter.\n+\t */\n+\tuint32_t\ttunnel_id;\n+\t/* Tunnel Type. */\n+\tuint8_t\ttunnel_type;\n+\t/* Non-tunnel */\n+\t#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \\\n+\t\tUINT32_C(0x0)\n+\t/* Virtual eXtensible Local Area Network (VXLAN) */\n+\t#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \\\n+\t\tUINT32_C(0x1)\n+\t/* Network Virtualization Generic Routing Encapsulation (NVGRE) */\n+\t#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \\\n+\t\tUINT32_C(0x2)\n+\t/* Generic Routing Encapsulation (GRE) inside Ethernet payload */\n+\t#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \\\n+\t\tUINT32_C(0x3)\n+\t/* IP in IP */\n+\t#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPIP \\\n+\t\tUINT32_C(0x4)\n+\t/* Generic Network Virtualization Encapsulation (Geneve) */\n+\t#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \\\n+\t\tUINT32_C(0x5)\n+\t/* Multi-Protocol Lable Switching (MPLS) */\n+\t#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS \\\n+\t\tUINT32_C(0x6)\n+\t/* Stateless Transport Tunnel (STT) */\n+\t#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_STT \\\n+\t\tUINT32_C(0x7)\n+\t/* Generic Routing Encapsulation (GRE) inside IP datagram payload */\n+\t#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \\\n+\t\tUINT32_C(0x8)\n+\t/* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */\n+\t#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \\\n+\t\tUINT32_C(0x9)\n+\t/* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */\n+\t#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \\\n+\t\tUINT32_C(0xa)\n+\t/* Use fixed layer 2 ether type of 0xFFFF */\n+\t#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \\\n+\t\tUINT32_C(0xb)\n+\t/* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */\n+\t#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \\\n+\t\tUINT32_C(0xc)\n+\t/* Any tunneled traffic */\n+\t#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \\\n+\t\tUINT32_C(0xff)\n+\t#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_LAST \\\n+\t\tHWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL\n+\tuint8_t\tunused_0;\n+\tuint16_t\tunused_1;\n+\t/*\n+\t * This value indicates the source MAC address in\n+\t * the Ethernet header.\n+\t */\n+\tuint8_t\tsrc_macaddr[6];\n+\tuint8_t\tunused_2[2];\n \t/*\n-\t * This bit must be '1' for the ivlan_vid field to be\n-\t * configured.\n+\t * This value indicates the destination MAC address in\n+\t * the Ethernet header.\n \t */\n-\t#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_IVLAN_VID \\\n-\t\tUINT32_C(0x20)\n+\tuint8_t\tdst_macaddr[6];\n+\t/*\n+\t * This value indicates the VLAN ID of the outer VLAN tag\n+\t * in the Ethernet header.\n+\t */\n+\tuint16_t\tovlan_vid;\n+\t/*\n+\t * This value indicates the VLAN ID of the inner VLAN tag\n+\t * in the Ethernet header.\n+\t */\n+\tuint16_t\tivlan_vid;\n+\t/*\n+\t * This value indicates the VLAN ID of the outer VLAN tag\n+\t * in the tunnel Ethernet header.\n+\t */\n+\tuint16_t\tt_ovlan_vid;\n+\t/*\n+\t * This value indicates the VLAN ID of the inner VLAN tag\n+\t * in the tunnel Ethernet header.\n+\t */\n+\tuint16_t\tt_ivlan_vid;\n+\t/* This value indicates the ethertype in the Ethernet header. */\n+\tuint16_t\tethertype;\n+\t/*\n+\t * This value indicates the type of IP address.\n+\t * 4 - IPv4\n+\t * 6 - IPv6\n+\t * All others are invalid.\n+\t */\n+\tuint8_t\tip_addr_type;\n+\t/* invalid */\n+\t#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_UNKNOWN \\\n+\t\tUINT32_C(0x0)\n+\t/* IPv4 */\n+\t#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV4 \\\n+\t\tUINT32_C(0x4)\n+\t/* IPv6 */\n+\t#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6 \\\n+\t\tUINT32_C(0x6)\n+\t#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_LAST \\\n+\t\tHWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6\n+\t/*\n+\t * The value of protocol filed in IP header.\n+\t * Applies to UDP and TCP traffic.\n+\t * 6 - TCP\n+\t * 17 - UDP\n+\t */\n+\tuint8_t\tip_protocol;\n+\t/* invalid */\n+\t#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_UNKNOWN \\\n+\t\tUINT32_C(0x0)\n+\t/* TCP */\n+\t#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_TCP \\\n+\t\tUINT32_C(0x6)\n+\t/* UDP */\n+\t#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP \\\n+\t\tUINT32_C(0x11)\n+\t#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_LAST \\\n+\t\tHWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP\n+\tuint16_t\tunused_3;\n+\tuint32_t\tunused_4;\n+\t/*\n+\t * The value of source IP address to be used in filtering.\n+\t * For IPv4, first four bytes represent the IP address.\n+\t */\n+\tuint32_t\tsrc_ipaddr[4];\n+\t/*\n+\t * The value of destination IP address to be used in filtering.\n+\t * For IPv4, first four bytes represent the IP address.\n+\t */\n+\tuint32_t\tdst_ipaddr[4];\n+\t/*\n+\t * The value of source port to be used in filtering.\n+\t * Applies to UDP and TCP traffic.\n+\t */\n+\tuint16_t\tsrc_port;\n+\t/*\n+\t * The value of destination port to be used in filtering.\n+\t * Applies to UDP and TCP traffic.\n+\t */\n+\tuint16_t\tdst_port;\n+\t/*\n+\t * If set, this value shall represent the\n+\t * Logical VNIC ID of the destination VNIC for the RX\n+\t * path.\n+\t */\n+\tuint16_t\tdst_id;\n+\t/*\n+\t * If set, this value shall represent the L2 context that matches the L2\n+\t * information of the decap filter.\n+\t */\n+\tuint16_t\tl2_ctxt_ref_id;\n+} __attribute__((packed));\n+\n+/* hwrm_cfa_decap_filter_alloc_output (size:128b/16B) */\n+struct hwrm_cfa_decap_filter_alloc_output {\n+\t/* The specific error status for the command. */\n+\tuint16_t\terror_code;\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/* The sequence ID from the original command. */\n+\tuint16_t\tseq_id;\n+\t/* The length of the response data in number of bytes. */\n+\tuint16_t\tresp_len;\n+\t/* This value is an opaque id into CFA data structures. */\n+\tuint32_t\tdecap_filter_id;\n+\tuint8_t\tunused_0[3];\n+\t/*\n+\t * This field is used in Output records to indicate that the output\n+\t * is completely written to RAM.  This field should be read as '1'\n+\t * to indicate that the output has been completely written.\n+\t * When writing a command completion or response to an internal processor,\n+\t * the order of writes has to be such that this field is written last.\n+\t */\n+\tuint8_t\tvalid;\n+} __attribute__((packed));\n+\n+/******************************\n+ * hwrm_cfa_decap_filter_free *\n+ ******************************/\n+\n+\n+/* hwrm_cfa_decap_filter_free_input (size:192b/24B) */\n+struct hwrm_cfa_decap_filter_free_input {\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/*\n+\t * The completion ring to send the completion event on. This should\n+\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n+\t */\n+\tuint16_t\tcmpl_ring;\n+\t/*\n+\t * The sequence ID is used by the driver for tracking multiple\n+\t * commands. This ID is treated as opaque data by the firmware and\n+\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n+\t */\n+\tuint16_t\tseq_id;\n+\t/*\n+\t * The target ID of the command:\n+\t * * 0x0-0xFFF8 - The function ID\n+\t * * 0xFFF8-0xFFFE - Reserved for internal processors\n+\t * * 0xFFFF - HWRM\n+\t */\n+\tuint16_t\ttarget_id;\n+\t/*\n+\t * A physical address pointer pointing to a host buffer that the\n+\t * command's response data will be written. This can be either a host\n+\t * physical address (HPA) or a guest physical address (GPA) and must\n+\t * point to a physically contiguous block of memory.\n+\t */\n+\tuint64_t\tresp_addr;\n+\t/* This value is an opaque id into CFA data structures. */\n+\tuint32_t\tdecap_filter_id;\n+\tuint8_t\tunused_0[4];\n+} __attribute__((packed));\n+\n+/* hwrm_cfa_decap_filter_free_output (size:128b/16B) */\n+struct hwrm_cfa_decap_filter_free_output {\n+\t/* The specific error status for the command. */\n+\tuint16_t\terror_code;\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/* The sequence ID from the original command. */\n+\tuint16_t\tseq_id;\n+\t/* The length of the response data in number of bytes. */\n+\tuint16_t\tresp_len;\n+\tuint8_t\tunused_0[7];\n+\t/*\n+\t * This field is used in Output records to indicate that the output\n+\t * is completely written to RAM.  This field should be read as '1'\n+\t * to indicate that the output has been completely written.\n+\t * When writing a command completion or response to an internal processor,\n+\t * the order of writes has to be such that this field is written last.\n+\t */\n+\tuint8_t\tvalid;\n+} __attribute__((packed));\n+\n+/***********************\n+ * hwrm_cfa_flow_alloc *\n+ ***********************/\n+\n+\n+/* hwrm_cfa_flow_alloc_input (size:1024b/128B) */\n+struct hwrm_cfa_flow_alloc_input {\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/*\n+\t * The completion ring to send the completion event on. This should\n+\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n+\t */\n+\tuint16_t\tcmpl_ring;\n+\t/*\n+\t * The sequence ID is used by the driver for tracking multiple\n+\t * commands. This ID is treated as opaque data by the firmware and\n+\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n+\t */\n+\tuint16_t\tseq_id;\n+\t/*\n+\t * The target ID of the command:\n+\t * * 0x0-0xFFF8 - The function ID\n+\t * * 0xFFF8-0xFFFE - Reserved for internal processors\n+\t * * 0xFFFF - HWRM\n+\t */\n+\tuint16_t\ttarget_id;\n+\t/*\n+\t * A physical address pointer pointing to a host buffer that the\n+\t * command's response data will be written. This can be either a host\n+\t * physical address (HPA) or a guest physical address (GPA) and must\n+\t * point to a physically contiguous block of memory.\n+\t */\n+\tuint64_t\tresp_addr;\n+\tuint16_t\tflags;\n+\t/* tunnel is 1 b */\n+\t#define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_TUNNEL \\\n+\t\tUINT32_C(0x1)\n+\t/* num_vlan is 2 b */\n+\t#define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_MASK \\\n+\t\tUINT32_C(0x6)\n+\t#define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_SFT           1\n+\t/* no tags */\n+\t#define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_NONE \\\n+\t\t(UINT32_C(0x0) << 1)\n+\t/* 1 tag */\n+\t#define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_ONE \\\n+\t\t(UINT32_C(0x1) << 1)\n+\t/* 2 tags */\n+\t#define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_TWO \\\n+\t\t(UINT32_C(0x2) << 1)\n+\t#define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_LAST \\\n+\t\tHWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_TWO\n+\t/* Enumeration denoting the Flow Type. */\n+\t#define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_MASK \\\n+\t\tUINT32_C(0x38)\n+\t#define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_SFT           3\n+\t/* L2 flow */\n+\t#define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_L2 \\\n+\t\t(UINT32_C(0x0) << 3)\n+\t/* IPV4 flow */\n+\t#define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_IPV4 \\\n+\t\t(UINT32_C(0x1) << 3)\n+\t/* IPV6 flow */\n+\t#define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_IPV6 \\\n+\t\t(UINT32_C(0x2) << 3)\n+\t#define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_LAST \\\n+\t\tHWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_IPV6\n \t/*\n-\t * This bit must be '1' for the t_ovlan_vid field to be\n-\t * configured.\n+\t * when set to 1, indicates TX flow offload for function specified in src_fid and\n+\t * the dst_fid should be set to invalid value. To indicate a VM to VM flow, both\n+\t * of the path_tx and path_rx flags need to be set. For virtio vSwitch offload\n+\t * case, the src_fid and dst_fid is set to the same fid value. For the SRIOV\n+\t * vSwitch offload case, the src_fid and dst_fid must be set to the same VF FID\n+\t * belong to the children VFs of the same PF to indicate VM to VM flow.\n \t */\n-\t#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_T_OVLAN_VID \\\n+\t#define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_PATH_TX \\\n \t\tUINT32_C(0x40)\n \t/*\n-\t * This bit must be '1' for the t_ivlan_vid field to be\n-\t * configured.\n+\t * when set to 1, indicates RX flow offload for function specified in dst_fid and\n+\t * the src_fid should be set to invalid value.\n \t */\n-\t#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_T_IVLAN_VID \\\n+\t#define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_PATH_RX \\\n \t\tUINT32_C(0x80)\n \t/*\n-\t * This bit must be '1' for the ethertype field to be\n-\t * configured.\n+\t * Set to 1 to indicate matching of VXLAN VNI from the custom vxlan header is\n+\t * required and the VXLAN VNI value is stored in the first 24 bits of the dmac field.\n+\t * This flag is only valid when the flow direction is RX.\n \t */\n-\t#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE \\\n+\t#define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_MATCH_VXLAN_IP_VNI \\\n \t\tUINT32_C(0x100)\n \t/*\n-\t * This bit must be '1' for the src_ipaddr field to be\n-\t * configured.\n+\t * Tx Flow: vf fid.\n+\t * Rx Flow: pf fid.\n \t */\n-\t#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR \\\n+\tuint16_t\tsrc_fid;\n+\t/* Tunnel handle valid when tunnel flag is set. */\n+\tuint32_t\ttunnel_handle;\n+\tuint16_t\taction_flags;\n+\t/*\n+\t * Setting of this flag indicates drop action. If this flag is not set,\n+\t * then it should be considered accept action.\n+\t */\n+\t#define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_FWD \\\n+\t\tUINT32_C(0x1)\n+\t/* recycle is 1 b */\n+\t#define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_RECYCLE \\\n+\t\tUINT32_C(0x2)\n+\t/*\n+\t * Setting of this flag indicates drop action. If this flag is not set,\n+\t * then it should be considered accept action.\n+\t */\n+\t#define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_DROP \\\n+\t\tUINT32_C(0x4)\n+\t/* meter is 1 b */\n+\t#define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_METER \\\n+\t\tUINT32_C(0x8)\n+\t/* tunnel is 1 b */\n+\t#define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_TUNNEL \\\n+\t\tUINT32_C(0x10)\n+\t/* nat_src is 1 b */\n+\t#define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NAT_SRC \\\n+\t\tUINT32_C(0x20)\n+\t/* nat_dest is 1 b */\n+\t#define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NAT_DEST \\\n+\t\tUINT32_C(0x40)\n+\t/* nat_ipv4_address is 1 b */\n+\t#define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NAT_IPV4_ADDRESS \\\n+\t\tUINT32_C(0x80)\n+\t/* l2_header_rewrite is 1 b */\n+\t#define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_L2_HEADER_REWRITE \\\n+\t\tUINT32_C(0x100)\n+\t/* ttl_decrement is 1 b */\n+\t#define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_TTL_DECREMENT \\\n \t\tUINT32_C(0x200)\n \t/*\n-\t * This bit must be '1' for the dst_ipaddr field to be\n-\t * configured.\n+\t * If set to 1 and flow direction is TX, it indicates decap of L2 header\n+\t * and encap of tunnel header. If set to 1 and flow direction is RX, it\n+\t * indicates decap of tunnel header and encap L2 header. The type of tunnel\n+\t * is specified in the tunnel_type field.\n \t */\n-\t#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR \\\n+\t#define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_TUNNEL_IP \\\n \t\tUINT32_C(0x400)\n+\t/* If set to 1, flow aging is enabled for this flow. */\n+\t#define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_FLOW_AGING_ENABLED \\\n+\t\tUINT32_C(0x800)\n \t/*\n-\t * This bit must be '1' for the ipaddr_type field to be\n-\t * configured.\n+\t * Tx Flow: pf or vf fid.\n+\t * Rx Flow: vf fid.\n \t */\n-\t#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE \\\n-\t\tUINT32_C(0x800)\n+\tuint16_t\tdst_fid;\n+\t/* VLAN tpid, valid when push_vlan flag is set. */\n+\tuint16_t\tl2_rewrite_vlan_tpid;\n+\t/* VLAN tci, valid when push_vlan flag is set. */\n+\tuint16_t\tl2_rewrite_vlan_tci;\n+\t/* Meter id, valid when meter flag is set. */\n+\tuint16_t\tact_meter_id;\n+\t/* Flow with the same l2 context tcam key. */\n+\tuint16_t\tref_flow_handle;\n+\t/* This value sets the match value for the ethertype. */\n+\tuint16_t\tethertype;\n+\t/* valid when num tags is 1 or 2. */\n+\tuint16_t\touter_vlan_tci;\n+\t/* This value sets the match value for the Destination MAC address. */\n+\tuint16_t\tdmac[3];\n+\t/* valid when num tags is 2. */\n+\tuint16_t\tinner_vlan_tci;\n+\t/* This value sets the match value for the Source MAC address. */\n+\tuint16_t\tsmac[3];\n+\t/* The bit length of destination IP address mask. */\n+\tuint8_t\tip_dst_mask_len;\n+\t/* The bit length of source IP address mask. */\n+\tuint8_t\tip_src_mask_len;\n+\t/* The value of destination IPv4/IPv6 address. */\n+\tuint32_t\tip_dst[4];\n+\t/* The source IPv4/IPv6 address. */\n+\tuint32_t\tip_src[4];\n \t/*\n-\t * This bit must be '1' for the ip_protocol field to be\n-\t * configured.\n+\t * The value of source port.\n+\t * Applies to UDP and TCP traffic.\n \t */\n-\t#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL \\\n-\t\tUINT32_C(0x1000)\n+\tuint16_t\tl4_src_port;\n \t/*\n-\t * This bit must be '1' for the src_port field to be\n-\t * configured.\n+\t * The value of source port mask.\n+\t * Applies to UDP and TCP traffic.\n \t */\n-\t#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT \\\n-\t\tUINT32_C(0x2000)\n+\tuint16_t\tl4_src_port_mask;\n \t/*\n-\t * This bit must be '1' for the dst_port field to be\n-\t * configured.\n+\t * The value of destination port.\n+\t * Applies to UDP and TCP traffic.\n \t */\n-\t#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_PORT \\\n-\t\tUINT32_C(0x4000)\n+\tuint16_t\tl4_dst_port;\n \t/*\n-\t * This bit must be '1' for the dst_id field to be\n-\t * configured.\n+\t * The value of destination port mask.\n+\t * Applies to UDP and TCP traffic.\n \t */\n-\t#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_ID \\\n-\t\tUINT32_C(0x8000)\n+\tuint16_t\tl4_dst_port_mask;\n \t/*\n-\t * This bit must be '1' for the mirror_vnic_id field to be\n-\t * configured.\n+\t * NAT IPv4/6 address based on address type flag.\n+\t * 0 values are ignored.\n \t */\n-\t#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID \\\n-\t\tUINT32_C(0x10000)\n+\tuint32_t\tnat_ip_address[4];\n+\t/* L2 header re-write Destination MAC address. */\n+\tuint16_t\tl2_rewrite_dmac[3];\n \t/*\n-\t * Tunnel identifier.\n-\t * Virtual Network Identifier (VNI). Only valid with\n-\t * tunnel_types VXLAN, NVGRE, and Geneve.\n-\t * Only lower 24-bits of VNI field are used\n-\t * in setting up the filter.\n+\t * The NAT source/destination port based on direction flag.\n+\t * Applies to UDP and TCP traffic.\n+\t * 0 values are ignored.\n \t */\n-\tuint32_t\ttunnel_id;\n+\tuint16_t\tnat_port;\n+\t/* L2 header re-write Source MAC address. */\n+\tuint16_t\tl2_rewrite_smac[3];\n+\t/* The value of ip protocol. */\n+\tuint8_t\tip_proto;\n \t/* Tunnel Type. */\n \tuint8_t\ttunnel_type;\n \t/* Non-tunnel */\n-\t#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \\\n+\t#define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \\\n \t\tUINT32_C(0x0)\n \t/* Virtual eXtensible Local Area Network (VXLAN) */\n-\t#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \\\n+\t#define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \\\n \t\tUINT32_C(0x1)\n \t/* Network Virtualization Generic Routing Encapsulation (NVGRE) */\n-\t#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \\\n+\t#define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \\\n \t\tUINT32_C(0x2)\n \t/* Generic Routing Encapsulation (GRE) inside Ethernet payload */\n-\t#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \\\n+\t#define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \\\n \t\tUINT32_C(0x3)\n \t/* IP in IP */\n-\t#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPIP \\\n+\t#define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPIP \\\n \t\tUINT32_C(0x4)\n \t/* Generic Network Virtualization Encapsulation (Geneve) */\n-\t#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \\\n+\t#define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \\\n \t\tUINT32_C(0x5)\n \t/* Multi-Protocol Lable Switching (MPLS) */\n-\t#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS \\\n+\t#define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_MPLS \\\n \t\tUINT32_C(0x6)\n \t/* Stateless Transport Tunnel (STT) */\n-\t#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_STT \\\n+\t#define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_STT \\\n \t\tUINT32_C(0x7)\n \t/* Generic Routing Encapsulation (GRE) inside IP datagram payload */\n-\t#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \\\n+\t#define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \\\n \t\tUINT32_C(0x8)\n \t/* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */\n-\t#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \\\n+\t#define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \\\n \t\tUINT32_C(0x9)\n+\t/* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */\n+\t#define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \\\n+\t\tUINT32_C(0xa)\n+\t/* Use fixed layer 2 ether type of 0xFFFF */\n+\t#define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \\\n+\t\tUINT32_C(0xb)\n+\t/* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */\n+\t#define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \\\n+\t\tUINT32_C(0xc)\n \t/* Any tunneled traffic */\n-\t#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \\\n+\t#define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \\\n \t\tUINT32_C(0xff)\n-\t#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_LAST \\\n-\t\tHWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL\n-\tuint8_t\tunused_0;\n-\tuint16_t\tunused_1;\n+\t#define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_LAST \\\n+\t\tHWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL\n+} __attribute__((packed));\n+\n+/* hwrm_cfa_flow_alloc_output (size:256b/32B) */\n+struct hwrm_cfa_flow_alloc_output {\n+\t/* The specific error status for the command. */\n+\tuint16_t\terror_code;\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/* The sequence ID from the original command. */\n+\tuint16_t\tseq_id;\n+\t/* The length of the response data in number of bytes. */\n+\tuint16_t\tresp_len;\n+\t/* Flow record index. */\n+\tuint16_t\tflow_handle;\n+\tuint8_t\tunused_0[2];\n \t/*\n-\t * This value indicates the source MAC address in\n-\t * the Ethernet header.\n+\t * This is the ID of the flow associated with this\n+\t * filter.\n+\t * This value shall be used to match and associate the\n+\t * flow identifier returned in completion records.\n+\t * A value of 0xFFFFFFFF shall indicate no flow id.\n+\t */\n+\tuint32_t\tflow_id;\n+\t/* This value identifies a set of CFA data structures used for a flow. */\n+\tuint64_t\text_flow_handle;\n+\tuint8_t\tunused_1[7];\n+\t/*\n+\t * This field is used in Output records to indicate that the output\n+\t * is completely written to RAM.  This field should be read as '1'\n+\t * to indicate that the output has been completely written.\n+\t * When writing a command completion or response to an internal processor,\n+\t * the order of writes has to be such that this field is written last.\n+\t */\n+\tuint8_t\tvalid;\n+} __attribute__((packed));\n+\n+/**********************\n+ * hwrm_cfa_flow_free *\n+ **********************/\n+\n+\n+/* hwrm_cfa_flow_free_input (size:256b/32B) */\n+struct hwrm_cfa_flow_free_input {\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/*\n+\t * The completion ring to send the completion event on. This should\n+\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n \t */\n-\tuint8_t\tsrc_macaddr[6];\n-\tuint8_t\tunused_2[2];\n+\tuint16_t\tcmpl_ring;\n \t/*\n-\t * This value indicates the destination MAC address in\n-\t * the Ethernet header.\n+\t * The sequence ID is used by the driver for tracking multiple\n+\t * commands. This ID is treated as opaque data by the firmware and\n+\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n \t */\n-\tuint8_t\tdst_macaddr[6];\n+\tuint16_t\tseq_id;\n \t/*\n-\t * This value indicates the VLAN ID of the outer VLAN tag\n-\t * in the Ethernet header.\n+\t * The target ID of the command:\n+\t * * 0x0-0xFFF8 - The function ID\n+\t * * 0xFFF8-0xFFFE - Reserved for internal processors\n+\t * * 0xFFFF - HWRM\n \t */\n-\tuint16_t\tovlan_vid;\n+\tuint16_t\ttarget_id;\n \t/*\n-\t * This value indicates the VLAN ID of the inner VLAN tag\n-\t * in the Ethernet header.\n+\t * A physical address pointer pointing to a host buffer that the\n+\t * command's response data will be written. This can be either a host\n+\t * physical address (HPA) or a guest physical address (GPA) and must\n+\t * point to a physically contiguous block of memory.\n \t */\n-\tuint16_t\tivlan_vid;\n+\tuint64_t\tresp_addr;\n+\t/* Flow record index. */\n+\tuint16_t\tflow_handle;\n+\tuint8_t\tunused_0[6];\n+\t/* This value identifies a set of CFA data structures used for a flow. */\n+\tuint64_t\text_flow_handle;\n+} __attribute__((packed));\n+\n+/* hwrm_cfa_flow_free_output (size:256b/32B) */\n+struct hwrm_cfa_flow_free_output {\n+\t/* The specific error status for the command. */\n+\tuint16_t\terror_code;\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/* The sequence ID from the original command. */\n+\tuint16_t\tseq_id;\n+\t/* The length of the response data in number of bytes. */\n+\tuint16_t\tresp_len;\n+\t/* packet is 64 b */\n+\tuint64_t\tpacket;\n+\t/* byte is 64 b */\n+\tuint64_t\tbyte;\n+\tuint8_t\tunused_0[7];\n \t/*\n-\t * This value indicates the VLAN ID of the outer VLAN tag\n-\t * in the tunnel Ethernet header.\n+\t * This field is used in Output records to indicate that the output\n+\t * is completely written to RAM.  This field should be read as '1'\n+\t * to indicate that the output has been completely written.\n+\t * When writing a command completion or response to an internal processor,\n+\t * the order of writes has to be such that this field is written last.\n \t */\n-\tuint16_t\tt_ovlan_vid;\n+\tuint8_t\tvalid;\n+} __attribute__((packed));\n+\n+/**********************\n+ * hwrm_cfa_flow_info *\n+ **********************/\n+\n+\n+/* hwrm_cfa_flow_info_input (size:256b/32B) */\n+struct hwrm_cfa_flow_info_input {\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n \t/*\n-\t * This value indicates the VLAN ID of the inner VLAN tag\n-\t * in the tunnel Ethernet header.\n+\t * The completion ring to send the completion event on. This should\n+\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n \t */\n-\tuint16_t\tt_ivlan_vid;\n-\t/* This value indicates the ethertype in the Ethernet header. */\n-\tuint16_t\tethertype;\n+\tuint16_t\tcmpl_ring;\n \t/*\n-\t * This value indicates the type of IP address.\n-\t * 4 - IPv4\n-\t * 6 - IPv6\n-\t * All others are invalid.\n+\t * The sequence ID is used by the driver for tracking multiple\n+\t * commands. This ID is treated as opaque data by the firmware and\n+\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n \t */\n-\tuint8_t\tip_addr_type;\n-\t/* invalid */\n-\t#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_UNKNOWN \\\n-\t\tUINT32_C(0x0)\n-\t/* IPv4 */\n-\t#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV4 \\\n-\t\tUINT32_C(0x4)\n-\t/* IPv6 */\n-\t#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6 \\\n-\t\tUINT32_C(0x6)\n-\t#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_LAST \\\n-\t\tHWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6\n+\tuint16_t\tseq_id;\n \t/*\n-\t * The value of protocol filed in IP header.\n-\t * Applies to UDP and TCP traffic.\n-\t * 6 - TCP\n-\t * 17 - UDP\n+\t * The target ID of the command:\n+\t * * 0x0-0xFFF8 - The function ID\n+\t * * 0xFFF8-0xFFFE - Reserved for internal processors\n+\t * * 0xFFFF - HWRM\n \t */\n-\tuint8_t\tip_protocol;\n-\t/* invalid */\n-\t#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_UNKNOWN \\\n-\t\tUINT32_C(0x0)\n-\t/* TCP */\n-\t#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_TCP \\\n-\t\tUINT32_C(0x6)\n-\t/* UDP */\n-\t#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP \\\n-\t\tUINT32_C(0x11)\n-\t#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_LAST \\\n-\t\tHWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP\n-\tuint16_t\tunused_3;\n-\tuint32_t\tunused_4;\n+\tuint16_t\ttarget_id;\n \t/*\n-\t * The value of source IP address to be used in filtering.\n-\t * For IPv4, first four bytes represent the IP address.\n+\t * A physical address pointer pointing to a host buffer that the\n+\t * command's response data will be written. This can be either a host\n+\t * physical address (HPA) or a guest physical address (GPA) and must\n+\t * point to a physically contiguous block of memory.\n \t */\n-\tuint32_t\tsrc_ipaddr[4];\n+\tuint64_t\tresp_addr;\n+\t/* Flow record index. */\n+\tuint16_t\tflow_handle;\n+\t/* Max flow handle */\n+\t#define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_MAX_MASK \\\n+\t\tUINT32_C(0xfff)\n+\t#define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_MAX_SFT        0\n+\t/* CNP flow handle */\n+\t#define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_CNP_CNT \\\n+\t\tUINT32_C(0x1000)\n+\t/* RoCEv1 flow handle */\n+\t#define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_ROCEV1_CNT \\\n+\t\tUINT32_C(0x2000)\n+\t/* RoCEv2 flow handle */\n+\t#define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_ROCEV2_CNT \\\n+\t\tUINT32_C(0x4000)\n+\t/* Direction rx = 1 */\n+\t#define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_DIR_RX \\\n+\t\tUINT32_C(0x8000)\n+\tuint8_t\tunused_0[6];\n+\t/* This value identifies a set of CFA data structures used for a flow. */\n+\tuint64_t\text_flow_handle;\n+} __attribute__((packed));\n+\n+/* hwrm_cfa_flow_info_output (size:448b/56B) */\n+struct hwrm_cfa_flow_info_output {\n+\t/* The specific error status for the command. */\n+\tuint16_t\terror_code;\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/* The sequence ID from the original command. */\n+\tuint16_t\tseq_id;\n+\t/* The length of the response data in number of bytes. */\n+\tuint16_t\tresp_len;\n+\t/* flags is 8 b */\n+\tuint8_t\tflags;\n+\t/* profile is 8 b */\n+\tuint8_t\tprofile;\n+\t/* src_fid is 16 b */\n+\tuint16_t\tsrc_fid;\n+\t/* dst_fid is 16 b */\n+\tuint16_t\tdst_fid;\n+\t/* l2_ctxt_id is 16 b */\n+\tuint16_t\tl2_ctxt_id;\n+\t/* em_info is 64 b */\n+\tuint64_t\tem_info;\n+\t/* tcam_info is 64 b */\n+\tuint64_t\ttcam_info;\n+\t/* vfp_tcam_info is 64 b */\n+\tuint64_t\tvfp_tcam_info;\n+\t/* ar_id is 16 b */\n+\tuint16_t\tar_id;\n+\t/* flow_handle is 16 b */\n+\tuint16_t\tflow_handle;\n+\t/* tunnel_handle is 32 b */\n+\tuint32_t\ttunnel_handle;\n+\t/* The flow aging timer for the flow, the unit is 100 milliseconds */\n+\tuint16_t\tflow_timer;\n+\tuint8_t\tunused_0[5];\n \t/*\n-\t * The value of destination IP address to be used in filtering.\n-\t * For IPv4, first four bytes represent the IP address.\n+\t * This field is used in Output records to indicate that the output\n+\t * is completely written to RAM.  This field should be read as '1'\n+\t * to indicate that the output has been completely written.\n+\t * When writing a command completion or response to an internal processor,\n+\t * the order of writes has to be such that this field is written last.\n \t */\n-\tuint32_t\tdst_ipaddr[4];\n+\tuint8_t\tvalid;\n+} __attribute__((packed));\n+\n+/***********************\n+ * hwrm_cfa_flow_flush *\n+ ***********************/\n+\n+\n+/* hwrm_cfa_flow_flush_input (size:192b/24B) */\n+struct hwrm_cfa_flow_flush_input {\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n \t/*\n-\t * The value of source port to be used in filtering.\n-\t * Applies to UDP and TCP traffic.\n+\t * The completion ring to send the completion event on. This should\n+\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n \t */\n-\tuint16_t\tsrc_port;\n+\tuint16_t\tcmpl_ring;\n \t/*\n-\t * The value of destination port to be used in filtering.\n-\t * Applies to UDP and TCP traffic.\n+\t * The sequence ID is used by the driver for tracking multiple\n+\t * commands. This ID is treated as opaque data by the firmware and\n+\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n \t */\n-\tuint16_t\tdst_port;\n+\tuint16_t\tseq_id;\n \t/*\n-\t * If set, this value shall represent the\n-\t * Logical VNIC ID of the destination VNIC for the RX\n-\t * path.\n+\t * The target ID of the command:\n+\t * * 0x0-0xFFF8 - The function ID\n+\t * * 0xFFF8-0xFFFE - Reserved for internal processors\n+\t * * 0xFFFF - HWRM\n \t */\n-\tuint16_t\tdst_id;\n+\tuint16_t\ttarget_id;\n \t/*\n-\t * If set, this value shall represent the L2 context that matches the L2\n-\t * information of the decap filter.\n+\t * A physical address pointer pointing to a host buffer that the\n+\t * command's response data will be written. This can be either a host\n+\t * physical address (HPA) or a guest physical address (GPA) and must\n+\t * point to a physically contiguous block of memory.\n \t */\n-\tuint16_t\tl2_ctxt_ref_id;\n+\tuint64_t\tresp_addr;\n+\tuint32_t\tflags;\n+\tuint8_t\tunused_0[4];\n } __attribute__((packed));\n \n-/* hwrm_cfa_decap_filter_alloc_output (size:128b/16B) */\n-struct hwrm_cfa_decap_filter_alloc_output {\n+/* hwrm_cfa_flow_flush_output (size:128b/16B) */\n+struct hwrm_cfa_flow_flush_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n \t/* The HWRM command request type. */\n@@ -23888,9 +25796,7 @@ struct hwrm_cfa_decap_filter_alloc_output {\n \tuint16_t\tseq_id;\n \t/* The length of the response data in number of bytes. */\n \tuint16_t\tresp_len;\n-\t/* This value is an opaque id into CFA data structures. */\n-\tuint32_t\tdecap_filter_id;\n-\tuint8_t\tunused_0[3];\n+\tuint8_t\tunused_0[7];\n \t/*\n \t * This field is used in Output records to indicate that the output\n \t * is completely written to RAM.  This field should be read as '1'\n@@ -23901,13 +25807,13 @@ struct hwrm_cfa_decap_filter_alloc_output {\n \tuint8_t\tvalid;\n } __attribute__((packed));\n \n-/******************************\n- * hwrm_cfa_decap_filter_free *\n- ******************************/\n+/***********************\n+ * hwrm_cfa_flow_stats *\n+ ***********************/\n \n \n-/* hwrm_cfa_decap_filter_free_input (size:192b/24B) */\n-struct hwrm_cfa_decap_filter_free_input {\n+/* hwrm_cfa_flow_stats_input (size:640b/80B) */\n+struct hwrm_cfa_flow_stats_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n \t/*\n@@ -23935,13 +25841,53 @@ struct hwrm_cfa_decap_filter_free_input {\n \t * point to a physically contiguous block of memory.\n \t */\n \tuint64_t\tresp_addr;\n-\t/* This value is an opaque id into CFA data structures. */\n-\tuint32_t\tdecap_filter_id;\n-\tuint8_t\tunused_0[4];\n+\t/* Flow handle. */\n+\tuint16_t\tnum_flows;\n+\t/* Flow handle. */\n+\tuint16_t\tflow_handle_0;\n+\t/* Flow handle. */\n+\tuint16_t\tflow_handle_1;\n+\t/* Flow handle. */\n+\tuint16_t\tflow_handle_2;\n+\t/* Flow handle. */\n+\tuint16_t\tflow_handle_3;\n+\t/* Flow handle. */\n+\tuint16_t\tflow_handle_4;\n+\t/* Flow handle. */\n+\tuint16_t\tflow_handle_5;\n+\t/* Flow handle. */\n+\tuint16_t\tflow_handle_6;\n+\t/* Flow handle. */\n+\tuint16_t\tflow_handle_7;\n+\t/* Flow handle. */\n+\tuint16_t\tflow_handle_8;\n+\t/* Flow handle. */\n+\tuint16_t\tflow_handle_9;\n+\tuint8_t\tunused_0[2];\n+\t/* Flow ID of a flow. */\n+\tuint32_t\tflow_id_0;\n+\t/* Flow ID of a flow. */\n+\tuint32_t\tflow_id_1;\n+\t/* Flow ID of a flow. */\n+\tuint32_t\tflow_id_2;\n+\t/* Flow ID of a flow. */\n+\tuint32_t\tflow_id_3;\n+\t/* Flow ID of a flow. */\n+\tuint32_t\tflow_id_4;\n+\t/* Flow ID of a flow. */\n+\tuint32_t\tflow_id_5;\n+\t/* Flow ID of a flow. */\n+\tuint32_t\tflow_id_6;\n+\t/* Flow ID of a flow. */\n+\tuint32_t\tflow_id_7;\n+\t/* Flow ID of a flow. */\n+\tuint32_t\tflow_id_8;\n+\t/* Flow ID of a flow. */\n+\tuint32_t\tflow_id_9;\n } __attribute__((packed));\n \n-/* hwrm_cfa_decap_filter_free_output (size:128b/16B) */\n-struct hwrm_cfa_decap_filter_free_output {\n+/* hwrm_cfa_flow_stats_output (size:1408b/176B) */\n+struct hwrm_cfa_flow_stats_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n \t/* The HWRM command request type. */\n@@ -23950,6 +25896,46 @@ struct hwrm_cfa_decap_filter_free_output {\n \tuint16_t\tseq_id;\n \t/* The length of the response data in number of bytes. */\n \tuint16_t\tresp_len;\n+\t/* packet_0 is 64 b */\n+\tuint64_t\tpacket_0;\n+\t/* packet_1 is 64 b */\n+\tuint64_t\tpacket_1;\n+\t/* packet_2 is 64 b */\n+\tuint64_t\tpacket_2;\n+\t/* packet_3 is 64 b */\n+\tuint64_t\tpacket_3;\n+\t/* packet_4 is 64 b */\n+\tuint64_t\tpacket_4;\n+\t/* packet_5 is 64 b */\n+\tuint64_t\tpacket_5;\n+\t/* packet_6 is 64 b */\n+\tuint64_t\tpacket_6;\n+\t/* packet_7 is 64 b */\n+\tuint64_t\tpacket_7;\n+\t/* packet_8 is 64 b */\n+\tuint64_t\tpacket_8;\n+\t/* packet_9 is 64 b */\n+\tuint64_t\tpacket_9;\n+\t/* byte_0 is 64 b */\n+\tuint64_t\tbyte_0;\n+\t/* byte_1 is 64 b */\n+\tuint64_t\tbyte_1;\n+\t/* byte_2 is 64 b */\n+\tuint64_t\tbyte_2;\n+\t/* byte_3 is 64 b */\n+\tuint64_t\tbyte_3;\n+\t/* byte_4 is 64 b */\n+\tuint64_t\tbyte_4;\n+\t/* byte_5 is 64 b */\n+\tuint64_t\tbyte_5;\n+\t/* byte_6 is 64 b */\n+\tuint64_t\tbyte_6;\n+\t/* byte_7 is 64 b */\n+\tuint64_t\tbyte_7;\n+\t/* byte_8 is 64 b */\n+\tuint64_t\tbyte_8;\n+\t/* byte_9 is 64 b */\n+\tuint64_t\tbyte_9;\n \tuint8_t\tunused_0[7];\n \t/*\n \t * This field is used in Output records to indicate that the output\n@@ -23961,13 +25947,13 @@ struct hwrm_cfa_decap_filter_free_output {\n \tuint8_t\tvalid;\n } __attribute__((packed));\n \n-/***********************\n- * hwrm_cfa_flow_alloc *\n- ***********************/\n+/***********************************\n+ * hwrm_cfa_flow_aging_timer_reset *\n+ ***********************************/\n \n \n-/* hwrm_cfa_flow_alloc_input (size:1024b/128B) */\n-struct hwrm_cfa_flow_alloc_input {\n+/* hwrm_cfa_flow_aging_timer_reset_input (size:256b/32B) */\n+struct hwrm_cfa_flow_aging_timer_reset_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n \t/*\n@@ -23989,219 +25975,21 @@ struct hwrm_cfa_flow_alloc_input {\n \t */\n \tuint16_t\ttarget_id;\n \t/*\n-\t * A physical address pointer pointing to a host buffer that the\n-\t * command's response data will be written. This can be either a host\n-\t * physical address (HPA) or a guest physical address (GPA) and must\n-\t * point to a physically contiguous block of memory.\n-\t */\n-\tuint64_t\tresp_addr;\n-\tuint16_t\tflags;\n-\t/* tunnel is 1 b */\n-\t#define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_TUNNEL \\\n-\t\tUINT32_C(0x1)\n-\t/* num_vlan is 2 b */\n-\t#define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_MASK \\\n-\t\tUINT32_C(0x6)\n-\t#define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_SFT           1\n-\t/* no tags */\n-\t#define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_NONE \\\n-\t\t(UINT32_C(0x0) << 1)\n-\t/* 1 tag */\n-\t#define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_ONE \\\n-\t\t(UINT32_C(0x1) << 1)\n-\t/* 2 tags */\n-\t#define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_TWO \\\n-\t\t(UINT32_C(0x2) << 1)\n-\t#define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_LAST \\\n-\t\tHWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_TWO\n-\t/* Enumeration denoting the Flow Type. */\n-\t#define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_MASK \\\n-\t\tUINT32_C(0x38)\n-\t#define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_SFT           3\n-\t/* L2 flow */\n-\t#define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_L2 \\\n-\t\t(UINT32_C(0x0) << 3)\n-\t/* IPV4 flow */\n-\t#define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_IPV4 \\\n-\t\t(UINT32_C(0x1) << 3)\n-\t/* IPV6 flow */\n-\t#define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_IPV6 \\\n-\t\t(UINT32_C(0x2) << 3)\n-\t#define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_LAST \\\n-\t\tHWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_IPV6\n-\t/*\n-\t * when set to 1, indicates TX flow offload for function specified in src_fid and\n-\t * the dst_fid should be set to invalid value. To indicate a VM to VM flow, both\n-\t * of the path_tx and path_rx flags need to be set. For virtio vSwitch offload\n-\t * case, the src_fid and dst_fid is set to the same fid value. For the SRIOV\n-\t * vSwitch offload case, the src_fid and dst_fid must be set to the same VF FID\n-\t * belong to the children VFs of the same PF to indicate VM to VM flow.\n-\t */\n-\t#define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_PATH_TX \\\n-\t\tUINT32_C(0x40)\n-\t/*\n-\t * when set to 1, indicates RX flow offload for function specified in dst_fid and\n-\t * the src_fid should be set to invalid value.\n-\t */\n-\t#define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_PATH_RX \\\n-\t\tUINT32_C(0x80)\n-\t/*\n-\t * Set to 1 to indicate matching of VXLAN VNI from the custom vxlan header is\n-\t * required and the VXLAN VNI value is stored in the first 24 bits of the dmac field.\n-\t * This flag is only valid when the flow direction is RX.\n-\t */\n-\t#define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_MATCH_VXLAN_IP_VNI \\\n-\t\tUINT32_C(0x100)\n-\t/*\n-\t * Tx Flow: vf fid.\n-\t * Rx Flow: pf fid.\n-\t */\n-\tuint16_t\tsrc_fid;\n-\t/* Tunnel handle valid when tunnel flag is set. */\n-\tuint32_t\ttunnel_handle;\n-\tuint16_t\taction_flags;\n-\t/*\n-\t * Setting of this flag indicates drop action. If this flag is not set,\n-\t * then it should be considered accept action.\n-\t */\n-\t#define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_FWD \\\n-\t\tUINT32_C(0x1)\n-\t/* recycle is 1 b */\n-\t#define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_RECYCLE \\\n-\t\tUINT32_C(0x2)\n-\t/*\n-\t * Setting of this flag indicates drop action. If this flag is not set,\n-\t * then it should be considered accept action.\n-\t */\n-\t#define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_DROP \\\n-\t\tUINT32_C(0x4)\n-\t/* meter is 1 b */\n-\t#define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_METER \\\n-\t\tUINT32_C(0x8)\n-\t/* tunnel is 1 b */\n-\t#define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_TUNNEL \\\n-\t\tUINT32_C(0x10)\n-\t/* nat_src is 1 b */\n-\t#define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NAT_SRC \\\n-\t\tUINT32_C(0x20)\n-\t/* nat_dest is 1 b */\n-\t#define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NAT_DEST \\\n-\t\tUINT32_C(0x40)\n-\t/* nat_ipv4_address is 1 b */\n-\t#define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NAT_IPV4_ADDRESS \\\n-\t\tUINT32_C(0x80)\n-\t/* l2_header_rewrite is 1 b */\n-\t#define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_L2_HEADER_REWRITE \\\n-\t\tUINT32_C(0x100)\n-\t/* ttl_decrement is 1 b */\n-\t#define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_TTL_DECREMENT \\\n-\t\tUINT32_C(0x200)\n-\t/*\n-\t * If set to 1 and flow direction is TX, it indicates decap of L2 header\n-\t * and encap of tunnel header. If set to 1 and flow direction is RX, it\n-\t * indicates decap of tunnel header and encap L2 header. The type of tunnel\n-\t * is specified in the tunnel_type field.\n-\t */\n-\t#define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_TUNNEL_IP \\\n-\t\tUINT32_C(0x400)\n-\t/*\n-\t * Tx Flow: pf or vf fid.\n-\t * Rx Flow: vf fid.\n-\t */\n-\tuint16_t\tdst_fid;\n-\t/* VLAN tpid, valid when push_vlan flag is set. */\n-\tuint16_t\tl2_rewrite_vlan_tpid;\n-\t/* VLAN tci, valid when push_vlan flag is set. */\n-\tuint16_t\tl2_rewrite_vlan_tci;\n-\t/* Meter id, valid when meter flag is set. */\n-\tuint16_t\tact_meter_id;\n-\t/* Flow with the same l2 context tcam key. */\n-\tuint16_t\tref_flow_handle;\n-\t/* This value sets the match value for the ethertype. */\n-\tuint16_t\tethertype;\n-\t/* valid when num tags is 1 or 2. */\n-\tuint16_t\touter_vlan_tci;\n-\t/* This value sets the match value for the Destination MAC address. */\n-\tuint16_t\tdmac[3];\n-\t/* valid when num tags is 2. */\n-\tuint16_t\tinner_vlan_tci;\n-\t/* This value sets the match value for the Source MAC address. */\n-\tuint16_t\tsmac[3];\n-\t/* The bit length of destination IP address mask. */\n-\tuint8_t\tip_dst_mask_len;\n-\t/* The bit length of source IP address mask. */\n-\tuint8_t\tip_src_mask_len;\n-\t/* The value of destination IPv4/IPv6 address. */\n-\tuint32_t\tip_dst[4];\n-\t/* The source IPv4/IPv6 address. */\n-\tuint32_t\tip_src[4];\n-\t/*\n-\t * The value of source port.\n-\t * Applies to UDP and TCP traffic.\n-\t */\n-\tuint16_t\tl4_src_port;\n-\t/*\n-\t * The value of source port mask.\n-\t * Applies to UDP and TCP traffic.\n-\t */\n-\tuint16_t\tl4_src_port_mask;\n-\t/*\n-\t * The value of destination port.\n-\t * Applies to UDP and TCP traffic.\n-\t */\n-\tuint16_t\tl4_dst_port;\n-\t/*\n-\t * The value of destination port mask.\n-\t * Applies to UDP and TCP traffic.\n-\t */\n-\tuint16_t\tl4_dst_port_mask;\n-\t/*\n-\t * NAT IPv4/6 address based on address type flag.\n-\t * 0 values are ignored.\n-\t */\n-\tuint32_t\tnat_ip_address[4];\n-\t/* L2 header re-write Destination MAC address. */\n-\tuint16_t\tl2_rewrite_dmac[3];\n-\t/*\n-\t * The NAT source/destination port based on direction flag.\n-\t * Applies to UDP and TCP traffic.\n-\t * 0 values are ignored.\n-\t */\n-\tuint16_t\tnat_port;\n-\t/* L2 header re-write Source MAC address. */\n-\tuint16_t\tl2_rewrite_smac[3];\n-\t/* The value of ip protocol. */\n-\tuint8_t\tip_proto;\n-\t/* Tunnel Type. */\n-\tuint8_t\ttunnel_type;\n-\t/* Non-tunnel */\n-\t#define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL UINT32_C(0x0)\n-\t/* Virtual eXtensible Local Area Network (VXLAN) */\n-\t#define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN     UINT32_C(0x1)\n-\t/* Network Virtualization Generic Routing Encapsulation (NVGRE) */\n-\t#define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_NVGRE     UINT32_C(0x2)\n-\t/* Generic Routing Encapsulation (GRE) inside Ethernet payload */\n-\t#define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_L2GRE     UINT32_C(0x3)\n-\t/* IP in IP */\n-\t#define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPIP      UINT32_C(0x4)\n-\t/* Generic Network Virtualization Encapsulation (Geneve) */\n-\t#define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_GENEVE    UINT32_C(0x5)\n-\t/* Multi-Protocol Lable Switching (MPLS) */\n-\t#define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_MPLS      UINT32_C(0x6)\n-\t/* Stateless Transport Tunnel (STT) */\n-\t#define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_STT       UINT32_C(0x7)\n-\t/* Generic Routing Encapsulation (GRE) inside IP datagram payload */\n-\t#define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPGRE     UINT32_C(0x8)\n-\t/* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */\n-\t#define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4  UINT32_C(0x9)\n-\t/* Any tunneled traffic */\n-\t#define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL UINT32_C(0xff)\n-\t#define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_LAST \\\n-\t\tHWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL\n+\t * A physical address pointer pointing to a host buffer that the\n+\t * command's response data will be written. This can be either a host\n+\t * physical address (HPA) or a guest physical address (GPA) and must\n+\t * point to a physically contiguous block of memory.\n+\t */\n+\tuint64_t\tresp_addr;\n+\t/* Flow record index. */\n+\tuint16_t\tflow_handle;\n+\tuint8_t\tunused_0[6];\n+\t/* This value identifies a set of CFA data structures used for a flow. */\n+\tuint64_t\text_flow_handle;\n } __attribute__((packed));\n \n-/* hwrm_cfa_flow_alloc_output (size:256b/32B) */\n-struct hwrm_cfa_flow_alloc_output {\n+/* hwrm_cfa_flow_aging_timer_reset_output (size:128b/16B) */\n+struct hwrm_cfa_flow_aging_timer_reset_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n \t/* The HWRM command request type. */\n@@ -24210,20 +25998,7 @@ struct hwrm_cfa_flow_alloc_output {\n \tuint16_t\tseq_id;\n \t/* The length of the response data in number of bytes. */\n \tuint16_t\tresp_len;\n-\t/* Flow record index. */\n-\tuint16_t\tflow_handle;\n-\tuint8_t\tunused_0[2];\n-\t/*\n-\t * This is the ID of the flow associated with this\n-\t * filter.\n-\t * This value shall be used to match and associate the\n-\t * flow identifier returned in completion records.\n-\t * A value of 0xFFFFFFFF shall indicate no flow id.\n-\t */\n-\tuint32_t\tflow_id;\n-\t/* This value identifies a set of CFA data structures used for a flow. */\n-\tuint64_t\text_flow_handle;\n-\tuint8_t\tunused_1[7];\n+\tuint8_t\tunused_0[7];\n \t/*\n \t * This field is used in Output records to indicate that the output\n \t * is completely written to RAM.  This field should be read as '1'\n@@ -24234,13 +26009,13 @@ struct hwrm_cfa_flow_alloc_output {\n \tuint8_t\tvalid;\n } __attribute__((packed));\n \n-/**********************\n- * hwrm_cfa_flow_free *\n- **********************/\n+/***************************\n+ * hwrm_cfa_flow_aging_cfg *\n+ ***************************/\n \n \n-/* hwrm_cfa_flow_free_input (size:256b/32B) */\n-struct hwrm_cfa_flow_free_input {\n+/* hwrm_cfa_flow_aging_cfg_input (size:256b/32B) */\n+struct hwrm_cfa_flow_aging_cfg_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n \t/*\n@@ -24268,15 +26043,38 @@ struct hwrm_cfa_flow_free_input {\n \t * point to a physically contiguous block of memory.\n \t */\n \tuint64_t\tresp_addr;\n-\t/* Flow record index. */\n-\tuint16_t\tflow_handle;\n-\tuint8_t\tunused_0[6];\n-\t/* This value identifies a set of CFA data structures used for a flow. */\n-\tuint64_t\text_flow_handle;\n+\t/* The bit field to enable per flow aging configuration. */\n+\tuint16_t\tenables;\n+\t/* This bit must be '1' for the tcp flow timer field to be configured */\n+\t#define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_TCP_FLOW_TIMER \\\n+\t\tUINT32_C(0x1)\n+\t/* This bit must be '1' for the tcp finish timer field to be configured */\n+\t#define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_TCP_FIN_TIMER \\\n+\t\tUINT32_C(0x2)\n+\t/* This bit must be '1' for the udp flow timer field to be configured */\n+\t#define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_UDP_FLOW_TIMER \\\n+\t\tUINT32_C(0x4)\n+\t/* The direction for the flow aging configuration, 1 is rx path, 2 is tx path. */\n+\tuint8_t\tflags;\n+\t/* Enumeration denoting the RX, TX type of the resource. */\n+\t#define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH     UINT32_C(0x1)\n+\t/* tx path */\n+\t#define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH_TX    UINT32_C(0x0)\n+\t/* rx path */\n+\t#define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH_RX    UINT32_C(0x1)\n+\t#define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH_LAST \\\n+\t\tHWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH_RX\n+\tuint8_t\tunused_0;\n+\t/* The flow aging timer for all TCP flows, the unit is 100 milliseconds. */\n+\tuint32_t\ttcp_flow_timer;\n+\t/* The TCP finished timer for all TCP flows, the unit is 100 milliseconds. */\n+\tuint32_t\ttcp_fin_timer;\n+\t/* The flow aging timer for all UDP flows, the unit is 100 milliseconds. */\n+\tuint32_t\tudp_flow_timer;\n } __attribute__((packed));\n \n-/* hwrm_cfa_flow_free_output (size:256b/32B) */\n-struct hwrm_cfa_flow_free_output {\n+/* hwrm_cfa_flow_aging_cfg_output (size:128b/16B) */\n+struct hwrm_cfa_flow_aging_cfg_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n \t/* The HWRM command request type. */\n@@ -24285,10 +26083,6 @@ struct hwrm_cfa_flow_free_output {\n \tuint16_t\tseq_id;\n \t/* The length of the response data in number of bytes. */\n \tuint16_t\tresp_len;\n-\t/* packet is 64 b */\n-\tuint64_t\tpacket;\n-\t/* byte is 64 b */\n-\tuint64_t\tbyte;\n \tuint8_t\tunused_0[7];\n \t/*\n \t * This field is used in Output records to indicate that the output\n@@ -24300,13 +26094,13 @@ struct hwrm_cfa_flow_free_output {\n \tuint8_t\tvalid;\n } __attribute__((packed));\n \n-/***********************\n- * hwrm_cfa_flow_flush *\n- ***********************/\n+/****************************\n+ * hwrm_cfa_flow_aging_qcfg *\n+ ****************************/\n \n \n-/* hwrm_cfa_flow_flush_input (size:192b/24B) */\n-struct hwrm_cfa_flow_flush_input {\n+/* hwrm_cfa_flow_aging_qcfg_input (size:192b/24B) */\n+struct hwrm_cfa_flow_aging_qcfg_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n \t/*\n@@ -24334,12 +26128,21 @@ struct hwrm_cfa_flow_flush_input {\n \t * point to a physically contiguous block of memory.\n \t */\n \tuint64_t\tresp_addr;\n-\tuint32_t\tflags;\n-\tuint8_t\tunused_0[4];\n+\t/* The direction for the flow aging configuration, 1 is rx path, 2 is tx path. */\n+\tuint8_t\tflags;\n+\t/* Enumeration denoting the RX, TX type of the resource. */\n+\t#define HWRM_CFA_FLOW_AGING_QCFG_INPUT_FLAGS_PATH     UINT32_C(0x1)\n+\t/* tx path */\n+\t#define HWRM_CFA_FLOW_AGING_QCFG_INPUT_FLAGS_PATH_TX    UINT32_C(0x0)\n+\t/* rx path */\n+\t#define HWRM_CFA_FLOW_AGING_QCFG_INPUT_FLAGS_PATH_RX    UINT32_C(0x1)\n+\t#define HWRM_CFA_FLOW_AGING_QCFG_INPUT_FLAGS_PATH_LAST \\\n+\t\tHWRM_CFA_FLOW_AGING_QCFG_INPUT_FLAGS_PATH_RX\n+\tuint8_t\tunused_0[7];\n } __attribute__((packed));\n \n-/* hwrm_cfa_flow_flush_output (size:128b/16B) */\n-struct hwrm_cfa_flow_flush_output {\n+/* hwrm_cfa_flow_aging_qcfg_output (size:192b/24B) */\n+struct hwrm_cfa_flow_aging_qcfg_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n \t/* The HWRM command request type. */\n@@ -24348,7 +26151,13 @@ struct hwrm_cfa_flow_flush_output {\n \tuint16_t\tseq_id;\n \t/* The length of the response data in number of bytes. */\n \tuint16_t\tresp_len;\n-\tuint8_t\tunused_0[7];\n+\t/* The current flow aging timer for all TCP flows, the unit is 100 millisecond. */\n+\tuint32_t\ttcp_flow_timer;\n+\t/* The current TCP finished timer for all TCP flows, the unit is 100 millisecond. */\n+\tuint32_t\ttcp_fin_timer;\n+\t/* The current flow aging timer for all UDP flows, the unit is 100 millisecond. */\n+\tuint32_t\tudp_flow_timer;\n+\tuint8_t\tunused_0[3];\n \t/*\n \t * This field is used in Output records to indicate that the output\n \t * is completely written to RAM.  This field should be read as '1'\n@@ -24359,13 +26168,13 @@ struct hwrm_cfa_flow_flush_output {\n \tuint8_t\tvalid;\n } __attribute__((packed));\n \n-/***********************\n- * hwrm_cfa_flow_stats *\n- ***********************/\n+/*****************************\n+ * hwrm_cfa_flow_aging_qcaps *\n+ *****************************/\n \n \n-/* hwrm_cfa_flow_stats_input (size:640b/80B) */\n-struct hwrm_cfa_flow_stats_input {\n+/* hwrm_cfa_flow_aging_qcaps_input (size:192b/24B) */\n+struct hwrm_cfa_flow_aging_qcaps_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n \t/*\n@@ -24393,53 +26202,21 @@ struct hwrm_cfa_flow_stats_input {\n \t * point to a physically contiguous block of memory.\n \t */\n \tuint64_t\tresp_addr;\n-\t/* Flow handle. */\n-\tuint16_t\tnum_flows;\n-\t/* Flow handle. */\n-\tuint16_t\tflow_handle_0;\n-\t/* Flow handle. */\n-\tuint16_t\tflow_handle_1;\n-\t/* Flow handle. */\n-\tuint16_t\tflow_handle_2;\n-\t/* Flow handle. */\n-\tuint16_t\tflow_handle_3;\n-\t/* Flow handle. */\n-\tuint16_t\tflow_handle_4;\n-\t/* Flow handle. */\n-\tuint16_t\tflow_handle_5;\n-\t/* Flow handle. */\n-\tuint16_t\tflow_handle_6;\n-\t/* Flow handle. */\n-\tuint16_t\tflow_handle_7;\n-\t/* Flow handle. */\n-\tuint16_t\tflow_handle_8;\n-\t/* Flow handle. */\n-\tuint16_t\tflow_handle_9;\n-\tuint8_t\tunused_0[2];\n-\t/* Flow ID of a flow. */\n-\tuint32_t\tflow_id_0;\n-\t/* Flow ID of a flow. */\n-\tuint32_t\tflow_id_1;\n-\t/* Flow ID of a flow. */\n-\tuint32_t\tflow_id_2;\n-\t/* Flow ID of a flow. */\n-\tuint32_t\tflow_id_3;\n-\t/* Flow ID of a flow. */\n-\tuint32_t\tflow_id_4;\n-\t/* Flow ID of a flow. */\n-\tuint32_t\tflow_id_5;\n-\t/* Flow ID of a flow. */\n-\tuint32_t\tflow_id_6;\n-\t/* Flow ID of a flow. */\n-\tuint32_t\tflow_id_7;\n-\t/* Flow ID of a flow. */\n-\tuint32_t\tflow_id_8;\n-\t/* Flow ID of a flow. */\n-\tuint32_t\tflow_id_9;\n+\t/* The direction for the flow aging configuration, 1 is rx path, 2 is tx path. */\n+\tuint8_t\tflags;\n+\t/* Enumeration denoting the RX, TX type of the resource. */\n+\t#define HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH     UINT32_C(0x1)\n+\t/* tx path */\n+\t#define HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH_TX    UINT32_C(0x0)\n+\t/* rx path */\n+\t#define HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH_RX    UINT32_C(0x1)\n+\t#define HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH_LAST \\\n+\t\tHWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH_RX\n+\tuint8_t\tunused_0[7];\n } __attribute__((packed));\n \n-/* hwrm_cfa_flow_stats_output (size:1408b/176B) */\n-struct hwrm_cfa_flow_stats_output {\n+/* hwrm_cfa_flow_aging_qcaps_output (size:256b/32B) */\n+struct hwrm_cfa_flow_aging_qcaps_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n \t/* The HWRM command request type. */\n@@ -24448,46 +26225,14 @@ struct hwrm_cfa_flow_stats_output {\n \tuint16_t\tseq_id;\n \t/* The length of the response data in number of bytes. */\n \tuint16_t\tresp_len;\n-\t/* packet_0 is 64 b */\n-\tuint64_t\tpacket_0;\n-\t/* packet_1 is 64 b */\n-\tuint64_t\tpacket_1;\n-\t/* packet_2 is 64 b */\n-\tuint64_t\tpacket_2;\n-\t/* packet_3 is 64 b */\n-\tuint64_t\tpacket_3;\n-\t/* packet_4 is 64 b */\n-\tuint64_t\tpacket_4;\n-\t/* packet_5 is 64 b */\n-\tuint64_t\tpacket_5;\n-\t/* packet_6 is 64 b */\n-\tuint64_t\tpacket_6;\n-\t/* packet_7 is 64 b */\n-\tuint64_t\tpacket_7;\n-\t/* packet_8 is 64 b */\n-\tuint64_t\tpacket_8;\n-\t/* packet_9 is 64 b */\n-\tuint64_t\tpacket_9;\n-\t/* byte_0 is 64 b */\n-\tuint64_t\tbyte_0;\n-\t/* byte_1 is 64 b */\n-\tuint64_t\tbyte_1;\n-\t/* byte_2 is 64 b */\n-\tuint64_t\tbyte_2;\n-\t/* byte_3 is 64 b */\n-\tuint64_t\tbyte_3;\n-\t/* byte_4 is 64 b */\n-\tuint64_t\tbyte_4;\n-\t/* byte_5 is 64 b */\n-\tuint64_t\tbyte_5;\n-\t/* byte_6 is 64 b */\n-\tuint64_t\tbyte_6;\n-\t/* byte_7 is 64 b */\n-\tuint64_t\tbyte_7;\n-\t/* byte_8 is 64 b */\n-\tuint64_t\tbyte_8;\n-\t/* byte_9 is 64 b */\n-\tuint64_t\tbyte_9;\n+\t/* The maximum flow aging timer for all TCP flows, the unit is 100 millisecond. */\n+\tuint32_t\tmax_tcp_flow_timer;\n+\t/* The maximum TCP finished timer for all TCP flows, the unit is 100 millisecond. */\n+\tuint32_t\tmax_tcp_fin_timer;\n+\t/* The maximum flow aging timer for all UDP flows, the unit is 100 millisecond. */\n+\tuint32_t\tmax_udp_flow_timer;\n+\t/* The maximum aging flows that HW can support. */\n+\tuint32_t\tmax_aging_flows;\n \tuint8_t\tunused_0[7];\n \t/*\n \t * This field is used in Output records to indicate that the output\n@@ -24706,6 +26451,12 @@ struct hwrm_cfa_redirect_query_tunnel_type_output {\n \t/* Any tunneled traffic */\n \t#define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_ANYTUNNEL \\\n \t\tUINT32_C(0x800)\n+\t/* Use fixed layer 2 ether type of 0xFFFF */\n+\t#define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_L2_ETYPE \\\n+\t\tUINT32_C(0x1000)\n+\t/* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */\n+\t#define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_VXLAN_GPE_V6 \\\n+\t\tUINT32_C(0x2000)\n \tuint8_t\tunused_0[3];\n \t/*\n \t * This field is used in Output records to indicate that the output\n@@ -24765,8 +26516,14 @@ struct hwrm_tunnel_dst_port_query_input {\n \t/* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */\n \t#define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_IPGRE_V1 \\\n \t\tUINT32_C(0xa)\n+\t/* Use fixed layer 2 ether type of 0xFFFF */\n+\t#define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_L2_ETYPE \\\n+\t\tUINT32_C(0xb)\n+\t/* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */\n+\t#define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \\\n+\t\tUINT32_C(0xc)\n \t#define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_LAST \\\n-\t\tHWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_IPGRE_V1\n+\t\tHWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6\n \tuint8_t\tunused_0[7];\n } __attribute__((packed));\n \n@@ -24857,8 +26614,14 @@ struct hwrm_tunnel_dst_port_alloc_input {\n \t/* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */\n \t#define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \\\n \t\tUINT32_C(0xa)\n+\t/* Use fixed layer 2 ether type of 0xFFFF */\n+\t#define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \\\n+\t\tUINT32_C(0xb)\n+\t/* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */\n+\t#define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \\\n+\t\tUINT32_C(0xc)\n \t#define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_LAST \\\n-\t\tHWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1\n+\t\tHWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6\n \tuint8_t\tunused_0;\n \t/*\n \t * This field represents the value of L4 destination port used\n@@ -24948,8 +26711,14 @@ struct hwrm_tunnel_dst_port_free_input {\n \t/* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */\n \t#define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_IPGRE_V1 \\\n \t\tUINT32_C(0xa)\n+\t/* Use fixed layer 2 ether type of 0xFFFF */\n+\t#define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_L2_ETYPE \\\n+\t\tUINT32_C(0xb)\n+\t/* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */\n+\t#define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \\\n+\t\tUINT32_C(0xc)\n \t#define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_LAST \\\n-\t\tHWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_IPGRE_V1\n+\t\tHWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6\n \tuint8_t\tunused_0;\n \t/*\n \t * Identifier of a tunnel L4 destination port value. Only applies to tunnel\n@@ -25025,6 +26794,52 @@ struct ctx_hw_stats {\n \tuint64_t\ttpa_aborts;\n } __attribute__((packed));\n \n+/* Periodic Engine statistics context DMA to host. */\n+/* ctx_eng_stats (size:512b/64B) */\n+struct ctx_eng_stats {\n+\t/*\n+\t * Count of data bytes into the Engine.\n+\t * This includes any user supplied prefix,\n+\t * but does not include any predefined\n+\t * prefix data.\n+\t */\n+\tuint64_t\teng_bytes_in;\n+\t/* Count of data bytes out of the Engine. */\n+\tuint64_t\teng_bytes_out;\n+\t/*\n+\t * Count, in 4-byte (dword) units, of bytes\n+\t * that are input as auxillary data.\n+\t * This includes the aux_cmd data.\n+\t */\n+\tuint64_t\taux_bytes_in;\n+\t/*\n+\t * Count, in 4-byte (dword) units, of bytes\n+\t * that are output as auxillary data.\n+\t * This count is the buffer space for aux_data\n+\t * output provided in the RQE, not the actual\n+\t * aux_data written\n+\t */\n+\tuint64_t\taux_bytes_out;\n+\t/* Count of number of commands executed. */\n+\tuint64_t\tcommands;\n+\t/*\n+\t * Count of number of error commands.\n+\t * These are the commands with a\n+\t * non-zero status value.\n+\t */\n+\tuint64_t\terror_commands;\n+\t/*\n+\t * Compression/Encryption Engine usage,\n+\t * the unit is count of clock cycles\n+\t */\n+\tuint64_t\tcce_engine_usage;\n+\t/*\n+\t * De-Compression/De-cryption Engine usage,\n+\t * the unit is count of clock cycles\n+\t */\n+\tuint64_t\tcdd_engine_usage;\n+} __attribute__((packed));\n+\n /***********************\n  * hwrm_stat_ctx_alloc *\n  ***********************/\n@@ -25081,7 +26896,7 @@ struct hwrm_stat_ctx_alloc_input {\n \t * than offloaded RoCE traffic shall not be included in this\n \t * statistic context.\n \t * When this bit is set to '0', the statistics context shall be\n-\t * used for the network traffic other than offloaded RoCE traffic.\n+\t * used for network traffic or engine traffic.\n \t */\n \t#define HWRM_STAT_CTX_ALLOC_INPUT_STAT_CTX_FLAGS_ROCE     UINT32_C(0x1)\n \tuint8_t\tunused_0[3];\n@@ -25272,6 +27087,107 @@ struct hwrm_stat_ctx_query_output {\n \tuint8_t\tvalid;\n } __attribute__((packed));\n \n+/***************************\n+ * hwrm_stat_ctx_eng_query *\n+ ***************************/\n+\n+\n+/* hwrm_stat_ctx_eng_query_input (size:192b/24B) */\n+struct hwrm_stat_ctx_eng_query_input {\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/*\n+\t * The completion ring to send the completion event on. This should\n+\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n+\t */\n+\tuint16_t\tcmpl_ring;\n+\t/*\n+\t * The sequence ID is used by the driver for tracking multiple\n+\t * commands. This ID is treated as opaque data by the firmware and\n+\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n+\t */\n+\tuint16_t\tseq_id;\n+\t/*\n+\t * The target ID of the command:\n+\t * * 0x0-0xFFF8 - The function ID\n+\t * * 0xFFF8-0xFFFE - Reserved for internal processors\n+\t * * 0xFFFF - HWRM\n+\t */\n+\tuint16_t\ttarget_id;\n+\t/*\n+\t * A physical address pointer pointing to a host buffer that the\n+\t * command's response data will be written. This can be either a host\n+\t * physical address (HPA) or a guest physical address (GPA) and must\n+\t * point to a physically contiguous block of memory.\n+\t */\n+\tuint64_t\tresp_addr;\n+\t/* ID of the statistics context that is being queried. */\n+\tuint32_t\tstat_ctx_id;\n+\tuint8_t\tunused_0[4];\n+} __attribute__((packed));\n+\n+/* hwrm_stat_ctx_eng_query_output (size:640b/80B) */\n+struct hwrm_stat_ctx_eng_query_output {\n+\t/* The specific error status for the command. */\n+\tuint16_t\terror_code;\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/* The sequence ID from the original command. */\n+\tuint16_t\tseq_id;\n+\t/* The length of the response data in number of bytes. */\n+\tuint16_t\tresp_len;\n+\t/*\n+\t * Count of data bytes into the Engine.\n+\t * This includes any user supplied prefix,\n+\t * but does not include any predefined\n+\t * prefix data.\n+\t */\n+\tuint64_t\teng_bytes_in;\n+\t/* Count of data bytes out of the Engine. */\n+\tuint64_t\teng_bytes_out;\n+\t/*\n+\t * Count, in 4-byte (dword) units, of bytes\n+\t * that are input as auxillary data.\n+\t * This includes the aux_cmd data.\n+\t */\n+\tuint64_t\taux_bytes_in;\n+\t/*\n+\t * Count, in 4-byte (dword) units, of bytes\n+\t * that are output as auxillary data.\n+\t * This count is the buffer space for aux_data\n+\t * output provided in the RQE, not the actual\n+\t * aux_data written\n+\t */\n+\tuint64_t\taux_bytes_out;\n+\t/* Count of number of commands executed. */\n+\tuint64_t\tcommands;\n+\t/*\n+\t * Count of number of error commands.\n+\t * These are the commands with a\n+\t * non-zero status value.\n+\t */\n+\tuint64_t\terror_commands;\n+\t/*\n+\t * Compression/Encryption Engine usage,\n+\t * the unit is count of clock cycles\n+\t */\n+\tuint64_t\tcce_engine_usage;\n+\t/*\n+\t * De-Compression/De-cryption Engine usage,\n+\t * the unit is count of clock cycles\n+\t */\n+\tuint64_t\tcdd_engine_usage;\n+\tuint8_t\tunused_0[7];\n+\t/*\n+\t * This field is used in Output records to indicate that the output\n+\t * is completely written to RAM.  This field should be read as '1'\n+\t * to indicate that the output has been completely written.\n+\t * When writing a command completion or response to an internal processor,\n+\t * the order of writes has to be such that this field is written last.\n+\t */\n+\tuint8_t\tvalid;\n+} __attribute__((packed));\n+\n /***************************\n  * hwrm_stat_ctx_clr_stats *\n  ***************************/\n",
    "prefixes": [
        "08/11"
    ]
}