Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/53602/?format=api
{ "id": 53602, "url": "http://patches.dpdk.org/api/patches/53602/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20190521213953.25425-10-ajit.khaparde@broadcom.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20190521213953.25425-10-ajit.khaparde@broadcom.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20190521213953.25425-10-ajit.khaparde@broadcom.com", "date": "2019-05-21T21:39:51", "name": "[09/11] net/bnxt: update HWRM version", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "73187143dbaac31aaa5d084d5ea6f2d260e1a2af", "submitter": { "id": 501, "url": "http://patches.dpdk.org/api/people/501/?format=api", "name": "Ajit Khaparde", "email": "ajit.khaparde@broadcom.com" }, "delegate": { "id": 319, "url": "http://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20190521213953.25425-10-ajit.khaparde@broadcom.com/mbox/", "series": [ { "id": 4736, "url": "http://patches.dpdk.org/api/series/4736/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=4736", "date": "2019-05-21T21:39:43", "name": "bnxt patchset", "version": 1, "mbox": "http://patches.dpdk.org/series/4736/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/53602/comments/", "check": "warning", "checks": "http://patches.dpdk.org/api/patches/53602/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 07F766C9B;\n\tTue, 21 May 2019 23:40:25 +0200 (CEST)", "from rnd-relay.smtp.broadcom.com (rnd-relay.smtp.broadcom.com\n\t[192.19.229.170]) by dpdk.org (Postfix) with ESMTP id E4CC04F91\n\tfor <dev@dpdk.org>; Tue, 21 May 2019 23:39:58 +0200 (CEST)", "from nis-sj1-27.broadcom.com (nis-sj1-27.lvn.broadcom.net\n\t[10.75.144.136])\n\tby rnd-relay.smtp.broadcom.com (Postfix) with ESMTP id 7DC8230C0E1;\n\tTue, 21 May 2019 14:39:56 -0700 (PDT)", "from C02VPB22HTD6.wifi.broadcom.net (c02vpb22htd6.wifi.broadcom.net\n\t[10.69.74.102])\n\tby nis-sj1-27.broadcom.com (Postfix) with ESMTP id 75A26AC072B;\n\tTue, 21 May 2019 14:39:56 -0700 (PDT)" ], "DKIM-Filter": "OpenDKIM Filter v2.10.3 rnd-relay.smtp.broadcom.com 7DC8230C0E1", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple; d=broadcom.com;\n\ts=dkimrelay; t=1558474796;\n\tbh=aYBnIMSEDNew7SYbelx4Cfxw3fDS5iXptmjMYCm3Ehg=;\n\th=From:To:Cc:Subject:Date:In-Reply-To:References:From;\n\tb=Z8aIRsqeUuGUDjjsAuV/e/icolWFTbm2IB2ylRw3Mo1LA+a01Av2nMOwXgP2cSdMa\n\tariTuK1qy3FTLXDfFQp7bLxJOryRfWF8Fc45qm4+gwFtvrh4f93R4K2ojjtaqs4RZd\n\t75Y4RsSSqMIFZ4Q93pb8BNeWH8Mxre2+3C5r39F8=", "From": "Ajit Khaparde <ajit.khaparde@broadcom.com>", "To": "dev@dpdk.org", "Cc": "ferruh.yigit@intel.com, Lance Richardson <lance.richardson@broadcom.com>", "Date": "Tue, 21 May 2019 14:39:51 -0700", "Message-Id": "<20190521213953.25425-10-ajit.khaparde@broadcom.com>", "X-Mailer": "git-send-email 2.20.1 (Apple Git-117)", "In-Reply-To": "<20190521213953.25425-1-ajit.khaparde@broadcom.com>", "References": "<20190521213953.25425-1-ajit.khaparde@broadcom.com>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=UTF-8", "Content-Transfer-Encoding": "8bit", "Subject": "[dpdk-dev] [PATCH 09/11] net/bnxt: update HWRM version", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Update HWRM version to 1.10.0.48\n\nSigned-off-by: Ajit Khaparde <ajit.khaparde@broadcom.com>\nReviewed-by: Lance Richardson <lance.richardson@broadcom.com>\n---\n drivers/net/bnxt/hsi_struct_def_dpdk.h | 3156 +++++++++++++++++++++---\n 1 file changed, 2874 insertions(+), 282 deletions(-)", "diff": "diff --git a/drivers/net/bnxt/hsi_struct_def_dpdk.h b/drivers/net/bnxt/hsi_struct_def_dpdk.h\nindex ea9a7d40e..00a8ff87e 100644\n--- a/drivers/net/bnxt/hsi_struct_def_dpdk.h\n+++ b/drivers/net/bnxt/hsi_struct_def_dpdk.h\n@@ -260,6 +260,7 @@ struct cmd_nums {\n \t */\n \tuint16_t\treq_type;\n \t#define HWRM_VER_GET UINT32_C(0x0)\n+\t#define HWRM_ERROR_RECOVERY_QCFG UINT32_C(0xc)\n \t#define HWRM_FUNC_DRV_IF_CHANGE UINT32_C(0xd)\n \t#define HWRM_FUNC_BUF_UNRGTR UINT32_C(0xe)\n \t#define HWRM_FUNC_VF_CFG UINT32_C(0xf)\n@@ -372,6 +373,8 @@ struct cmd_nums {\n \t#define HWRM_STAT_CTX_QUERY UINT32_C(0xb2)\n \t#define HWRM_STAT_CTX_CLR_STATS UINT32_C(0xb3)\n \t#define HWRM_PORT_QSTATS_EXT UINT32_C(0xb4)\n+\t#define HWRM_PORT_PHY_MDIO_WRITE UINT32_C(0xb5)\n+\t#define HWRM_PORT_PHY_MDIO_READ UINT32_C(0xb6)\n \t#define HWRM_FW_RESET UINT32_C(0xc0)\n \t#define HWRM_FW_QSTATUS UINT32_C(0xc1)\n \t#define HWRM_FW_HEALTH_CHECK UINT32_C(0xc2)\n@@ -397,6 +400,8 @@ struct cmd_nums {\n \t#define HWRM_WOL_FILTER_QCFG UINT32_C(0xf2)\n \t#define HWRM_WOL_REASON_QCFG UINT32_C(0xf3)\n \t/* Experimental */\n+\t#define HWRM_CFA_METER_QCAPS UINT32_C(0xf4)\n+\t/* Experimental */\n \t#define HWRM_CFA_METER_PROFILE_ALLOC UINT32_C(0xf5)\n \t/* Experimental */\n \t#define HWRM_CFA_METER_PROFILE_FREE UINT32_C(0xf6)\n@@ -407,6 +412,8 @@ struct cmd_nums {\n \t/* Experimental */\n \t#define HWRM_CFA_METER_INSTANCE_FREE UINT32_C(0xf9)\n \t/* Experimental */\n+\t#define HWRM_CFA_METER_INSTANCE_CFG UINT32_C(0xfa)\n+\t/* Experimental */\n \t#define HWRM_CFA_VFR_ALLOC UINT32_C(0xfd)\n \t/* Experimental */\n \t#define HWRM_CFA_VFR_FREE UINT32_C(0xfe)\n@@ -451,6 +458,34 @@ struct cmd_nums {\n \t#define HWRM_CFA_FLOW_AGING_QCFG UINT32_C(0x115)\n \t/* Experimental */\n \t#define HWRM_CFA_FLOW_AGING_QCAPS UINT32_C(0x116)\n+\t/* Experimental */\n+\t#define HWRM_CFA_CTX_MEM_RGTR UINT32_C(0x117)\n+\t/* Experimental */\n+\t#define HWRM_CFA_CTX_MEM_UNRGTR UINT32_C(0x118)\n+\t/* Experimental */\n+\t#define HWRM_CFA_CTX_MEM_QCTX UINT32_C(0x119)\n+\t/* Experimental */\n+\t#define HWRM_CFA_CTX_MEM_QCAPS UINT32_C(0x11a)\n+\t/* Experimental */\n+\t#define HWRM_CFA_COUNTER_QCAPS UINT32_C(0x11b)\n+\t/* Experimental */\n+\t#define HWRM_CFA_COUNTER_CFG UINT32_C(0x11c)\n+\t/* Experimental */\n+\t#define HWRM_CFA_COUNTER_QCFG UINT32_C(0x11d)\n+\t/* Experimental */\n+\t#define HWRM_CFA_COUNTER_QSTATS UINT32_C(0x11e)\n+\t/* Experimental */\n+\t#define HWRM_CFA_TCP_FLAG_PROCESS_QCFG UINT32_C(0x11f)\n+\t/* Experimental */\n+\t#define HWRM_CFA_EEM_QCAPS UINT32_C(0x120)\n+\t/* Experimental */\n+\t#define HWRM_CFA_EEM_CFG UINT32_C(0x121)\n+\t/* Experimental */\n+\t#define HWRM_CFA_EEM_QCFG UINT32_C(0x122)\n+\t/* Experimental */\n+\t#define HWRM_CFA_EEM_OP UINT32_C(0x123)\n+\t/* Experimental */\n+\t#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS UINT32_C(0x124)\n \t/* Engine CKV - Ping the device and SRT firmware to get the public key. */\n \t#define HWRM_ENGINE_CKV_HELLO UINT32_C(0x12d)\n \t/* Engine CKV - Get the current allocation status of keys provisioned in the key vault. */\n@@ -469,6 +504,8 @@ struct cmd_nums {\n \t#define HWRM_ENGINE_CKV_RNG_GET UINT32_C(0x134)\n \t/* Engine CKV - Generate and encrypt a new AES key. */\n \t#define HWRM_ENGINE_CKV_KEY_GEN UINT32_C(0x135)\n+\t/* Engine CKV - Configure a label index with a label value. */\n+\t#define HWRM_ENGINE_CKV_KEY_LABEL_CFG UINT32_C(0x136)\n \t/* Engine - Query the available queue groups configuration. */\n \t#define HWRM_ENGINE_QG_CONFIG_QUERY UINT32_C(0x13c)\n \t/* Engine - Query the queue groups assigned to a function. */\n@@ -523,6 +560,8 @@ struct cmd_nums {\n \t#define HWRM_ENGINE_NQ_FREE UINT32_C(0x163)\n \t/* Engine - Set the on-die RQE credit update location. */\n \t#define HWRM_ENGINE_ON_DIE_RQE_CREDITS UINT32_C(0x164)\n+\t/* Engine - Query the engine function configuration. */\n+\t#define HWRM_ENGINE_FUNC_QCFG UINT32_C(0x165)\n \t/* Experimental */\n \t#define HWRM_FUNC_RESOURCE_QCAPS UINT32_C(0x190)\n \t/* Experimental */\n@@ -573,6 +612,10 @@ struct cmd_nums {\n \t/* */\n \t#define HWRM_DBG_RING_INFO_GET UINT32_C(0xff1c)\n \t/* Experimental */\n+\t#define HWRM_DBG_CRASHDUMP_HEADER UINT32_C(0xff1d)\n+\t/* Experimental */\n+\t#define HWRM_DBG_CRASHDUMP_ERASE UINT32_C(0xff1e)\n+\t/* Experimental */\n \t#define HWRM_NVM_FACTORY_DEFAULTS UINT32_C(0xffee)\n \t#define HWRM_NVM_VALIDATE_OPTION UINT32_C(0xffef)\n \t#define HWRM_NVM_FLUSH UINT32_C(0xfff0)\n@@ -724,8 +767,8 @@ struct hwrm_err_output {\n #define HWRM_NA_SIGNATURE ((uint32_t)(-1))\n /* hwrm_func_buf_rgtr */\n #define HWRM_MAX_REQ_LEN 128\n-/* hwrm_selftest_qlist */\n-#define HWRM_MAX_RESP_LEN 280\n+/* hwrm_cfa_flow_info */\n+#define HWRM_MAX_RESP_LEN 704\n /* 7 bit indirection table index. */\n #define HW_HASH_INDEX_SIZE 0x80\n #define HW_HASH_KEY_SIZE 40\n@@ -735,8 +778,8 @@ struct hwrm_err_output {\n #define HWRM_VERSION_MINOR 10\n #define HWRM_VERSION_UPDATE 0\n /* non-zero means beta version */\n-#define HWRM_VERSION_RSVD 19\n-#define HWRM_VERSION_STR \"1.10.0.19\"\n+#define HWRM_VERSION_RSVD 48\n+#define HWRM_VERSION_STR \"1.10.0.48\"\n \n /****************\n * hwrm_ver_get *\n@@ -993,6 +1036,32 @@ struct hwrm_ver_get_output {\n \t */\n \t#define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_FLOW_AGING_SUPPORTED \\\n \t\tUINT32_C(0x200)\n+\t/*\n+\t * If set to 1, firmware is capable to support advanced flow counters like,\n+\t * Meter drop counters and EEM counters.\n+\t * If set to 0, firmware is not capable to support advanced flow counters.\n+\t * By default, this flag should be 0 for older version of core firmware.\n+\t */\n+\t#define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_ADV_FLOW_COUNTERS_SUPPORTED \\\n+\t\tUINT32_C(0x400)\n+\t/*\n+\t * If set to 1, the firmware is able to support the use of the CFA\n+\t * Extended Exact Match(EEM) feature.\n+\t * If set to 0, firmware is not capable to support the use of the\n+\t * CFA EEM feature.\n+\t * By default, this flag should be 0 for older version of core firmware.\n+\t */\n+\t#define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_EEM_SUPPORTED \\\n+\t\tUINT32_C(0x800)\n+\t/*\n+\t * If set to 1, the firmware is able to support advance CFA flow management\n+\t * features reported in the HWRM_CFA_FLOW_MGNT_QCAPS.\n+\t * If set to 0, then the firmware doesn’t support the advance CFA flow management\n+\t * features.\n+\t * By default, this flag should be 0 for older version of core firmware.\n+\t */\n+\t#define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED \\\n+\t\tUINT32_C(0x1000)\n \t/*\n \t * This field represents the major version of RoCE firmware.\n \t * A change in major version represents a major release.\n@@ -3695,6 +3764,9 @@ struct hwrm_async_event_cmpl {\n \t/* Reset notification to clients */\n \t#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_RESET_NOTIFY \\\n \t\tUINT32_C(0x8)\n+\t/* Master function selection event */\n+\t#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_ERROR_RECOVERY \\\n+\t\tUINT32_C(0x9)\n \t/* Function driver unloaded */\n \t#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_UNLOAD \\\n \t\tUINT32_C(0x10)\n@@ -3739,6 +3811,40 @@ struct hwrm_async_event_cmpl {\n \t */\n \t#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_DEBUG_NOTIFICATION \\\n \t\tUINT32_C(0x37)\n+\t/*\n+\t * A EEM flow cached memory flush request event being posted to the PF\n+\t * driver.\n+\t */\n+\t#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_EEM_CACHE_FLUSH_REQ \\\n+\t\tUINT32_C(0x38)\n+\t/*\n+\t * A EEM flow cache memory flush completion event being posted to the\n+\t * firmware by the PF driver. This is indication that host EEM flush\n+\t * has completed by the PF.\n+\t */\n+\t#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_EEM_CACHE_FLUSH_DONE \\\n+\t\tUINT32_C(0x39)\n+\t/*\n+\t * A tcp flag action change event being posted to the PF or trusted VF\n+\t * driver by the firmware. The PF or trusted VF driver should query\n+\t * the firmware for the new TCP flag action update after receiving\n+\t * this async event.\n+\t */\n+\t#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_TCP_FLAG_ACTION_CHANGE \\\n+\t\tUINT32_C(0x3a)\n+\t/*\n+\t * A eem flow active event being posted to the PF or trusted VF driver\n+\t * by the firmware. The PF or trusted VF driver should update the\n+\t * flow's aging timer after receiving this async event.\n+\t */\n+\t#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_EEM_FLOW_ACTIVE \\\n+\t\tUINT32_C(0x3b)\n+\t/*\n+\t * A eem cfg change event being posted to the trusted VF driver by the\n+\t * firmware if the parent PF EEM configuration changed.\n+\t */\n+\t#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_EEM_CFG_CHANGE \\\n+\t\tUINT32_C(0x3c)\n \t/*\n \t * A trace log message. This contains firmware trace logs string\n \t * embedded in the asynchronous message. This is an experimental\n@@ -4450,6 +4556,75 @@ struct hwrm_async_event_cmpl_reset_notify {\n \t\t16\n } __attribute__((packed));\n \n+/* hwrm_async_event_cmpl_error_recovery (size:128b/16B) */\n+struct hwrm_async_event_cmpl_error_recovery {\n+\tuint16_t\ttype;\n+\t/*\n+\t * This field indicates the exact type of the completion.\n+\t * By convention, the LSB identifies the length of the\n+\t * record in 16B units. Even values indicate 16B\n+\t * records. Odd values indicate 32B\n+\t * records.\n+\t */\n+\t#define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_MASK \\\n+\t\tUINT32_C(0x3f)\n+\t#define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_SFT 0\n+\t/* HWRM Asynchronous Event Information */\n+\t#define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_HWRM_ASYNC_EVENT \\\n+\t\tUINT32_C(0x2e)\n+\t#define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_LAST \\\n+\t\tHWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_HWRM_ASYNC_EVENT\n+\t/* Identifiers of events. */\n+\tuint16_t\tevent_id;\n+\t/*\n+\t * This async notification message can be used for selecting or\n+\t * deselecting master function for error recovery,\n+\t * and to communicate to all the functions whether error recovery\n+\t * was enabled/disabled.\n+\t */\n+\t#define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_ERROR_RECOVERY \\\n+\t\tUINT32_C(0x9)\n+\t#define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_LAST \\\n+\t\tHWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_ERROR_RECOVERY\n+\t/* Event specific data */\n+\tuint32_t\tevent_data2;\n+\tuint8_t\topaque_v;\n+\t/*\n+\t * This value is written by the NIC such that it will be different\n+\t * for each pass through the completion queue. The even passes\n+\t * will write 1. The odd passes will write 0.\n+\t */\n+\t#define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_V UINT32_C(0x1)\n+\t/* opaque is 7 b */\n+\t#define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_OPAQUE_MASK UINT32_C(0xfe)\n+\t#define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_OPAQUE_SFT 1\n+\t/* 8-lsb timestamp (100-msec resolution) */\n+\tuint8_t\ttimestamp_lo;\n+\t/* 16-lsb timestamp (100-msec resolution) */\n+\tuint16_t\ttimestamp_hi;\n+\t/* Event specific data */\n+\tuint32_t\tevent_data1;\n+\t/* Indicates driver action requested */\n+\t#define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_MASK \\\n+\t\tUINT32_C(0xff)\n+\t#define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_SFT \\\n+\t\t0\n+\t/*\n+\t * If set to 1, this function is selected as Master function.\n+\t * This function has responsibility to do 'chip reset' when it\n+\t * detects a fatal error. If set to 0, master function functionality\n+\t * is disabled on this function.\n+\t */\n+\t#define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_MASTER_FUNC \\\n+\t\tUINT32_C(0x1)\n+\t/*\n+\t * If set to 1, error recovery is enabled.\n+\t * If set to 0, error recovery is disabled.\n+\t */\n+\t#define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_RECOVERY_ENABLED \\\n+\t\tUINT32_C(0x2)\n+} __attribute__((packed));\n+\n /* hwrm_async_event_cmpl_func_drvr_unload (size:128b/16B) */\n struct hwrm_async_event_cmpl_func_drvr_unload {\n \tuint16_t\ttype;\n@@ -5182,8 +5357,8 @@ struct hwrm_async_event_cmpl_hw_flow_aged {\n \t\tHWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_TX\n } __attribute__((packed));\n \n-/* hwrm_async_event_cmpl_hwrm_error (size:128b/16B) */\n-struct hwrm_async_event_cmpl_hwrm_error {\n+/* hwrm_async_event_cmpl_eem_cache_flush_req (size:128b/16B) */\n+struct hwrm_async_event_cmpl_eem_cache_flush_req {\n \tuint16_t\ttype;\n \t/*\n \t * This field indicates the exact type of the completion.\n@@ -5192,133 +5367,549 @@ struct hwrm_async_event_cmpl_hwrm_error {\n \t * records. Odd values indicate 32B\n \t * records.\n \t */\n-\t#define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_MASK \\\n+\t#define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_MASK \\\n \t\tUINT32_C(0x3f)\n-\t#define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_SFT 0\n+\t#define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_SFT \\\n+\t\t0\n \t/* HWRM Asynchronous Event Information */\n-\t#define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_HWRM_ASYNC_EVENT \\\n+\t#define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_HWRM_ASYNC_EVENT \\\n \t\tUINT32_C(0x2e)\n-\t#define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_LAST \\\n-\t\tHWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_HWRM_ASYNC_EVENT\n+\t#define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_LAST \\\n+\t\tHWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_HWRM_ASYNC_EVENT\n \t/* Identifiers of events. */\n \tuint16_t\tevent_id;\n-\t/* HWRM Error */\n-\t#define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_HWRM_ERROR \\\n-\t\tUINT32_C(0xff)\n-\t#define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_LAST \\\n-\t\tHWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_HWRM_ERROR\n+\t/* Notification of a eem_cache_flush request */\n+\t#define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_EEM_CACHE_FLUSH_REQ \\\n+\t\tUINT32_C(0x38)\n+\t#define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_LAST \\\n+\t\tHWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_EEM_CACHE_FLUSH_REQ\n \t/* Event specific data */\n \tuint32_t\tevent_data2;\n-\t/* Severity of HWRM Error */\n-\t#define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_MASK \\\n-\t\tUINT32_C(0xff)\n-\t#define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_SFT 0\n-\t/* Warning */\n-\t#define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_WARNING \\\n-\t\tUINT32_C(0x0)\n-\t/* Non-fatal Error */\n-\t#define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_NONFATAL \\\n-\t\tUINT32_C(0x1)\n-\t/* Fatal Error */\n-\t#define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_FATAL \\\n-\t\tUINT32_C(0x2)\n-\t#define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_LAST \\\n-\t\tHWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_FATAL\n \tuint8_t\topaque_v;\n \t/*\n \t * This value is written by the NIC such that it will be different\n \t * for each pass through the completion queue. The even passes\n \t * will write 1. The odd passes will write 0.\n \t */\n-\t#define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_V UINT32_C(0x1)\n+\t#define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_V \\\n+\t\tUINT32_C(0x1)\n \t/* opaque is 7 b */\n-\t#define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_OPAQUE_MASK UINT32_C(0xfe)\n-\t#define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_OPAQUE_SFT 1\n+\t#define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_OPAQUE_MASK \\\n+\t\tUINT32_C(0xfe)\n+\t#define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_OPAQUE_SFT 1\n \t/* 8-lsb timestamp from POR (100-msec resolution) */\n \tuint8_t\ttimestamp_lo;\n \t/* 16-lsb timestamp from POR (100-msec resolution) */\n \tuint16_t\ttimestamp_hi;\n \t/* Event specific data */\n \tuint32_t\tevent_data1;\n-\t/* Time stamp for error event */\n-\t#define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA1_TIMESTAMP \\\n-\t\tUINT32_C(0x1)\n } __attribute__((packed));\n \n-/*******************\n- * hwrm_func_reset *\n- *******************/\n-\n-\n-/* hwrm_func_reset_input (size:192b/24B) */\n-struct hwrm_func_reset_input {\n-\t/* The HWRM command request type. */\n-\tuint16_t\treq_type;\n+/* hwrm_async_event_cmpl_eem_cache_flush_done (size:128b/16B) */\n+struct hwrm_async_event_cmpl_eem_cache_flush_done {\n+\tuint16_t\ttype;\n \t/*\n-\t * The completion ring to send the completion event on. This should\n-\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n+\t * This field indicates the exact type of the completion.\n+\t * By convention, the LSB identifies the length of the\n+\t * record in 16B units. Even values indicate 16B\n+\t * records. Odd values indicate 32B\n+\t * records.\n \t */\n-\tuint16_t\tcmpl_ring;\n+\t#define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_MASK \\\n+\t\tUINT32_C(0x3f)\n+\t#define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_SFT \\\n+\t\t0\n+\t/* HWRM Asynchronous Event Information */\n+\t#define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_HWRM_ASYNC_EVENT \\\n+\t\tUINT32_C(0x2e)\n+\t#define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_LAST \\\n+\t\tHWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_HWRM_ASYNC_EVENT\n+\t/* Identifiers of events. */\n+\tuint16_t\tevent_id;\n \t/*\n-\t * The sequence ID is used by the driver for tracking multiple\n-\t * commands. This ID is treated as opaque data by the firmware and\n-\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n+\t * Notification of a host eem_cache_flush has completed. This event\n+\t * is generated by the host driver.\n \t */\n-\tuint16_t\tseq_id;\n+\t#define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_EEM_CACHE_FLUSH_DONE \\\n+\t\tUINT32_C(0x39)\n+\t#define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_LAST \\\n+\t\tHWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_EEM_CACHE_FLUSH_DONE\n+\t/* Event specific data */\n+\tuint32_t\tevent_data2;\n+\tuint8_t\topaque_v;\n \t/*\n-\t * The target ID of the command:\n-\t * * 0x0-0xFFF8 - The function ID\n-\t * * 0xFFF8-0xFFFE - Reserved for internal processors\n-\t * * 0xFFFF - HWRM\n+\t * This value is written by the NIC such that it will be different\n+\t * for each pass through the completion queue. The even passes\n+\t * will write 1. The odd passes will write 0.\n \t */\n-\tuint16_t\ttarget_id;\n+\t#define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_V \\\n+\t\tUINT32_C(0x1)\n+\t/* opaque is 7 b */\n+\t#define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_OPAQUE_MASK \\\n+\t\tUINT32_C(0xfe)\n+\t#define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_OPAQUE_SFT 1\n+\t/* 8-lsb timestamp from POR (100-msec resolution) */\n+\tuint8_t\ttimestamp_lo;\n+\t/* 16-lsb timestamp from POR (100-msec resolution) */\n+\tuint16_t\ttimestamp_hi;\n+\t/* Event specific data */\n+\tuint32_t\tevent_data1;\n+\t/* Indicates function ID that this event occured on. */\n+\t#define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_DATA1_FID_MASK \\\n+\t\tUINT32_C(0xffff)\n+\t#define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_DATA1_FID_SFT \\\n+\t\t0\n+} __attribute__((packed));\n+\n+/* hwrm_async_event_cmpl_tcp_flag_action_change (size:128b/16B) */\n+struct hwrm_async_event_cmpl_tcp_flag_action_change {\n+\tuint16_t\ttype;\n \t/*\n-\t * A physical address pointer pointing to a host buffer that the\n-\t * command's response data will be written. This can be either a host\n-\t * physical address (HPA) or a guest physical address (GPA) and must\n-\t * point to a physically contiguous block of memory.\n+\t * This field indicates the exact type of the completion.\n+\t * By convention, the LSB identifies the length of the\n+\t * record in 16B units. Even values indicate 16B\n+\t * records. Odd values indicate 32B\n+\t * records.\n \t */\n-\tuint64_t\tresp_addr;\n-\tuint32_t\tenables;\n+\t#define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_TYPE_MASK \\\n+\t\tUINT32_C(0x3f)\n+\t#define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_TYPE_SFT \\\n+\t\t0\n+\t/* HWRM Asynchronous Event Information */\n+\t#define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_TYPE_HWRM_ASYNC_EVENT \\\n+\t\tUINT32_C(0x2e)\n+\t#define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_TYPE_LAST \\\n+\t\tHWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_TYPE_HWRM_ASYNC_EVENT\n+\t/* Identifiers of events. */\n+\tuint16_t\tevent_id;\n+\t/* Notification of tcp flag action change */\n+\t#define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_EVENT_ID_TCP_FLAG_ACTION_CHANGE \\\n+\t\tUINT32_C(0x3a)\n+\t#define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_EVENT_ID_LAST \\\n+\t\tHWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_EVENT_ID_TCP_FLAG_ACTION_CHANGE\n+\t/* Event specific data */\n+\tuint32_t\tevent_data2;\n+\tuint8_t\topaque_v;\n \t/*\n-\t * This bit must be '1' for the vf_id_valid field to be\n-\t * configured.\n+\t * This value is written by the NIC such that it will be different\n+\t * for each pass through the completion queue. The even passes\n+\t * will write 1. The odd passes will write 0.\n \t */\n-\t#define HWRM_FUNC_RESET_INPUT_ENABLES_VF_ID_VALID UINT32_C(0x1)\n+\t#define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_V \\\n+\t\tUINT32_C(0x1)\n+\t/* opaque is 7 b */\n+\t#define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_OPAQUE_MASK \\\n+\t\tUINT32_C(0xfe)\n+\t#define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_OPAQUE_SFT 1\n+\t/* 8-lsb timestamp from POR (100-msec resolution) */\n+\tuint8_t\ttimestamp_lo;\n+\t/* 16-lsb timestamp from POR (100-msec resolution) */\n+\tuint16_t\ttimestamp_hi;\n+\t/* Event specific data */\n+\tuint32_t\tevent_data1;\n+} __attribute__((packed));\n+\n+/* hwrm_async_event_cmpl_eem_flow_active (size:128b/16B) */\n+struct hwrm_async_event_cmpl_eem_flow_active {\n+\tuint16_t\ttype;\n \t/*\n-\t * The ID of the VF that this PF is trying to reset.\n-\t * Only the parent PF shall be allowed to reset a child VF.\n-\t *\n-\t * A parent PF driver shall use this field only when a specific child VF\n-\t * is requested to be reset.\n+\t * This field indicates the exact type of the completion.\n+\t * By convention, the LSB identifies the length of the\n+\t * record in 16B units. Even values indicate 16B\n+\t * records. Odd values indicate 32B\n+\t * records.\n \t */\n-\tuint16_t\tvf_id;\n-\t/* This value indicates the level of a function reset. */\n-\tuint8_t\tfunc_reset_level;\n+\t#define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_TYPE_MASK \\\n+\t\tUINT32_C(0x3f)\n+\t#define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_TYPE_SFT 0\n+\t/* HWRM Asynchronous Event Information */\n+\t#define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_TYPE_HWRM_ASYNC_EVENT \\\n+\t\tUINT32_C(0x2e)\n+\t#define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_TYPE_LAST \\\n+\t\tHWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_TYPE_HWRM_ASYNC_EVENT\n+\t/* Identifiers of events. */\n+\tuint16_t\tevent_id;\n+\t/* Notification of an active eem flow */\n+\t#define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_ID_EEM_FLOW_ACTIVE \\\n+\t\tUINT32_C(0x3b)\n+\t#define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_ID_LAST \\\n+\t\tHWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_ID_EEM_FLOW_ACTIVE\n+\t/* Event specific data */\n+\tuint32_t\tevent_data2;\n+\t/* Indicates the 2nd global id this event occured on. */\n+\t#define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_GLOBAL_ID_2_MASK \\\n+\t\tUINT32_C(0x3fffffff)\n+\t#define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_GLOBAL_ID_2_SFT \\\n+\t\t0\n \t/*\n-\t * Reset the caller function and its children VFs (if any). If no\n-\t * children functions exist, then reset the caller function only.\n-\t */\n-\t#define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETALL \\\n-\t\tUINT32_C(0x0)\n-\t/* Reset the caller function only */\n-\t#define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETME \\\n-\t\tUINT32_C(0x1)\n+\t * Indicates flow direction of the flow identified by\n+\t * the global_id_2.\n+\t */\n+\t#define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_FLOW_DIRECTION \\\n+\t\tUINT32_C(0x40000000)\n+\t/* If this bit is set to 0, then it indicates that this rx flow. */\n+\t#define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_FLOW_DIRECTION_RX \\\n+\t\t(UINT32_C(0x0) << 30)\n+\t/* If this bit is set to 1, then it indicates that this tx flow. */\n+\t#define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_FLOW_DIRECTION_TX \\\n+\t\t(UINT32_C(0x1) << 30)\n+\t#define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_FLOW_DIRECTION_LAST \\\n+\t\tHWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_FLOW_DIRECTION_TX\n+\tuint8_t\topaque_v;\n \t/*\n-\t * Reset all children VFs of the caller function driver if the\n-\t * caller is a PF driver.\n-\t * It is an error to specify this level by a VF driver.\n-\t * It is an error to specify this level by a PF driver with\n-\t * no children VFs.\n+\t * This value is written by the NIC such that it will be different\n+\t * for each pass through the completion queue. The even passes\n+\t * will write 1. The odd passes will write 0.\n \t */\n-\t#define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETCHILDREN \\\n-\t\tUINT32_C(0x2)\n-\t/*\n-\t * Reset a specific VF of the caller function driver if the caller\n-\t * is the parent PF driver.\n-\t * It is an error to specify this level by a VF driver.\n-\t * It is an error to specify this level by a PF driver that is not\n-\t * the parent of the VF that is being requested to reset.\n+\t#define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_V UINT32_C(0x1)\n+\t/* opaque is 7 b */\n+\t#define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_OPAQUE_MASK \\\n+\t\tUINT32_C(0xfe)\n+\t#define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_OPAQUE_SFT 1\n+\t/* 8-lsb timestamp from POR (100-msec resolution) */\n+\tuint8_t\ttimestamp_lo;\n+\t/* 16-lsb timestamp from POR (100-msec resolution) */\n+\tuint16_t\ttimestamp_hi;\n+\t/* Event specific data */\n+\tuint32_t\tevent_data1;\n+\t/* Indicates the 1st global id this event occured on. */\n+\t#define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_GLOBAL_ID_1_MASK \\\n+\t\tUINT32_C(0x3fffffff)\n+\t#define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_GLOBAL_ID_1_SFT \\\n+\t\t0\n+\t/*\n+\t * Indicates flow direction of the flow identified by the\n+\t * global_id_1.\n+\t */\n+\t#define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_FLOW_DIRECTION \\\n+\t\tUINT32_C(0x40000000)\n+\t/* If this bit is set to 0, then it indicates that this is rx flow. */\n+\t#define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_FLOW_DIRECTION_RX \\\n+\t\t(UINT32_C(0x0) << 30)\n+\t/* If this bit is set to 1, then it indicates that this is tx flow. */\n+\t#define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_FLOW_DIRECTION_TX \\\n+\t\t(UINT32_C(0x1) << 30)\n+\t#define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_FLOW_DIRECTION_LAST \\\n+\t\tHWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_FLOW_DIRECTION_TX\n+\t/*\n+\t * Indicates EEM flow aging mode this event occured on. If\n+\t * this bit is set to 0, the event_data1 is the EEM global\n+\t * ID. If this bit is set to 1, the event_data1 is the number\n+\t * of global ID in the context memory.\n+\t */\n+\t#define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_MODE \\\n+\t\tUINT32_C(0x80000000)\n+\t/* EEM flow aging mode 0. */\n+\t#define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_MODE_0 \\\n+\t\t(UINT32_C(0x0) << 31)\n+\t/* EEM flow aging mode 1. */\n+\t#define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_MODE_1 \\\n+\t\t(UINT32_C(0x1) << 31)\n+\t#define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_MODE_LAST \\\n+\t\tHWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_MODE_1\n+} __attribute__((packed));\n+\n+/* hwrm_async_event_cmpl_eem_cfg_change (size:128b/16B) */\n+struct hwrm_async_event_cmpl_eem_cfg_change {\n+\tuint16_t\ttype;\n+\t/*\n+\t * This field indicates the exact type of the completion.\n+\t * By convention, the LSB identifies the length of the\n+\t * record in 16B units. Even values indicate 16B\n+\t * records. Odd values indicate 32B\n+\t * records.\n+\t */\n+\t#define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_TYPE_MASK \\\n+\t\tUINT32_C(0x3f)\n+\t#define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_TYPE_SFT 0\n+\t/* HWRM Asynchronous Event Information */\n+\t#define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT \\\n+\t\tUINT32_C(0x2e)\n+\t#define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_TYPE_LAST \\\n+\t\tHWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT\n+\t/* Identifiers of events. */\n+\tuint16_t\tevent_id;\n+\t/* Notification of EEM configuration change */\n+\t#define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_EVENT_ID_EEM_CFG_CHANGE \\\n+\t\tUINT32_C(0x3c)\n+\t#define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_EVENT_ID_LAST \\\n+\t\tHWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_EVENT_ID_EEM_CFG_CHANGE\n+\t/* Event specific data */\n+\tuint32_t\tevent_data2;\n+\tuint8_t\topaque_v;\n+\t/*\n+\t * This value is written by the NIC such that it will be different\n+\t * for each pass through the completion queue. The even passes\n+\t * will write 1. The odd passes will write 0.\n+\t */\n+\t#define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_V UINT32_C(0x1)\n+\t/* opaque is 7 b */\n+\t#define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_OPAQUE_MASK UINT32_C(0xfe)\n+\t#define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_OPAQUE_SFT 1\n+\t/* 8-lsb timestamp from POR (100-msec resolution) */\n+\tuint8_t\ttimestamp_lo;\n+\t/* 16-lsb timestamp from POR (100-msec resolution) */\n+\tuint16_t\ttimestamp_hi;\n+\t/* Event specific data */\n+\tuint32_t\tevent_data1;\n+\t/*\n+\t * Value of 1 to indicate EEM TX configuration is enabled. Value of\n+\t * 0 to indicate the EEM TX configuration is disabled.\n+\t */\n+\t#define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_EVENT_DATA1_EEM_TX_ENABLE \\\n+\t\tUINT32_C(0x1)\n+\t/*\n+\t * Value of 1 to indicate EEM RX configuration is enabled. Value of 0\n+\t * to indicate the EEM RX configuration is disabled.\n+\t */\n+\t#define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_EVENT_DATA1_EEM_RX_ENABLE \\\n+\t\tUINT32_C(0x2)\n+} __attribute__((packed));\n+\n+/* hwrm_async_event_cmpl_fw_trace_msg (size:128b/16B) */\n+struct hwrm_async_event_cmpl_fw_trace_msg {\n+\tuint16_t\ttype;\n+\t/*\n+\t * This field indicates the exact type of the completion.\n+\t * By convention, the LSB identifies the length of the\n+\t * record in 16B units. Even values indicate 16B\n+\t * records. Odd values indicate 32B\n+\t * records.\n+\t */\n+\t#define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TYPE_MASK \\\n+\t\tUINT32_C(0x3f)\n+\t#define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TYPE_SFT 0\n+\t/* HWRM Asynchronous Event Information */\n+\t#define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TYPE_HWRM_ASYNC_EVENT \\\n+\t\tUINT32_C(0x2e)\n+\t#define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TYPE_LAST \\\n+\t\tHWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TYPE_HWRM_ASYNC_EVENT\n+\t/* Identifiers of events. */\n+\tuint16_t\tevent_id;\n+\t/* Firmware trace log message */\n+\t#define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_ID_FW_TRACE_MSG \\\n+\t\tUINT32_C(0xfe)\n+\t#define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_ID_LAST \\\n+\t\tHWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_ID_FW_TRACE_MSG\n+\t/* Trace byte 0 to 3 */\n+\tuint32_t\tevent_data2;\n+\t/* Trace byte0 */\n+\t#define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE0_MASK \\\n+\t\tUINT32_C(0xff)\n+\t#define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE0_SFT 0\n+\t/* Trace byte1 */\n+\t#define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE1_MASK \\\n+\t\tUINT32_C(0xff00)\n+\t#define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE1_SFT 8\n+\t/* Trace byte2 */\n+\t#define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE2_MASK \\\n+\t\tUINT32_C(0xff0000)\n+\t#define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE2_SFT 16\n+\t/* Trace byte3 */\n+\t#define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE3_MASK \\\n+\t\tUINT32_C(0xff000000)\n+\t#define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE3_SFT 24\n+\tuint8_t\topaque_v;\n+\t/*\n+\t * This value is written by the NIC such that it will be different\n+\t * for each pass through the completion queue. The even passes\n+\t * will write 1. The odd passes will write 0.\n+\t */\n+\t#define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_V UINT32_C(0x1)\n+\t/* opaque is 7 b */\n+\t#define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_OPAQUE_MASK UINT32_C(0xfe)\n+\t#define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_OPAQUE_SFT 1\n+\t/* Trace flags */\n+\tuint8_t\ttimestamp_lo;\n+\t/* Indicates if the string is partial or complete. */\n+\t#define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_STRING \\\n+\t\tUINT32_C(0x1)\n+\t/* Complete string */\n+\t#define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_STRING_COMPLETE \\\n+\t\tUINT32_C(0x0)\n+\t/* Partial string */\n+\t#define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_STRING_PARTIAL \\\n+\t\tUINT32_C(0x1)\n+\t#define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_STRING_LAST \\\n+\t\tHWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_STRING_PARTIAL\n+\t/* Indicates the firmware that sent the trace message. */\n+\t#define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_FIRMWARE \\\n+\t\tUINT32_C(0x2)\n+\t/* Primary firmware */\n+\t#define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_FIRMWARE_PRIMARY \\\n+\t\t(UINT32_C(0x0) << 1)\n+\t/* Secondary firmware */\n+\t#define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_FIRMWARE_SECONDARY \\\n+\t\t(UINT32_C(0x1) << 1)\n+\t#define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_FIRMWARE_LAST \\\n+\t\tHWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_FIRMWARE_SECONDARY\n+\t/* Trace byte 4 to 5 */\n+\tuint16_t\ttimestamp_hi;\n+\t/* Trace byte4 */\n+\t#define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_HI_BYTE4_MASK \\\n+\t\tUINT32_C(0xff)\n+\t#define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_HI_BYTE4_SFT 0\n+\t/* Trace byte5 */\n+\t#define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_HI_BYTE5_MASK \\\n+\t\tUINT32_C(0xff00)\n+\t#define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_HI_BYTE5_SFT 8\n+\t/* Trace byte 6 to 9 */\n+\tuint32_t\tevent_data1;\n+\t/* Trace byte6 */\n+\t#define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE6_MASK \\\n+\t\tUINT32_C(0xff)\n+\t#define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE6_SFT 0\n+\t/* Trace byte7 */\n+\t#define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE7_MASK \\\n+\t\tUINT32_C(0xff00)\n+\t#define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE7_SFT 8\n+\t/* Trace byte8 */\n+\t#define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE8_MASK \\\n+\t\tUINT32_C(0xff0000)\n+\t#define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE8_SFT 16\n+\t/* Trace byte9 */\n+\t#define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE9_MASK \\\n+\t\tUINT32_C(0xff000000)\n+\t#define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE9_SFT 24\n+} __attribute__((packed));\n+\n+/* hwrm_async_event_cmpl_hwrm_error (size:128b/16B) */\n+struct hwrm_async_event_cmpl_hwrm_error {\n+\tuint16_t\ttype;\n+\t/*\n+\t * This field indicates the exact type of the completion.\n+\t * By convention, the LSB identifies the length of the\n+\t * record in 16B units. Even values indicate 16B\n+\t * records. Odd values indicate 32B\n+\t * records.\n+\t */\n+\t#define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_MASK \\\n+\t\tUINT32_C(0x3f)\n+\t#define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_SFT 0\n+\t/* HWRM Asynchronous Event Information */\n+\t#define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_HWRM_ASYNC_EVENT \\\n+\t\tUINT32_C(0x2e)\n+\t#define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_LAST \\\n+\t\tHWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_HWRM_ASYNC_EVENT\n+\t/* Identifiers of events. */\n+\tuint16_t\tevent_id;\n+\t/* HWRM Error */\n+\t#define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_HWRM_ERROR \\\n+\t\tUINT32_C(0xff)\n+\t#define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_LAST \\\n+\t\tHWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_HWRM_ERROR\n+\t/* Event specific data */\n+\tuint32_t\tevent_data2;\n+\t/* Severity of HWRM Error */\n+\t#define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_MASK \\\n+\t\tUINT32_C(0xff)\n+\t#define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_SFT 0\n+\t/* Warning */\n+\t#define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_WARNING \\\n+\t\tUINT32_C(0x0)\n+\t/* Non-fatal Error */\n+\t#define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_NONFATAL \\\n+\t\tUINT32_C(0x1)\n+\t/* Fatal Error */\n+\t#define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_FATAL \\\n+\t\tUINT32_C(0x2)\n+\t#define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_LAST \\\n+\t\tHWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_FATAL\n+\tuint8_t\topaque_v;\n+\t/*\n+\t * This value is written by the NIC such that it will be different\n+\t * for each pass through the completion queue. The even passes\n+\t * will write 1. The odd passes will write 0.\n+\t */\n+\t#define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_V UINT32_C(0x1)\n+\t/* opaque is 7 b */\n+\t#define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_OPAQUE_MASK UINT32_C(0xfe)\n+\t#define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_OPAQUE_SFT 1\n+\t/* 8-lsb timestamp from POR (100-msec resolution) */\n+\tuint8_t\ttimestamp_lo;\n+\t/* 16-lsb timestamp from POR (100-msec resolution) */\n+\tuint16_t\ttimestamp_hi;\n+\t/* Event specific data */\n+\tuint32_t\tevent_data1;\n+\t/* Time stamp for error event */\n+\t#define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA1_TIMESTAMP \\\n+\t\tUINT32_C(0x1)\n+} __attribute__((packed));\n+\n+/*******************\n+ * hwrm_func_reset *\n+ *******************/\n+\n+\n+/* hwrm_func_reset_input (size:192b/24B) */\n+struct hwrm_func_reset_input {\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/*\n+\t * The completion ring to send the completion event on. This should\n+\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n+\t */\n+\tuint16_t\tcmpl_ring;\n+\t/*\n+\t * The sequence ID is used by the driver for tracking multiple\n+\t * commands. This ID is treated as opaque data by the firmware and\n+\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n+\t */\n+\tuint16_t\tseq_id;\n+\t/*\n+\t * The target ID of the command:\n+\t * * 0x0-0xFFF8 - The function ID\n+\t * * 0xFFF8-0xFFFE - Reserved for internal processors\n+\t * * 0xFFFF - HWRM\n+\t */\n+\tuint16_t\ttarget_id;\n+\t/*\n+\t * A physical address pointer pointing to a host buffer that the\n+\t * command's response data will be written. This can be either a host\n+\t * physical address (HPA) or a guest physical address (GPA) and must\n+\t * point to a physically contiguous block of memory.\n+\t */\n+\tuint64_t\tresp_addr;\n+\tuint32_t\tenables;\n+\t/*\n+\t * This bit must be '1' for the vf_id_valid field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_FUNC_RESET_INPUT_ENABLES_VF_ID_VALID UINT32_C(0x1)\n+\t/*\n+\t * The ID of the VF that this PF is trying to reset.\n+\t * Only the parent PF shall be allowed to reset a child VF.\n+\t *\n+\t * A parent PF driver shall use this field only when a specific child VF\n+\t * is requested to be reset.\n+\t */\n+\tuint16_t\tvf_id;\n+\t/* This value indicates the level of a function reset. */\n+\tuint8_t\tfunc_reset_level;\n+\t/*\n+\t * Reset the caller function and its children VFs (if any). If no\n+\t * children functions exist, then reset the caller function only.\n+\t */\n+\t#define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETALL \\\n+\t\tUINT32_C(0x0)\n+\t/* Reset the caller function only */\n+\t#define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETME \\\n+\t\tUINT32_C(0x1)\n+\t/*\n+\t * Reset all children VFs of the caller function driver if the\n+\t * caller is a PF driver.\n+\t * It is an error to specify this level by a VF driver.\n+\t * It is an error to specify this level by a PF driver with\n+\t * no children VFs.\n+\t */\n+\t#define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETCHILDREN \\\n+\t\tUINT32_C(0x2)\n+\t/*\n+\t * Reset a specific VF of the caller function driver if the caller\n+\t * is the parent PF driver.\n+\t * It is an error to specify this level by a VF driver.\n+\t * It is an error to specify this level by a PF driver that is not\n+\t * the parent of the VF that is being requested to reset.\n \t */\n \t#define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETVF \\\n \t\tUINT32_C(0x3)\n@@ -6066,6 +6657,12 @@ struct hwrm_func_qcaps_output {\n \t */\n \t#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_HOT_RESET_CAPABLE \\\n \t\tUINT32_C(0x400000)\n+\t/*\n+\t * This flag will be set to 1 by the FW if FW supports adapter error\n+\t * recovery.\n+\t */\n+\t#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERROR_RECOVERY_CAPABLE \\\n+\t\tUINT32_C(0x800000)\n \t/*\n \t * This value is current MAC address configured for this\n \t * function. A value of 00-00-00-00-00-00 indicates no\n@@ -6813,8 +7410,7 @@ struct hwrm_func_cfg_input {\n \t * resident HWRM clients, only the parent PF driver shall be allowed\n \t * to initiate this change on one of its children VFs. If this bit is\n \t * set to 1, then the VF that is being configured is requested to be\n-\t * trusted. If this bit is set to 0, then the VF that is being configured\n-\t * is requested to be not trusted.\n+\t * trusted.\n \t */\n \t#define HWRM_FUNC_CFG_INPUT_FLAGS_TRUSTED_VF_ENABLE \\\n \t\tUINT32_C(0x200000)\n@@ -6825,6 +7421,25 @@ struct hwrm_func_cfg_input {\n \t */\n \t#define HWRM_FUNC_CFG_INPUT_FLAGS_DYNAMIC_TX_RING_ALLOC \\\n \t\tUINT32_C(0x400000)\n+\t/*\n+\t * This bit requests that the firmware test to see if all the assets\n+\t * requested in this command (i.e. number of NQ rings) are available.\n+\t * The firmware will return an error if the requested assets are\n+\t * not available. The firwmare will NOT reserve the assets if they\n+\t * are available.\n+\t */\n+\t#define HWRM_FUNC_CFG_INPUT_FLAGS_NQ_ASSETS_TEST \\\n+\t\tUINT32_C(0x800000)\n+\t/*\n+\t * This configuration change can be initiated by a PF driver. This\n+\t * configuration request shall be targeted to a VF. From local host\n+\t * resident HWRM clients, only the parent PF driver shall be allowed\n+\t * to initiate this change on one of its children VFs. If this bit is\n+\t * set to 1, then the VF that is being configured is requested to be\n+\t * untrusted.\n+\t */\n+\t#define HWRM_FUNC_CFG_INPUT_FLAGS_TRUSTED_VF_DISABLE \\\n+\t\tUINT32_C(0x1000000)\n \tuint32_t\tenables;\n \t/*\n \t * This bit must be '1' for the mtu field to be\n@@ -7593,6 +8208,19 @@ struct hwrm_func_drv_rgtr_input {\n \t */\n \t#define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_HOT_RESET_SUPPORT \\\n \t\tUINT32_C(0x10)\n+\t/*\n+\t * When this bit is 1, the function is indicating the support of the\n+\t * error recovery capability. Error recovery support will be used by\n+\t * firmware only if all the driver instances support error recovery\n+\t * process. By setting this bit, driver is indicating support for\n+\t * corresponding async event completion message. These will be\n+\t * delivered to the driver even if they did not register for it.\n+\t * If supported, after receiving reset notify async event with fatal\n+\t * flag set in event data1, then all the drivers have to tear down\n+\t * their resources without sending any HWRM commands to FW.\n+\t */\n+\t#define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_ERROR_RECOVERY_SUPPORT \\\n+\t\tUINT32_C(0x20)\n \tuint32_t\tenables;\n \t/*\n \t * This bit must be '1' for the os_type field to be\n@@ -10270,17 +10898,384 @@ struct hwrm_func_backing_store_qcfg_output {\n \tuint8_t\tunused_1[7];\n \t/*\n \t * This field is used in Output records to indicate that the output\n-\t * is completely written to RAM. This field should be read as '1'\n+\t * is completely written to RAM. This field should be read as 1\n \t * to indicate that the output has been completely written.\n-\t * When writing a command completion or response to an internal processor,\n-\t * the order of writes has to be such that this field is written last.\n+\t * When writing a command completion or response to an internal\n+\t * processor, the order of writes has to be such that this field\n+\t * is written last.\n \t */\n \tuint8_t\tvalid;\n } __attribute__((packed));\n \n-/***********************\n- * hwrm_func_vlan_qcfg *\n- ***********************/\n+/****************************\n+ * hwrm_error_recovery_qcfg *\n+ ****************************/\n+\n+\n+/* hwrm_error_recovery_qcfg_input (size:192b/24B) */\n+struct hwrm_error_recovery_qcfg_input {\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/*\n+\t * The completion ring to send the completion event on. This should\n+\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n+\t */\n+\tuint16_t\tcmpl_ring;\n+\t/*\n+\t * The sequence ID is used by the driver for tracking multiple\n+\t * commands. This ID is treated as opaque data by the firmware and\n+\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n+\t */\n+\tuint16_t\tseq_id;\n+\t/*\n+\t * The target ID of the command:\n+\t * * 0x0-0xFFF8 - The function ID\n+\t * * 0xFFF8-0xFFFE - Reserved for internal processors\n+\t * * 0xFFFF - HWRM\n+\t */\n+\tuint16_t\ttarget_id;\n+\t/*\n+\t * A physical address pointer pointing to a host buffer that the\n+\t * command's response data will be written. This can be either a host\n+\t * physical address (HPA) or a guest physical address (GPA) and must\n+\t * point to a physically contiguous block of memory.\n+\t */\n+\tuint64_t\tresp_addr;\n+\tuint8_t\tunused_0[8];\n+} __attribute__((packed));\n+\n+/* hwrm_error_recovery_qcfg_output (size:1664b/208B) */\n+struct hwrm_error_recovery_qcfg_output {\n+\t/* The specific error status for the command. */\n+\tuint16_t\terror_code;\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/* The sequence ID from the original command. */\n+\tuint16_t\tseq_id;\n+\t/* The length of the response data in number of bytes. */\n+\tuint16_t\tresp_len;\n+\tuint32_t\tflags;\n+\t/*\n+\t * When this flag is set to 1, error recovery will be initiated\n+\t * through master function driver.\n+\t */\n+\t#define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_HOST UINT32_C(0x1)\n+\t/*\n+\t * When this flag is set to 1, error recovery will be performed\n+\t * through Co processor.\n+\t */\n+\t#define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_CO_CPU UINT32_C(0x2)\n+\t/*\n+\t * Driver Polling frequency. This value is in units of 100msec.\n+\t * Typical value would be 10 to indicate 1sec.\n+\t * Drivers can poll FW health status, Heartbeat, reset_counter with\n+\t * this frequency.\n+\t */\n+\tuint32_t\tdriver_polling_freq;\n+\t/*\n+\t * This value is in units of 100msec.\n+\t * Typical value would be 30 to indicate 3sec.\n+\t * Master function wait period from detecting a fatal error to\n+\t * initiating reset. In this time period Master PF expects every\n+\t * active driver will detect fatal error.\n+\t */\n+\tuint32_t\tmaster_func_wait_period;\n+\t/*\n+\t * This value is in units of 100msec.\n+\t * Typical value would be 50 to indicate 5sec.\n+\t * Normal function wait period from fatal error detection to\n+\t * polling FW health status. In this time period, drivers should not\n+\t * do any PCIe MMIO transaction and should not send any HWRM commands.\n+\t */\n+\tuint32_t\tnormal_func_wait_period;\n+\t/*\n+\t * This value is in units of 100msec.\n+\t * Typical value would be 20 to indicate 2sec.\n+\t * This field indicates that, master function wait period after chip\n+\t * reset. After this time, master function should reinitialize with\n+\t * FW.\n+\t */\n+\tuint32_t\tmaster_func_wait_period_after_reset;\n+\t/*\n+\t * This value is in units of 100msec.\n+\t * Typical value would be 60 to indicate 6sec.\n+\t * This field is applicable to both master and normal functions.\n+\t * Even after chip reset, if FW status not changed to ready,\n+\t * then all the functions can poll for this much time and bailout.\n+\t */\n+\tuint32_t\tmax_bailout_time_after_reset;\n+\t/*\n+\t * FW health status register.\n+\t * Lower 2 bits indicates address space location and upper 30 bits\n+\t * indicates upper 30bits of the register address.\n+\t * A value of 0xFFFF-FFFF indicates this register does not exist.\n+\t */\n+\tuint32_t\tfw_health_status_reg;\n+\t/* Lower 2 bits indicates address space location. */\n+\t#define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_MASK \\\n+\t\tUINT32_C(0x3)\n+\t#define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_SFT \\\n+\t\t0\n+\t/*\n+\t * If value is 0, this register is located in PCIe config space.\n+\t * Drivers have to map appropriate window to access this\n+\t * register.\n+\t */\n+\t#define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_PCIE_CFG \\\n+\t\tUINT32_C(0x0)\n+\t/*\n+\t * If value is 1, this register is located in GRC address space.\n+\t * Drivers have to map appropriate window to access this\n+\t * register.\n+\t */\n+\t#define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_GRC \\\n+\t\tUINT32_C(0x1)\n+\t/*\n+\t * If value is 2, this register is located in first BAR address\n+\t * space. Drivers have to map appropriate window to access this\n+\t * register.\n+\t */\n+\t#define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR0 \\\n+\t\tUINT32_C(0x2)\n+\t/*\n+\t * If value is 3, this register is located in second BAR address\n+\t * space. Drivers have to map appropriate window to access this\n+\t * Drivers have to map appropriate window to access this\n+\t * register.\n+\t */\n+\t#define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR1 \\\n+\t\tUINT32_C(0x3)\n+\t#define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_LAST \\\n+\t\tHWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR1\n+\t/* Upper 30bits of the register address. */\n+\t#define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_MASK \\\n+\t\tUINT32_C(0xfffffffc)\n+\t#define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SFT \\\n+\t\t2\n+\t/*\n+\t * FW HeartBeat register.\n+\t * Lower 2 bits indicates address space location and upper 30 bits\n+\t * indicates actual address.\n+\t * A value of 0xFFFF-FFFF indicates this register does not exist.\n+\t */\n+\tuint32_t\tfw_heartbeat_reg;\n+\t/* Lower 2 bits indicates address space location. */\n+\t#define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_MASK \\\n+\t\tUINT32_C(0x3)\n+\t#define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_SFT \\\n+\t\t0\n+\t/*\n+\t * If value is 0, this register is located in PCIe config space.\n+\t * Drivers have to map appropriate window to access this\n+\t * register.\n+\t */\n+\t#define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_PCIE_CFG \\\n+\t\tUINT32_C(0x0)\n+\t/*\n+\t * If value is 1, this register is located in GRC address space.\n+\t * Drivers have to map appropriate window to access this\n+\t * register.\n+\t */\n+\t#define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_GRC \\\n+\t\tUINT32_C(0x1)\n+\t/*\n+\t * If value is 2, this register is located in first BAR address\n+\t * space. Drivers have to map appropriate window to access this\n+\t * register.\n+\t */\n+\t#define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_BAR0 \\\n+\t\tUINT32_C(0x2)\n+\t/*\n+\t * If value is 3, this register is located in second BAR address\n+\t * space. Drivers have to map appropriate window to access this\n+\t * register.\n+\t */\n+\t#define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_BAR1 \\\n+\t\tUINT32_C(0x3)\n+\t#define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_LAST \\\n+\t\tHWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_BAR1\n+\t/* Upper 30bits of the register address. */\n+\t#define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_MASK \\\n+\t\tUINT32_C(0xfffffffc)\n+\t#define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SFT \\\n+\t\t2\n+\t/*\n+\t * FW reset counter.\n+\t * Lower 2 bits indicates address space location and upper 30 bits\n+\t * indicates actual address.\n+\t * A value of 0xFFFF-FFFF indicates this register does not exist.\n+\t */\n+\tuint32_t\tfw_reset_cnt_reg;\n+\t/* Lower 2 bits indicates address space location. */\n+\t#define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_MASK \\\n+\t\tUINT32_C(0x3)\n+\t#define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_SFT \\\n+\t\t0\n+\t/*\n+\t * If value is 0, this register is located in PCIe config space.\n+\t * Drivers have to map appropriate window to access this\n+\t * register.\n+\t */\n+\t#define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_PCIE_CFG \\\n+\t\tUINT32_C(0x0)\n+\t/*\n+\t * If value is 1, this register is located in GRC address space.\n+\t * Drivers have to map appropriate window to access this\n+\t * register.\n+\t */\n+\t#define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_GRC \\\n+\t\tUINT32_C(0x1)\n+\t/*\n+\t * If value is 2, this register is located in first BAR address\n+\t * space. Drivers have to map appropriate window to access this\n+\t * register.\n+\t */\n+\t#define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_BAR0 \\\n+\t\tUINT32_C(0x2)\n+\t/*\n+\t * If value is 3, this register is located in second BAR address\n+\t * space. Drivers have to map appropriate window to access this\n+\t * register.\n+\t */\n+\t#define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_BAR1 \\\n+\t\tUINT32_C(0x3)\n+\t#define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_LAST \\\n+\t\tHWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_BAR1\n+\t/* Upper 30bits of the register address. */\n+\t#define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_MASK \\\n+\t\tUINT32_C(0xfffffffc)\n+\t#define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SFT \\\n+\t\t2\n+\t/*\n+\t * Reset Inprogress Register address for PFs.\n+\t * Lower 2 bits indicates address space location and upper 30 bits\n+\t * indicates actual address.\n+\t * A value of 0xFFFF-FFFF indicates this register does not exist.\n+\t */\n+\tuint32_t\treset_inprogress_reg;\n+\t/* Lower 2 bits indicates address space location. */\n+\t#define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_MASK \\\n+\t\tUINT32_C(0x3)\n+\t#define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_SFT \\\n+\t\t0\n+\t/*\n+\t * If value is 0, this register is located in PCIe config space.\n+\t * Drivers have to map appropriate window to access this\n+\t * register.\n+\t */\n+\t#define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_PCIE_CFG \\\n+\t\tUINT32_C(0x0)\n+\t/*\n+\t * If value is 1, this register is located in GRC address space.\n+\t * Drivers have to map appropriate window to access this\n+\t * register.\n+\t */\n+\t#define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_GRC \\\n+\t\tUINT32_C(0x1)\n+\t/*\n+\t * If value is 2, this register is located in first BAR address\n+\t * space. Drivers have to map appropriate window to access this\n+\t * register.\n+\t */\n+\t#define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_BAR0 \\\n+\t\tUINT32_C(0x2)\n+\t/*\n+\t * If value is 3, this register is located in second BAR address\n+\t * space. Drivers have to map appropriate window to access this\n+\t * register.\n+\t */\n+\t#define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_BAR1 \\\n+\t\tUINT32_C(0x3)\n+\t#define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_LAST \\\n+\t\tHWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_BAR1\n+\t/* Upper 30bits of the register address. */\n+\t#define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_MASK \\\n+\t\tUINT32_C(0xfffffffc)\n+\t#define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SFT \\\n+\t\t2\n+\t/* This field indicates the mask value for reset_inprogress_reg. */\n+\tuint32_t\treset_inprogress_reg_mask;\n+\tuint8_t\tunused_0[3];\n+\t/*\n+\t * Array of registers and value count to reset the Chip\n+\t * Each array count has reset_reg, reset_reg_val, delay_after_reset\n+\t * in TLV format. Depending upon Chip type, number of reset registers\n+\t * will vary. Drivers have to write reset_reg_val in the reset_reg\n+\t * location in the same sequence in order to recover from a fatal\n+\t * error.\n+\t */\n+\tuint8_t\treg_array_cnt;\n+\t/*\n+\t * Reset register.\n+\t * Lower 2 bits indicates address space location and upper 30 bits\n+\t * indicates actual address.\n+\t * A value of 0xFFFF-FFFF indicates this register does not exist.\n+\t */\n+\tuint32_t\treset_reg[16];\n+\t/* Lower 2 bits indicates address space location. */\n+\t#define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_MASK \\\n+\t\tUINT32_C(0x3)\n+\t#define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_SFT 0\n+\t/*\n+\t * If value is 0, this register is located in PCIe config space.\n+\t * Drivers have to map appropriate window to access this\n+\t * register.\n+\t */\n+\t#define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_PCIE_CFG \\\n+\t\tUINT32_C(0x0)\n+\t/*\n+\t * If value is 1, this register is located in GRC address space.\n+\t * Drivers have to map appropriate window to access this\n+\t * register.\n+\t */\n+\t#define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_GRC \\\n+\t\tUINT32_C(0x1)\n+\t/*\n+\t * If value is 2, this register is located in first BAR address\n+\t * space. Drivers have to map appropriate window to access this\n+\t * register.\n+\t */\n+\t#define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_BAR0 \\\n+\t\tUINT32_C(0x2)\n+\t/*\n+\t * If value is 3, this register is located in second BAR address\n+\t * space. Drivers have to map appropriate window to access this\n+\t * register.\n+\t */\n+\t#define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_BAR1 \\\n+\t\tUINT32_C(0x3)\n+\t#define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_LAST \\\n+\t\tHWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_BAR1\n+\t/* Upper 30bits of the register address. */\n+\t#define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_MASK \\\n+\t\tUINT32_C(0xfffffffc)\n+\t#define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SFT 2\n+\t/* Value to be written in reset_reg to reset the controller. */\n+\tuint32_t\treset_reg_val[16];\n+\t/*\n+\t * This value is in units of 1msec.\n+\t * Typical value would be 10 to indicate 10msec.\n+\t * Some of the operations like Core reset require delay before\n+\t * accessing PCIE MMIO register space.\n+\t * If this value is non-zero, drivers have to wait for\n+\t * this much time after writing reset_reg_val in reset_reg.\n+\t */\n+\tuint8_t\tdelay_after_reset[16];\n+\tuint8_t\tunused_1[7];\n+\t/*\n+\t * This field is used in Output records to indicate that the output\n+\t * is completely written to RAM. This field should be read as '1'\n+\t * to indicate that the output has been completely written.\n+\t * When writing a command completion or response to an internal\n+\t * processor, the order of writes has to be such that this field\n+\t * is written last.\n+\t */\n+\tuint8_t\tvalid;\n+} __attribute__((packed));\n+\n+/***********************\n+ * hwrm_func_vlan_qcfg *\n+ ***********************/\n \n \n /* hwrm_func_vlan_qcfg_input (size:192b/24B) */\n@@ -10894,6 +11889,12 @@ struct hwrm_func_drv_if_change_output {\n \t */\n \t#define HWRM_FUNC_DRV_IF_CHANGE_OUTPUT_FLAGS_RESC_CHANGE \\\n \t\tUINT32_C(0x1)\n+\t/*\n+\t * When this bit is '1', it indicates that the firmware got changed / reset.\n+\t * The driver should do complete re-initialization when that bit is set.\n+\t */\n+\t#define HWRM_FUNC_DRV_IF_CHANGE_OUTPUT_FLAGS_HOT_FW_RESET_DONE \\\n+\t\tUINT32_C(0x2)\n \tuint8_t\tunused_0[3];\n \t/*\n \t * This field is used in Output records to indicate that the output\n@@ -14166,6 +15167,9 @@ struct hwrm_port_phy_qcaps_output {\n \t/* 10Mb link speed (Full-duplex) */\n \t#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_10MB \\\n \t\tUINT32_C(0x2000)\n+\t/* 200Gb link speed */\n+\t#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_200GB \\\n+\t\tUINT32_C(0x4000)\n \t/*\n \t * This is a bit mask to indicate what speeds are supported\n \t * for autonegotiation on this link.\n@@ -14215,6 +15219,9 @@ struct hwrm_port_phy_qcaps_output {\n \t/* 10Mb link speed (Full-duplex) */\n \t#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_10MB \\\n \t\tUINT32_C(0x2000)\n+\t/* 200Gb link speed */\n+\t#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_200GB \\\n+\t\tUINT32_C(0x4000)\n \t/*\n \t * This is a bit mask to indicate what speeds are supported\n \t * for EEE on this link.\n@@ -14281,13 +15288,13 @@ struct hwrm_port_phy_qcaps_output {\n \t#define HWRM_PORT_PHY_QCAPS_OUTPUT_VALID_SFT 24\n } __attribute__((packed));\n \n-/*********************\n- * hwrm_port_led_cfg *\n- *********************/\n+/****************************\n+ * hwrm_port_phy_mdio_write *\n+ ****************************/\n \n \n-/* hwrm_port_led_cfg_input (size:512b/64B) */\n-struct hwrm_port_led_cfg_input {\n+/* hwrm_port_phy_mdio_write_input (size:320b/40B) */\n+struct hwrm_port_phy_mdio_write_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n \t/*\n@@ -14315,46 +15322,198 @@ struct hwrm_port_led_cfg_input {\n \t * point to a physically contiguous block of memory.\n \t */\n \tuint64_t\tresp_addr;\n-\tuint32_t\tenables;\n+\t/* Reserved for future use. */\n+\tuint32_t\tunused_0[2];\n+\t/* Port ID of port. */\n+\tuint16_t\tport_id;\n+\t/* If phy_address is 0xFF, port_id will be used to derive phy_addr. */\n+\tuint8_t\tphy_addr;\n+\t/* 8-bit device address. */\n+\tuint8_t\tdev_addr;\n+\t/* 16-bit register address. */\n+\tuint16_t\treg_addr;\n+\t/* 16-bit register data. */\n+\tuint16_t\treg_data;\n+\t/*\n+\t * When this bit is set to 1 a Clause 45 mdio access is done.\n+\t * when this bit is set to 0 a Clause 22 mdio access is done.\n+\t */\n+\tuint8_t\tcl45_mdio;\n+\t/* */\n+\tuint8_t\tunused_1[7];\n+} __attribute__((packed));\n+\n+/* hwrm_port_phy_mdio_write_output (size:128b/16B) */\n+struct hwrm_port_phy_mdio_write_output {\n+\t/* The specific error status for the command. */\n+\tuint16_t\terror_code;\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/* The sequence ID from the original command. */\n+\tuint16_t\tseq_id;\n+\t/* The length of the response data in number of bytes. */\n+\tuint16_t\tresp_len;\n+\tuint8_t\tunused_0[7];\n \t/*\n-\t * This bit must be '1' for the led0_id field to be\n-\t * configured.\n+\t * This field is used in Output records to indicate that the output\n+\t * is completely written to RAM. This field should be read as '1'\n+\t * to indicate that the output has been completely written.\n+\t * When writing a command completion or response to an internal processor,\n+\t * the order of writes has to be such that this field is written last.\n \t */\n-\t#define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_ID \\\n-\t\tUINT32_C(0x1)\n+\tuint8_t\tvalid;\n+} __attribute__((packed));\n+\n+/***************************\n+ * hwrm_port_phy_mdio_read *\n+ ***************************/\n+\n+\n+/* hwrm_port_phy_mdio_read_input (size:256b/32B) */\n+struct hwrm_port_phy_mdio_read_input {\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n \t/*\n-\t * This bit must be '1' for the led0_state field to be\n-\t * configured.\n+\t * The completion ring to send the completion event on. This should\n+\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n \t */\n-\t#define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_STATE \\\n-\t\tUINT32_C(0x2)\n+\tuint16_t\tcmpl_ring;\n \t/*\n-\t * This bit must be '1' for the led0_color field to be\n-\t * configured.\n+\t * The sequence ID is used by the driver for tracking multiple\n+\t * commands. This ID is treated as opaque data by the firmware and\n+\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n \t */\n-\t#define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_COLOR \\\n-\t\tUINT32_C(0x4)\n+\tuint16_t\tseq_id;\n \t/*\n-\t * This bit must be '1' for the led0_blink_on field to be\n-\t * configured.\n+\t * The target ID of the command:\n+\t * * 0x0-0xFFF8 - The function ID\n+\t * * 0xFFF8-0xFFFE - Reserved for internal processors\n+\t * * 0xFFFF - HWRM\n \t */\n-\t#define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_BLINK_ON \\\n-\t\tUINT32_C(0x8)\n+\tuint16_t\ttarget_id;\n \t/*\n-\t * This bit must be '1' for the led0_blink_off field to be\n-\t * configured.\n+\t * A physical address pointer pointing to a host buffer that the\n+\t * command's response data will be written. This can be either a host\n+\t * physical address (HPA) or a guest physical address (GPA) and must\n+\t * point to a physically contiguous block of memory.\n \t */\n-\t#define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_BLINK_OFF \\\n-\t\tUINT32_C(0x10)\n+\tuint64_t\tresp_addr;\n+\t/* Reserved for future use. */\n+\tuint32_t\tunused_0[2];\n+\t/* Port ID of port. */\n+\tuint16_t\tport_id;\n+\t/* If phy_address is 0xFF, port_id will be used to derive phy_addr. */\n+\tuint8_t\tphy_addr;\n+\t/* 8-bit device address. */\n+\tuint8_t\tdev_addr;\n+\t/* 16-bit register address. */\n+\tuint16_t\treg_addr;\n \t/*\n-\t * This bit must be '1' for the led0_group_id field to be\n-\t * configured.\n+\t * When this bit is set to 1 a Clause 45 mdio access is done.\n+\t * when this bit is set to 0 a Clause 22 mdio access is done.\n \t */\n-\t#define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_GROUP_ID \\\n-\t\tUINT32_C(0x20)\n+\tuint8_t\tcl45_mdio;\n+\t/* */\n+\tuint8_t\tunused_1;\n+} __attribute__((packed));\n+\n+/* hwrm_port_phy_mdio_read_output (size:128b/16B) */\n+struct hwrm_port_phy_mdio_read_output {\n+\t/* The specific error status for the command. */\n+\tuint16_t\terror_code;\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/* The sequence ID from the original command. */\n+\tuint16_t\tseq_id;\n+\t/* The length of the response data in number of bytes. */\n+\tuint16_t\tresp_len;\n+\t/* 16-bit register data. */\n+\tuint16_t\treg_data;\n+\tuint8_t\tunused_0[5];\n \t/*\n-\t * This bit must be '1' for the led1_id field to be\n-\t * configured.\n+\t * This field is used in Output records to indicate that the output\n+\t * is completely written to RAM. This field should be read as '1'\n+\t * to indicate that the output has been completely written.\n+\t * When writing a command completion or response to an internal processor,\n+\t * the order of writes has to be such that this field is written last.\n+\t */\n+\tuint8_t\tvalid;\n+} __attribute__((packed));\n+\n+/*********************\n+ * hwrm_port_led_cfg *\n+ *********************/\n+\n+\n+/* hwrm_port_led_cfg_input (size:512b/64B) */\n+struct hwrm_port_led_cfg_input {\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/*\n+\t * The completion ring to send the completion event on. This should\n+\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n+\t */\n+\tuint16_t\tcmpl_ring;\n+\t/*\n+\t * The sequence ID is used by the driver for tracking multiple\n+\t * commands. This ID is treated as opaque data by the firmware and\n+\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n+\t */\n+\tuint16_t\tseq_id;\n+\t/*\n+\t * The target ID of the command:\n+\t * * 0x0-0xFFF8 - The function ID\n+\t * * 0xFFF8-0xFFFE - Reserved for internal processors\n+\t * * 0xFFFF - HWRM\n+\t */\n+\tuint16_t\ttarget_id;\n+\t/*\n+\t * A physical address pointer pointing to a host buffer that the\n+\t * command's response data will be written. This can be either a host\n+\t * physical address (HPA) or a guest physical address (GPA) and must\n+\t * point to a physically contiguous block of memory.\n+\t */\n+\tuint64_t\tresp_addr;\n+\tuint32_t\tenables;\n+\t/*\n+\t * This bit must be '1' for the led0_id field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_ID \\\n+\t\tUINT32_C(0x1)\n+\t/*\n+\t * This bit must be '1' for the led0_state field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_STATE \\\n+\t\tUINT32_C(0x2)\n+\t/*\n+\t * This bit must be '1' for the led0_color field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_COLOR \\\n+\t\tUINT32_C(0x4)\n+\t/*\n+\t * This bit must be '1' for the led0_blink_on field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_BLINK_ON \\\n+\t\tUINT32_C(0x8)\n+\t/*\n+\t * This bit must be '1' for the led0_blink_off field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_BLINK_OFF \\\n+\t\tUINT32_C(0x10)\n+\t/*\n+\t * This bit must be '1' for the led0_group_id field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_GROUP_ID \\\n+\t\tUINT32_C(0x20)\n+\t/*\n+\t * This bit must be '1' for the led1_id field to be\n+\t * configured.\n \t */\n \t#define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_ID \\\n \t\tUINT32_C(0x40)\n@@ -20644,7 +21803,9 @@ struct hwrm_ring_reset_output {\n \tuint16_t\tseq_id;\n \t/* The length of the response data in number of bytes. */\n \tuint16_t\tresp_len;\n-\tuint8_t\tunused_0[7];\n+\tuint8_t\tunused_0[4];\n+\t/* Position of consumer index after ring reset completes. */\n+\tuint8_t\tconsumer_idx[3];\n \t/*\n \t * This field is used in Output records to indicate that the output\n \t * is completely written to RAM. This field should be read as '1'\n@@ -21209,6 +22370,26 @@ struct hwrm_ring_grp_free_output {\n \t */\n \tuint8_t\tvalid;\n } __attribute__((packed));\n+/*\n+ * special reserved flow ID to identify per function default\n+ * flows for vSwitch offload\n+ */\n+#define DEFAULT_FLOW_ID 0xFFFFFFFFUL\n+/*\n+ * special reserved flow ID to identify per function RoCEv1\n+ * flows\n+ */\n+#define ROCEV1_FLOW_ID 0xFFFFFFFEUL\n+/*\n+ * special reserved flow ID to identify per function RoCEv2\n+ * flows\n+ */\n+#define ROCEV2_FLOW_ID 0xFFFFFFFDUL\n+/*\n+ * special reserved flow ID to identify per function RoCEv2\n+ * CNP flows\n+ */\n+#define ROCEV2_CNP_FLOW_ID 0xFFFFFFFCUL\n \n /****************************\n * hwrm_cfa_l2_filter_alloc *\n@@ -22968,6 +24149,13 @@ struct hwrm_cfa_encap_record_alloc_input {\n \t/* Setting of this flag indicates the applicability to the loopback path. */\n \t#define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_FLAGS_LOOPBACK \\\n \t\tUINT32_C(0x1)\n+\t/*\n+\t * Setting of this flag indicates this encap record is external encap record.\n+\t * Resetting of this flag indicates this flag is internal encap record and\n+\t * this is the default setting.\n+\t */\n+\t#define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_FLAGS_EXTERNAL \\\n+\t\tUINT32_C(0x2)\n \t/* Encapsulation Type. */\n \tuint8_t\tencap_type;\n \t/* Virtual eXtensible Local Area Network (VXLAN) */\n@@ -23003,8 +24191,11 @@ struct hwrm_cfa_encap_record_alloc_input {\n \t/* Use fixed layer 2 ether type of 0xFFFF */\n \t#define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_L2_ETYPE \\\n \t\tUINT32_C(0xb)\n+\t/* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */\n+\t#define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VXLAN_GPE_V6 \\\n+\t\tUINT32_C(0xc)\n \t#define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_LAST \\\n-\t\tHWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_L2_ETYPE\n+\t\tHWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VXLAN_GPE_V6\n \tuint8_t\tunused_0[3];\n \t/* This value is encap data used for the given encap type. */\n \tuint32_t\tencap_data[20];\n@@ -23144,6 +24335,12 @@ struct hwrm_cfa_ntuple_filter_alloc_input {\n \t */\n \t#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_METER \\\n \t\tUINT32_C(0x4)\n+\t/*\n+\t * Setting of this flag indicates that the dest_id field contains function ID.\n+\t * If this is not set it indicates dest_id is VNIC or VPORT.\n+\t */\n+\t#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DEST_FID \\\n+\t\tUINT32_C(0x8)\n \tuint32_t\tenables;\n \t/*\n \t * This bit must be '1' for the l2_filter_id field to be\n@@ -23605,7 +24802,13 @@ struct hwrm_cfa_ntuple_filter_cfg_input {\n \t */\n \t#define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_ENABLES_NEW_METER_INSTANCE_ID \\\n \t\tUINT32_C(0x4)\n-\tuint8_t\tunused_0[4];\n+\tuint32_t\tflags;\n+\t/*\n+\t * Setting this bit to 1 indicates that dest_id field contains FID.\n+\t * Setting this to 0 indicates that dest_id field contains VNIC or VPORT.\n+\t */\n+\t#define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_FLAGS_DEST_FID \\\n+\t\tUINT32_C(0x1)\n \t/* This value is an opaque id into CFA data structures. */\n \tuint64_t\tntuple_filter_id;\n \t/*\n@@ -24090,6 +25293,118 @@ struct hwrm_cfa_em_flow_free_output {\n \tuint8_t\tvalid;\n } __attribute__((packed));\n \n+/************************\n+ * hwrm_cfa_meter_qcaps *\n+ ************************/\n+\n+\n+/* hwrm_cfa_meter_qcaps_input (size:128b/16B) */\n+struct hwrm_cfa_meter_qcaps_input {\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/*\n+\t * The completion ring to send the completion event on. This should\n+\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n+\t */\n+\tuint16_t\tcmpl_ring;\n+\t/*\n+\t * The sequence ID is used by the driver for tracking multiple\n+\t * commands. This ID is treated as opaque data by the firmware and\n+\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n+\t */\n+\tuint16_t\tseq_id;\n+\t/*\n+\t * The target ID of the command:\n+\t * * 0x0-0xFFF8 - The function ID\n+\t * * 0xFFF8-0xFFFE - Reserved for internal processors\n+\t * * 0xFFFF - HWRM\n+\t */\n+\tuint16_t\ttarget_id;\n+\t/*\n+\t * A physical address pointer pointing to a host buffer that the\n+\t * command's response data will be written. This can be either a host\n+\t * physical address (HPA) or a guest physical address (GPA) and must\n+\t * point to a physically contiguous block of memory.\n+\t */\n+\tuint64_t\tresp_addr;\n+} __attribute__((packed));\n+\n+/* hwrm_cfa_meter_qcaps_output (size:320b/40B) */\n+struct hwrm_cfa_meter_qcaps_output {\n+\t/* The specific error status for the command. */\n+\tuint16_t\terror_code;\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/* The sequence ID from the original command. */\n+\tuint16_t\tseq_id;\n+\t/* The length of the response data in number of bytes. */\n+\tuint16_t\tresp_len;\n+\tuint32_t\tflags;\n+\t/*\n+\t * Enumeration denoting the clock at which the Meter is running with.\n+\t * This enumeration is used for resources that are similar for both\n+\t * TX and RX paths of the chip.\n+\t */\n+\t#define HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_MASK UINT32_C(0xf)\n+\t#define HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_SFT 0\n+\t/* 375 MHz */\n+\t#define HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_375MHZ UINT32_C(0x0)\n+\t/* 625 MHz */\n+\t#define HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_625MHZ UINT32_C(0x1)\n+\t#define HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_LAST \\\n+\t\tHWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_625MHZ\n+\tuint8_t\tunused_0[4];\n+\t/*\n+\t * The minimum guaranteed number of tx meter profiles supported\n+\t * for this function.\n+\t */\n+\tuint16_t\tmin_tx_profile;\n+\t/*\n+\t * The maximum non-guaranteed number of tx meter profiles supported\n+\t * for this function.\n+\t */\n+\tuint16_t\tmax_tx_profile;\n+\t/*\n+\t * The minimum guaranteed number of rx meter profiles supported\n+\t * for this function.\n+\t */\n+\tuint16_t\tmin_rx_profile;\n+\t/*\n+\t * The maximum non-guaranteed number of rx meter profiles supported\n+\t * for this function.\n+\t */\n+\tuint16_t\tmax_rx_profile;\n+\t/*\n+\t * The minimum guaranteed number of tx meter instances supported\n+\t * for this function.\n+\t */\n+\tuint16_t\tmin_tx_instance;\n+\t/*\n+\t * The maximum non-guaranteed number of tx meter instances supported\n+\t * for this function.\n+\t */\n+\tuint16_t\tmax_tx_instance;\n+\t/*\n+\t * The minimum guaranteed number of rx meter instances supported\n+\t * for this function.\n+\t */\n+\tuint16_t\tmin_rx_instance;\n+\t/*\n+\t * The maximum non-guaranteed number of rx meter instances supported\n+\t * for this function.\n+\t */\n+\tuint16_t\tmax_rx_instance;\n+\tuint8_t\tunused_1[7];\n+\t/*\n+\t * This field is used in Output records to indicate that the output\n+\t * is completely written to RAM. This field should be read as '1'\n+\t * to indicate that the output has been completely written.\n+\t * When writing a command completion or response to an internal processor,\n+\t * the order of writes has to be such that this field is written last.\n+\t */\n+\tuint8_t\tvalid;\n+} __attribute__((packed));\n+\n /********************************\n * hwrm_cfa_meter_profile_alloc *\n ********************************/\n@@ -24200,11 +25515,11 @@ struct hwrm_cfa_meter_profile_alloc_input {\n \t/* Value is in 1/100th of a percentage of total bandwidth. */\n \t#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_PERCENT1_100 \\\n \t\t(UINT32_C(0x1) << 29)\n-\t/* Invalid unit */\n-\t#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_INVALID \\\n+\t/* Raw value */\n+\t#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_RAW \\\n \t\t(UINT32_C(0x7) << 29)\n \t#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_LAST \\\n-\t\tHWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_INVALID\n+\t\tHWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_RAW\n \t/* A meter burst size specified in bytes. */\n \tuint32_t\tcommit_burst;\n \t/* The bandwidth value. */\n@@ -24243,7 +25558,7 @@ struct hwrm_cfa_meter_profile_alloc_input {\n \t/* Value is in 1/100th of a percentage of total bandwidth. */\n \t#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_PERCENT1_100 \\\n \t\t(UINT32_C(0x1) << 29)\n-\t/* Invalid unit */\n+\t/* Invalid value */\n \t#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_INVALID \\\n \t\t(UINT32_C(0x7) << 29)\n \t#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_LAST \\\n@@ -24286,11 +25601,11 @@ struct hwrm_cfa_meter_profile_alloc_input {\n \t/* Value is in 1/100th of a percentage of total bandwidth. */\n \t#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_PERCENT1_100 \\\n \t\t(UINT32_C(0x1) << 29)\n-\t/* Invalid unit */\n-\t#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_INVALID \\\n+\t/* Raw unit */\n+\t#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_RAW \\\n \t\t(UINT32_C(0x7) << 29)\n \t#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_LAST \\\n-\t\tHWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_INVALID\n+\t\tHWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_RAW\n \t/* A meter burst size specified in bytes. */\n \tuint32_t\texcess_peak_burst;\n \t/* The bandwidth value. */\n@@ -24564,11 +25879,11 @@ struct hwrm_cfa_meter_profile_cfg_input {\n \t/* Value is in 1/100th of a percentage of total bandwidth. */\n \t#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_PERCENT1_100 \\\n \t\t(UINT32_C(0x1) << 29)\n-\t/* Invalid unit */\n-\t#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_INVALID \\\n+\t/* Raw value */\n+\t#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_RAW \\\n \t\t(UINT32_C(0x7) << 29)\n \t#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_LAST \\\n-\t\tHWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_INVALID\n+\t\tHWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_RAW\n \t/* A meter burst size specified in bytes. */\n \tuint32_t\tcommit_burst;\n \t/* The bandwidth value. */\n@@ -24607,7 +25922,7 @@ struct hwrm_cfa_meter_profile_cfg_input {\n \t/* Value is in 1/100th of a percentage of total bandwidth. */\n \t#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_PERCENT1_100 \\\n \t\t(UINT32_C(0x1) << 29)\n-\t/* Invalid unit */\n+\t/* Invalid value */\n \t#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_INVALID \\\n \t\t(UINT32_C(0x7) << 29)\n \t#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_LAST \\\n@@ -24650,11 +25965,11 @@ struct hwrm_cfa_meter_profile_cfg_input {\n \t/* Value is in 1/100th of a percentage of total bandwidth. */\n \t#define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_PERCENT1_100 \\\n \t\t(UINT32_C(0x1) << 29)\n-\t/* Invalid unit */\n-\t#define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_INVALID \\\n+\t/* Raw unit */\n+\t#define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_RAW \\\n \t\t(UINT32_C(0x7) << 29)\n \t#define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_LAST \\\n-\t\tHWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_INVALID\n+\t\tHWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_RAW\n \t/* A meter burst size specified in bytes. */\n \tuint32_t\texcess_peak_burst;\n \t/* The bandwidth value. */\n@@ -24775,7 +26090,7 @@ struct hwrm_cfa_meter_instance_alloc_input {\n \t/* This value identifies a meter profile in CFA. */\n \tuint16_t\tmeter_profile_id;\n \t/*\n-\t * A value of 0xfff is considered invalid and implies the\n+\t * A value of 0xffff is considered invalid and implies the\n \t * profile is not configured.\n \t */\n \t#define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_METER_PROFILE_ID_INVALID \\\n@@ -24798,7 +26113,7 @@ struct hwrm_cfa_meter_instance_alloc_output {\n \t/* This value identifies a meter instance in CFA. */\n \tuint16_t\tmeter_instance_id;\n \t/*\n-\t * A value of 0xfff is considered invalid and implies the\n+\t * A value of 0xffff is considered invalid and implies the\n \t * instance is not configured.\n \t */\n \t#define HWRM_CFA_METER_INSTANCE_ALLOC_OUTPUT_METER_INSTANCE_ID_INVALID \\\n@@ -24816,13 +26131,13 @@ struct hwrm_cfa_meter_instance_alloc_output {\n \tuint8_t\tvalid;\n } __attribute__((packed));\n \n-/********************************\n- * hwrm_cfa_meter_instance_free *\n- ********************************/\n+/*******************************\n+ * hwrm_cfa_meter_instance_cfg *\n+ *******************************/\n \n \n-/* hwrm_cfa_meter_instance_free_input (size:192b/24B) */\n-struct hwrm_cfa_meter_instance_free_input {\n+/* hwrm_cfa_meter_instance_cfg_input (size:192b/24B) */\n+struct hwrm_cfa_meter_instance_cfg_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n \t/*\n@@ -24856,31 +26171,39 @@ struct hwrm_cfa_meter_instance_free_input {\n \t * This enumeration is used for resources that are similar for both\n \t * TX and RX paths of the chip.\n \t */\n-\t#define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH UINT32_C(0x1)\n+\t#define HWRM_CFA_METER_INSTANCE_CFG_INPUT_FLAGS_PATH UINT32_C(0x1)\n \t/* tx path */\n-\t#define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_TX \\\n+\t#define HWRM_CFA_METER_INSTANCE_CFG_INPUT_FLAGS_PATH_TX \\\n \t\tUINT32_C(0x0)\n \t/* rx path */\n-\t#define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_RX \\\n+\t#define HWRM_CFA_METER_INSTANCE_CFG_INPUT_FLAGS_PATH_RX \\\n \t\tUINT32_C(0x1)\n-\t#define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_LAST \\\n-\t\tHWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_RX\n+\t#define HWRM_CFA_METER_INSTANCE_CFG_INPUT_FLAGS_PATH_LAST \\\n+\t\tHWRM_CFA_METER_INSTANCE_CFG_INPUT_FLAGS_PATH_RX\n \tuint8_t\tunused_0;\n-\t/* This value identifies a meter instance in CFA. */\n-\tuint16_t\tmeter_instance_id;\n \t/*\n-\t * A value of 0xfff is considered invalid and implies the\n-\t * instance is not configured.\n+\t * This value identifies a new meter profile to be associated with\n+\t * the meter instance specified in this command.\n \t */\n-\t#define HWRM_CFA_METER_INSTANCE_FREE_INPUT_METER_INSTANCE_ID_INVALID \\\n+\tuint16_t\tmeter_profile_id;\n+\t/*\n+\t * A value of 0xffff is considered invalid and implies the\n+\t * profile is not configured.\n+\t */\n+\t#define HWRM_CFA_METER_INSTANCE_CFG_INPUT_METER_PROFILE_ID_INVALID \\\n \t\tUINT32_C(0xffff)\n-\t#define HWRM_CFA_METER_INSTANCE_FREE_INPUT_METER_INSTANCE_ID_LAST \\\n-\t\tHWRM_CFA_METER_INSTANCE_FREE_INPUT_METER_INSTANCE_ID_INVALID\n-\tuint8_t\tunused_1[4];\n+\t#define HWRM_CFA_METER_INSTANCE_CFG_INPUT_METER_PROFILE_ID_LAST \\\n+\t\tHWRM_CFA_METER_INSTANCE_CFG_INPUT_METER_PROFILE_ID_INVALID\n+\t/*\n+\t * This value identifies the ID of a meter instance that needs to be updated with\n+\t * a new meter profile specified in this command.\n+\t */\n+\tuint16_t\tmeter_instance_id;\n+\tuint8_t\tunused_1[2];\n } __attribute__((packed));\n \n-/* hwrm_cfa_meter_instance_free_output (size:128b/16B) */\n-struct hwrm_cfa_meter_instance_free_output {\n+/* hwrm_cfa_meter_instance_cfg_output (size:128b/16B) */\n+struct hwrm_cfa_meter_instance_cfg_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n \t/* The HWRM command request type. */\n@@ -24900,13 +26223,13 @@ struct hwrm_cfa_meter_instance_free_output {\n \tuint8_t\tvalid;\n } __attribute__((packed));\n \n-/*******************************\n- * hwrm_cfa_decap_filter_alloc *\n- *******************************/\n+/********************************\n+ * hwrm_cfa_meter_instance_free *\n+ ********************************/\n \n \n-/* hwrm_cfa_decap_filter_alloc_input (size:832b/104B) */\n-struct hwrm_cfa_decap_filter_alloc_input {\n+/* hwrm_cfa_meter_instance_free_input (size:192b/24B) */\n+struct hwrm_cfa_meter_instance_free_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n \t/*\n@@ -24934,22 +26257,106 @@ struct hwrm_cfa_decap_filter_alloc_input {\n \t * point to a physically contiguous block of memory.\n \t */\n \tuint64_t\tresp_addr;\n-\tuint32_t\tflags;\n-\t/* ovs_tunnel is 1 b */\n-\t#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_FLAGS_OVS_TUNNEL \\\n-\t\tUINT32_C(0x1)\n-\tuint32_t\tenables;\n+\tuint8_t\tflags;\n \t/*\n-\t * This bit must be '1' for the tunnel_type field to be\n-\t * configured.\n+\t * Enumeration denoting the RX, TX type of the resource.\n+\t * This enumeration is used for resources that are similar for both\n+\t * TX and RX paths of the chip.\n \t */\n-\t#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \\\n+\t#define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH UINT32_C(0x1)\n+\t/* tx path */\n+\t#define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_TX \\\n+\t\tUINT32_C(0x0)\n+\t/* rx path */\n+\t#define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_RX \\\n \t\tUINT32_C(0x1)\n+\t#define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_LAST \\\n+\t\tHWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_RX\n+\tuint8_t\tunused_0;\n+\t/* This value identifies a meter instance in CFA. */\n+\tuint16_t\tmeter_instance_id;\n \t/*\n-\t * This bit must be '1' for the tunnel_id field to be\n-\t * configured.\n+\t * A value of 0xfff is considered invalid and implies the\n+\t * instance is not configured.\n \t */\n-\t#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_ID \\\n+\t#define HWRM_CFA_METER_INSTANCE_FREE_INPUT_METER_INSTANCE_ID_INVALID \\\n+\t\tUINT32_C(0xffff)\n+\t#define HWRM_CFA_METER_INSTANCE_FREE_INPUT_METER_INSTANCE_ID_LAST \\\n+\t\tHWRM_CFA_METER_INSTANCE_FREE_INPUT_METER_INSTANCE_ID_INVALID\n+\tuint8_t\tunused_1[4];\n+} __attribute__((packed));\n+\n+/* hwrm_cfa_meter_instance_free_output (size:128b/16B) */\n+struct hwrm_cfa_meter_instance_free_output {\n+\t/* The specific error status for the command. */\n+\tuint16_t\terror_code;\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/* The sequence ID from the original command. */\n+\tuint16_t\tseq_id;\n+\t/* The length of the response data in number of bytes. */\n+\tuint16_t\tresp_len;\n+\tuint8_t\tunused_0[7];\n+\t/*\n+\t * This field is used in Output records to indicate that the output\n+\t * is completely written to RAM. This field should be read as '1'\n+\t * to indicate that the output has been completely written.\n+\t * When writing a command completion or response to an internal processor,\n+\t * the order of writes has to be such that this field is written last.\n+\t */\n+\tuint8_t\tvalid;\n+} __attribute__((packed));\n+\n+/*******************************\n+ * hwrm_cfa_decap_filter_alloc *\n+ *******************************/\n+\n+\n+/* hwrm_cfa_decap_filter_alloc_input (size:832b/104B) */\n+struct hwrm_cfa_decap_filter_alloc_input {\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/*\n+\t * The completion ring to send the completion event on. This should\n+\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n+\t */\n+\tuint16_t\tcmpl_ring;\n+\t/*\n+\t * The sequence ID is used by the driver for tracking multiple\n+\t * commands. This ID is treated as opaque data by the firmware and\n+\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n+\t */\n+\tuint16_t\tseq_id;\n+\t/*\n+\t * The target ID of the command:\n+\t * * 0x0-0xFFF8 - The function ID\n+\t * * 0xFFF8-0xFFFE - Reserved for internal processors\n+\t * * 0xFFFF - HWRM\n+\t */\n+\tuint16_t\ttarget_id;\n+\t/*\n+\t * A physical address pointer pointing to a host buffer that the\n+\t * command's response data will be written. This can be either a host\n+\t * physical address (HPA) or a guest physical address (GPA) and must\n+\t * point to a physically contiguous block of memory.\n+\t */\n+\tuint64_t\tresp_addr;\n+\tuint32_t\tflags;\n+\t/* ovs_tunnel is 1 b */\n+\t#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_FLAGS_OVS_TUNNEL \\\n+\t\tUINT32_C(0x1)\n+\tuint32_t\tenables;\n+\t/*\n+\t * This bit must be '1' for the tunnel_type field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \\\n+\t\tUINT32_C(0x1)\n+\t/*\n+\t * This bit must be '1' for the tunnel_id field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_ID \\\n \t\tUINT32_C(0x2)\n \t/*\n \t * This bit must be '1' for the src_macaddr field to be\n@@ -25375,6 +26782,9 @@ struct hwrm_cfa_flow_alloc_input {\n \t */\n \t#define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_MATCH_VXLAN_IP_VNI \\\n \t\tUINT32_C(0x100)\n+\t/* Set to 1 to indicate vhost_id is specified in the outer_vlan_tci field. */\n+\t#define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_VHOST_ID_USE_VLAN \\\n+\t\tUINT32_C(0x200)\n \t/*\n \t * Tx Flow: vf fid.\n \t * Rx Flow: pf fid.\n@@ -25430,6 +26840,13 @@ struct hwrm_cfa_flow_alloc_input {\n \t/* If set to 1, flow aging is enabled for this flow. */\n \t#define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_FLOW_AGING_ENABLED \\\n \t\tUINT32_C(0x800)\n+\t/*\n+\t * If set to 1 an attempt will be made to try to offload this flow to the\n+\t * most optimal flow table resource. If set to 0, the flow will be\n+\t * placed to the default flow table resource.\n+\t */\n+\t#define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_PRI_HINT \\\n+\t\tUINT32_C(0x1000)\n \t/*\n \t * Tx Flow: pf or vf fid.\n \t * Rx Flow: vf fid.\n@@ -25569,7 +26986,8 @@ struct hwrm_cfa_flow_alloc_output {\n \tuint32_t\tflow_id;\n \t/* This value identifies a set of CFA data structures used for a flow. */\n \tuint64_t\text_flow_handle;\n-\tuint8_t\tunused_1[7];\n+\tuint32_t\tflow_counter_id;\n+\tuint8_t\tunused_1[3];\n \t/*\n \t * This field is used in Output records to indicate that the output\n \t * is completely written to RAM. This field should be read as '1'\n@@ -25646,6 +27064,229 @@ struct hwrm_cfa_flow_free_output {\n \tuint8_t\tvalid;\n } __attribute__((packed));\n \n+/* hwrm_cfa_flow_action_data (size:960b/120B) */\n+struct hwrm_cfa_flow_action_data {\n+\tuint16_t\taction_flags;\n+\t/* Setting of this flag indicates accept action. */\n+\t#define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_FWD \\\n+\t\tUINT32_C(0x1)\n+\t/* Setting of this flag indicates recycle action. */\n+\t#define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_RECYCLE \\\n+\t\tUINT32_C(0x2)\n+\t/* Setting of this flag indicates drop action. */\n+\t#define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_DROP \\\n+\t\tUINT32_C(0x4)\n+\t/* Setting of this flag indicates meter action. */\n+\t#define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_METER \\\n+\t\tUINT32_C(0x8)\n+\t/* Setting of this flag indicates tunnel action. */\n+\t#define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_TUNNEL \\\n+\t\tUINT32_C(0x10)\n+\t/*\n+\t * If set to 1 and flow direction is TX, it indicates decap of L2 header\n+\t * and encap of tunnel header. If set to 1 and flow direction is RX, it\n+\t * indicates decap of tunnel header and encap L2 header.\n+\t */\n+\t#define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_TUNNEL_IP \\\n+\t\tUINT32_C(0x20)\n+\t/* Setting of this flag indicates ttl decrement action. */\n+\t#define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_TTL_DECREMENT \\\n+\t\tUINT32_C(0x40)\n+\t/* If set to 1, flow aging is enabled for this flow. */\n+\t#define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_FLOW_AGING_ENABLED \\\n+\t\tUINT32_C(0x80)\n+\t/* Setting of this flag indicates encap action.. */\n+\t#define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_ENCAP \\\n+\t\tUINT32_C(0x100)\n+\t/* Setting of this flag indicates decap action.. */\n+\t#define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_DECAP \\\n+\t\tUINT32_C(0x200)\n+\t/* Meter id. */\n+\tuint16_t\tact_meter_id;\n+\t/* VNIC id. */\n+\tuint16_t\tvnic_id;\n+\t/* vport number. */\n+\tuint16_t\tvport_id;\n+\t/* The NAT source/destination. */\n+\tuint16_t\tnat_port;\n+\tuint16_t\tunused_0[3];\n+\t/* NAT IPv4/IPv6 address. */\n+\tuint32_t\tnat_ip_address[4];\n+\t/* Encapsulation Type. */\n+\tuint8_t\tencap_type;\n+\t/* Virtual eXtensible Local Area Network (VXLAN) */\n+\t#define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VXLAN UINT32_C(0x1)\n+\t/* Network Virtualization Generic Routing Encapsulation (NVGRE) */\n+\t#define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_NVGRE UINT32_C(0x2)\n+\t/* Generic Routing Encapsulation (GRE) after inside Ethernet payload */\n+\t#define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_L2GRE UINT32_C(0x3)\n+\t/* IP in IP */\n+\t#define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_IPIP UINT32_C(0x4)\n+\t/* Generic Network Virtualization Encapsulation (Geneve) */\n+\t#define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_GENEVE UINT32_C(0x5)\n+\t/* Multi-Protocol Lable Switching (MPLS) */\n+\t#define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_MPLS UINT32_C(0x6)\n+\t/* VLAN */\n+\t#define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VLAN UINT32_C(0x7)\n+\t/* Generic Routing Encapsulation (GRE) inside IP datagram payload */\n+\t#define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_IPGRE UINT32_C(0x8)\n+\t/* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */\n+\t#define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VXLAN_V4 UINT32_C(0x9)\n+\t/* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */\n+\t#define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_IPGRE_V1 UINT32_C(0xa)\n+\t/* Use fixed layer 2 ether type of 0xFFFF */\n+\t#define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_L2_ETYPE UINT32_C(0xb)\n+\t/* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */\n+\t#define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VXLAN_GPE_V6 UINT32_C(0xc)\n+\t#define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_LAST \\\n+\t\tHWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VXLAN_GPE_V6\n+\tuint8_t\tunused[7];\n+\t/* This value is encap data for the associated encap type. */\n+\tuint32_t\tencap_data[20];\n+} __attribute__((packed));\n+\n+/* hwrm_cfa_flow_tunnel_hdr_data (size:64b/8B) */\n+struct hwrm_cfa_flow_tunnel_hdr_data {\n+\t/* Tunnel Type. */\n+\tuint8_t\ttunnel_type;\n+\t/* Non-tunnel */\n+\t#define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_NONTUNNEL \\\n+\t\tUINT32_C(0x0)\n+\t/* Virtual eXtensible Local Area Network (VXLAN) */\n+\t#define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_VXLAN \\\n+\t\tUINT32_C(0x1)\n+\t/* Network Virtualization Generic Routing Encapsulation (NVGRE) */\n+\t#define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_NVGRE \\\n+\t\tUINT32_C(0x2)\n+\t/* Generic Routing Encapsulation (GRE) inside Ethernet payload */\n+\t#define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_L2GRE \\\n+\t\tUINT32_C(0x3)\n+\t/* IP in IP */\n+\t#define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_IPIP \\\n+\t\tUINT32_C(0x4)\n+\t/* Generic Network Virtualization Encapsulation (Geneve) */\n+\t#define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_GENEVE \\\n+\t\tUINT32_C(0x5)\n+\t/* Multi-Protocol Lable Switching (MPLS) */\n+\t#define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_MPLS \\\n+\t\tUINT32_C(0x6)\n+\t/* Stateless Transport Tunnel (STT) */\n+\t#define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_STT \\\n+\t\tUINT32_C(0x7)\n+\t/* Generic Routing Encapsulation (GRE) inside IP datagram payload */\n+\t#define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_IPGRE \\\n+\t\tUINT32_C(0x8)\n+\t/* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */\n+\t#define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_VXLAN_V4 \\\n+\t\tUINT32_C(0x9)\n+\t/* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */\n+\t#define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_IPGRE_V1 \\\n+\t\tUINT32_C(0xa)\n+\t/* Use fixed layer 2 ether type of 0xFFFF */\n+\t#define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_L2_ETYPE \\\n+\t\tUINT32_C(0xb)\n+\t/* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */\n+\t#define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_VXLAN_GPE_V6 \\\n+\t\tUINT32_C(0xc)\n+\t/* Any tunneled traffic */\n+\t#define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_ANYTUNNEL \\\n+\t\tUINT32_C(0xff)\n+\t#define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_LAST \\\n+\t\tHWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_ANYTUNNEL\n+\tuint8_t\tunused[3];\n+\t/*\n+\t * Tunnel identifier.\n+\t * Virtual Network Identifier (VNI).\n+\t */\n+\tuint32_t\ttunnel_id;\n+} __attribute__((packed));\n+\n+/* hwrm_cfa_flow_l4_key_data (size:64b/8B) */\n+struct hwrm_cfa_flow_l4_key_data {\n+\t/* The value of source port. */\n+\tuint16_t\tl4_src_port;\n+\t/* The value of destination port. */\n+\tuint16_t\tl4_dst_port;\n+\tuint32_t\tunused;\n+} __attribute__((packed));\n+\n+/* hwrm_cfa_flow_l3_key_data (size:512b/64B) */\n+struct hwrm_cfa_flow_l3_key_data {\n+\t/* The value of ip protocol. */\n+\tuint8_t\tip_protocol;\n+\tuint8_t\tunused_0[7];\n+\t/* The value of destination IPv4/IPv6 address. */\n+\tuint32_t\tip_dst[4];\n+\t/* The source IPv4/IPv6 address. */\n+\tuint32_t\tip_src[4];\n+\t/* NAT IPv4/IPv6 address. */\n+\tuint32_t\tnat_ip_address[4];\n+\tuint32_t\tunused[2];\n+} __attribute__((packed));\n+\n+/* hwrm_cfa_flow_l2_key_data (size:448b/56B) */\n+struct hwrm_cfa_flow_l2_key_data {\n+\t/* Destination MAC address. */\n+\tuint16_t\tdmac[3];\n+\tuint16_t\tunused_0;\n+\t/* Source MAC address. */\n+\tuint16_t\tsmac[3];\n+\tuint16_t\tunused_1;\n+\t/* L2 header re-write Destination MAC address. */\n+\tuint16_t\tl2_rewrite_dmac[3];\n+\tuint16_t\tunused_2;\n+\t/* L2 header re-write Source MAC address. */\n+\tuint16_t\tl2_rewrite_smac[3];\n+\t/* Ethertype. */\n+\tuint16_t\tethertype;\n+\t/* Number of VLAN tags. */\n+\tuint16_t\tnum_vlan_tags;\n+\t/* VLAN tpid. */\n+\tuint16_t\tl2_rewrite_vlan_tpid;\n+\t/* VLAN tci. */\n+\tuint16_t\tl2_rewrite_vlan_tci;\n+\tuint8_t\tunused_3[2];\n+\t/* Outer VLAN TPID. */\n+\tuint16_t\tovlan_tpid;\n+\t/* Outer VLAN TCI. */\n+\tuint16_t\tovlan_tci;\n+\t/* Inner VLAN TPID. */\n+\tuint16_t\tivlan_tpid;\n+\t/* Inner VLAN TCI. */\n+\tuint16_t\tivlan_tci;\n+\tuint8_t\tunused[8];\n+} __attribute__((packed));\n+\n+/* hwrm_cfa_flow_key_data (size:4160b/520B) */\n+struct hwrm_cfa_flow_key_data {\n+\t/* Flow associated tunnel L2 header key info. */\n+\tuint32_t\tt_l2_key_data[14];\n+\t/* Flow associated tunnel L2 header mask info. */\n+\tuint32_t\tt_l2_key_mask[14];\n+\t/* Flow associated tunnel L3 header key info. */\n+\tuint32_t\tt_l3_key_data[16];\n+\t/* Flow associated tunnel L3 header mask info. */\n+\tuint32_t\tt_l3_key_mask[16];\n+\t/* Flow associated tunnel L4 header key info. */\n+\tuint32_t\tt_l4_key_data[2];\n+\t/* Flow associated tunnel L4 header mask info. */\n+\tuint32_t\tt_l4_key_mask[2];\n+\t/* Flow associated tunnel header info. */\n+\tuint32_t\ttunnel_hdr[2];\n+\t/* Flow associated L2 header key info. */\n+\tuint32_t\tl2_key_data[14];\n+\t/* Flow associated L2 header mask info. */\n+\tuint32_t\tl2_key_mask[14];\n+\t/* Flow associated L3 header key info. */\n+\tuint32_t\tl3_key_data[16];\n+\t/* Flow associated L3 header mask info. */\n+\tuint32_t\tl3_key_mask[16];\n+\t/* Flow associated L4 header key info. */\n+\tuint32_t\tl4_key_data[2];\n+\t/* Flow associated L4 header mask info. */\n+\tuint32_t\tl4_key_mask[2];\n+} __attribute__((packed));\n+\n /**********************\n * hwrm_cfa_flow_info *\n **********************/\n@@ -25703,7 +27344,7 @@ struct hwrm_cfa_flow_info_input {\n \tuint64_t\text_flow_handle;\n } __attribute__((packed));\n \n-/* hwrm_cfa_flow_info_output (size:448b/56B) */\n+/* hwrm_cfa_flow_info_output (size:5632b/704B) */\n struct hwrm_cfa_flow_info_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n@@ -25713,8 +27354,11 @@ struct hwrm_cfa_flow_info_output {\n \tuint16_t\tseq_id;\n \t/* The length of the response data in number of bytes. */\n \tuint16_t\tresp_len;\n-\t/* flags is 8 b */\n \tuint8_t\tflags;\n+\t/* When set to 1, indicates the configuration is the TX flow. */\n+\t#define HWRM_CFA_FLOW_INFO_OUTPUT_FLAGS_PATH_TX UINT32_C(0x1)\n+\t/* When set to 1, indicates the configuration is the RX flow. */\n+\t#define HWRM_CFA_FLOW_INFO_OUTPUT_FLAGS_PATH_RX UINT32_C(0x2)\n \t/* profile is 8 b */\n \tuint8_t\tprofile;\n \t/* src_fid is 16 b */\n@@ -25737,7 +27381,12 @@ struct hwrm_cfa_flow_info_output {\n \tuint32_t\ttunnel_handle;\n \t/* The flow aging timer for the flow, the unit is 100 milliseconds */\n \tuint16_t\tflow_timer;\n-\tuint8_t\tunused_0[5];\n+\tuint8_t\tunused_0[6];\n+\t/* Flow associated L2, L3 and L4 headers info. */\n+\tuint32_t\tflow_key_data[130];\n+\t/* Flow associated action record info. */\n+\tuint32_t\tflow_action_info[30];\n+\tuint8_t\tunused_1[7];\n \t/*\n \t * This field is used in Output records to indicate that the output\n \t * is completely written to RAM. This field should be read as '1'\n@@ -25753,7 +27402,7 @@ struct hwrm_cfa_flow_info_output {\n ***********************/\n \n \n-/* hwrm_cfa_flow_flush_input (size:192b/24B) */\n+/* hwrm_cfa_flow_flush_input (size:256b/32B) */\n struct hwrm_cfa_flow_flush_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n@@ -25782,8 +27431,73 @@ struct hwrm_cfa_flow_flush_input {\n \t * point to a physically contiguous block of memory.\n \t */\n \tuint64_t\tresp_addr;\n+\t/* flags is 32 b */\n \tuint32_t\tflags;\n-\tuint8_t\tunused_0[4];\n+\t/*\n+\t * Set to 1 to indicate the page size, page layers, and flow_handle_table_dma_addr\n+\t * fields are valid. The flow flush operation should only flush the flows from the\n+\t * flow table specified. This flag is set to 0 by older driver. For older firmware,\n+\t * setting this flag has no effect.\n+\t */\n+\t#define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_TABLE_VALID \\\n+\t\tUINT32_C(0x1)\n+\t/*\n+\t * Set to 1 to indicate flow flush operation to cleanup all the flows, meters, CFA\n+\t * context memory tables..etc. This flag is set to 0 by older driver. For older firmware,\n+\t * setting this flag has no effect.\n+\t */\n+\t#define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_RESET_ALL \\\n+\t\tUINT32_C(0x2)\n+\t/*\n+\t * This specifies the size of flow handle entries provided by the driver\n+\t * in the flow table specified below. Only two flow handle size enums are defined.\n+\t */\n+\t#define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_ENTRY_SIZE_MASK \\\n+\t\tUINT32_C(0xc0000000)\n+\t#define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_ENTRY_SIZE_SFT \\\n+\t\t30\n+\t/* The flow handle is 16bit */\n+\t#define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_ENTRY_SIZE_FLOW_HND_16BIT \\\n+\t\t(UINT32_C(0x0) << 30)\n+\t/* The flow handle is 64bit */\n+\t#define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_ENTRY_SIZE_FLOW_HND_64BIT \\\n+\t\t(UINT32_C(0x1) << 30)\n+\t#define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_ENTRY_SIZE_LAST \\\n+\t\tHWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_ENTRY_SIZE_FLOW_HND_64BIT\n+\t/* Specify page size of the flow table memory. */\n+\tuint8_t\tpage_size;\n+\t/* The page size is 4K */\n+\t#define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_4K UINT32_C(0x0)\n+\t/* The page size is 8K */\n+\t#define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_8K UINT32_C(0x1)\n+\t/* The page size is 64K */\n+\t#define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_64K UINT32_C(0x4)\n+\t/* The page size is 256K */\n+\t#define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_256K UINT32_C(0x6)\n+\t/* The page size is 1M */\n+\t#define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_1M UINT32_C(0x8)\n+\t/* The page size is 2M */\n+\t#define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_2M UINT32_C(0x9)\n+\t/* The page size is 4M */\n+\t#define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_4M UINT32_C(0xa)\n+\t/* The page size is 1G */\n+\t#define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_1G UINT32_C(0x12)\n+\t#define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_LAST \\\n+\t\tHWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_1G\n+\t/* FLow table memory indirect levels. */\n+\tuint8_t\tpage_level;\n+\t/* PBL pointer is physical start address. */\n+\t#define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_LEVEL_LVL_0 UINT32_C(0x0)\n+\t/* PBL pointer points to PTE table. */\n+\t#define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_LEVEL_LVL_1 UINT32_C(0x1)\n+\t/* PBL pointer points to PDE table with each entry pointing to PTE tables. */\n+\t#define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_LEVEL_LVL_2 UINT32_C(0x2)\n+\t#define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_LEVEL_LAST \\\n+\t\tHWRM_CFA_FLOW_FLUSH_INPUT_PAGE_LEVEL_LVL_2\n+\t/* number of flows in the flow table */\n+\tuint16_t\tnum_flows;\n+\t/* Pointer to the PBL, or PDL depending on number of levels */\n+\tuint64_t\tpage_dir;\n } __attribute__((packed));\n \n /* hwrm_cfa_flow_flush_output (size:128b/16B) */\n@@ -25983,7 +27697,12 @@ struct hwrm_cfa_flow_aging_timer_reset_input {\n \tuint64_t\tresp_addr;\n \t/* Flow record index. */\n \tuint16_t\tflow_handle;\n-\tuint8_t\tunused_0[6];\n+\tuint8_t\tunused_0[2];\n+\t/*\n+\t * New flow timer value for the flow specified in the ext_flow_handle.\n+\t * The flow timer unit is 100ms.\n+\t */\n+\tuint32_t\tflow_timer;\n \t/* This value identifies a set of CFA data structures used for a flow. */\n \tuint64_t\text_flow_handle;\n } __attribute__((packed));\n@@ -26244,13 +27963,13 @@ struct hwrm_cfa_flow_aging_qcaps_output {\n \tuint8_t\tvalid;\n } __attribute__((packed));\n \n-/**********************\n- * hwrm_cfa_pair_info *\n- **********************/\n+/**********************************\n+ * hwrm_cfa_tcp_flag_process_qcfg *\n+ **********************************/\n \n \n-/* hwrm_cfa_pair_info_input (size:448b/56B) */\n-struct hwrm_cfa_pair_info_input {\n+/* hwrm_cfa_tcp_flag_process_qcfg_input (size:128b/16B) */\n+struct hwrm_cfa_tcp_flag_process_qcfg_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n \t/*\n@@ -26278,23 +27997,10 @@ struct hwrm_cfa_pair_info_input {\n \t * point to a physically contiguous block of memory.\n \t */\n \tuint64_t\tresp_addr;\n-\tuint32_t\tflags;\n-\t/* If this flag is set, lookup by name else lookup by index. */\n-\t#define HWRM_CFA_PAIR_INFO_INPUT_FLAGS_LOOKUP_TYPE UINT32_C(0x1)\n-\t/* If this flag is set, lookup by PF id and VF id. */\n-\t#define HWRM_CFA_PAIR_INFO_INPUT_FLAGS_LOOKUP_REPRE UINT32_C(0x2)\n-\t/* Pair table index. */\n-\tuint16_t\tpair_index;\n-\t/* Pair pf index. */\n-\tuint8_t\tpair_pfid;\n-\t/* Pair vf index. */\n-\tuint8_t\tpair_vfid;\n-\t/* Pair name (32 byte string). */\n-\tchar\tpair_name[32];\n } __attribute__((packed));\n \n-/* hwrm_cfa_pair_info_output (size:576b/72B) */\n-struct hwrm_cfa_pair_info_output {\n+/* hwrm_cfa_tcp_flag_process_qcfg_output (size:192b/24B) */\n+struct hwrm_cfa_tcp_flag_process_qcfg_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n \t/* The HWRM command request type. */\n@@ -26303,22 +28009,100 @@ struct hwrm_cfa_pair_info_output {\n \tuint16_t\tseq_id;\n \t/* The length of the response data in number of bytes. */\n \tuint16_t\tresp_len;\n-\t/* Pair table index. */\n-\tuint16_t\tnext_pair_index;\n-\t/* Pair member a's fid. */\n-\tuint16_t\ta_fid;\n-\t/* Logical host number. */\n-\tuint8_t\thost_a_index;\n-\t/* Logical PF number. */\n-\tuint8_t\tpf_a_index;\n-\t/* Pair member a's Linux logical VF number. */\n-\tuint16_t\tvf_a_index;\n-\t/* Rx CFA code. */\n-\tuint16_t\trx_cfa_code_a;\n-\t/* Tx CFA action. */\n-\tuint16_t\ttx_cfa_action_a;\n-\t/* Pair member b's fid. */\n-\tuint16_t\tb_fid;\n+\t/* The port 0 RX mirror action record ID. */\n+\tuint16_t\trx_ar_id_port0;\n+\t/* The port 1 RX mirror action record ID. */\n+\tuint16_t\trx_ar_id_port1;\n+\t/* The port 0 RX action record ID for TX TCP flag packets from loopback path. */\n+\tuint16_t\ttx_ar_id_port0;\n+\t/* The port 1 RX action record ID for TX TCP flag packets from loopback path. */\n+\tuint16_t\ttx_ar_id_port1;\n+\tuint8_t\tunused_0[7];\n+\t/*\n+\t * This field is used in Output records to indicate that the output\n+\t * is completely written to RAM. This field should be read as '1'\n+\t * to indicate that the output has been completely written.\n+\t * When writing a command completion or response to an internal processor,\n+\t * the order of writes has to be such that this field is written last.\n+\t */\n+\tuint8_t\tvalid;\n+} __attribute__((packed));\n+\n+/**********************\n+ * hwrm_cfa_pair_info *\n+ **********************/\n+\n+\n+/* hwrm_cfa_pair_info_input (size:448b/56B) */\n+struct hwrm_cfa_pair_info_input {\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/*\n+\t * The completion ring to send the completion event on. This should\n+\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n+\t */\n+\tuint16_t\tcmpl_ring;\n+\t/*\n+\t * The sequence ID is used by the driver for tracking multiple\n+\t * commands. This ID is treated as opaque data by the firmware and\n+\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n+\t */\n+\tuint16_t\tseq_id;\n+\t/*\n+\t * The target ID of the command:\n+\t * * 0x0-0xFFF8 - The function ID\n+\t * * 0xFFF8-0xFFFE - Reserved for internal processors\n+\t * * 0xFFFF - HWRM\n+\t */\n+\tuint16_t\ttarget_id;\n+\t/*\n+\t * A physical address pointer pointing to a host buffer that the\n+\t * command's response data will be written. This can be either a host\n+\t * physical address (HPA) or a guest physical address (GPA) and must\n+\t * point to a physically contiguous block of memory.\n+\t */\n+\tuint64_t\tresp_addr;\n+\tuint32_t\tflags;\n+\t/* If this flag is set, lookup by name else lookup by index. */\n+\t#define HWRM_CFA_PAIR_INFO_INPUT_FLAGS_LOOKUP_TYPE UINT32_C(0x1)\n+\t/* If this flag is set, lookup by PF id and VF id. */\n+\t#define HWRM_CFA_PAIR_INFO_INPUT_FLAGS_LOOKUP_REPRE UINT32_C(0x2)\n+\t/* Pair table index. */\n+\tuint16_t\tpair_index;\n+\t/* Pair pf index. */\n+\tuint8_t\tpair_pfid;\n+\t/* Pair vf index. */\n+\tuint8_t\tpair_vfid;\n+\t/* Pair name (32 byte string). */\n+\tchar\tpair_name[32];\n+} __attribute__((packed));\n+\n+/* hwrm_cfa_pair_info_output (size:576b/72B) */\n+struct hwrm_cfa_pair_info_output {\n+\t/* The specific error status for the command. */\n+\tuint16_t\terror_code;\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/* The sequence ID from the original command. */\n+\tuint16_t\tseq_id;\n+\t/* The length of the response data in number of bytes. */\n+\tuint16_t\tresp_len;\n+\t/* Pair table index. */\n+\tuint16_t\tnext_pair_index;\n+\t/* Pair member a's fid. */\n+\tuint16_t\ta_fid;\n+\t/* Logical host number. */\n+\tuint8_t\thost_a_index;\n+\t/* Logical PF number. */\n+\tuint8_t\tpf_a_index;\n+\t/* Pair member a's Linux logical VF number. */\n+\tuint16_t\tvf_a_index;\n+\t/* Rx CFA code. */\n+\tuint16_t\trx_cfa_code_a;\n+\t/* Tx CFA action. */\n+\tuint16_t\ttx_cfa_action_a;\n+\t/* Pair member b's fid. */\n+\tuint16_t\tb_fid;\n \t/* Logical host number. */\n \tuint8_t\thost_b_index;\n \t/* Logical PF number. */\n@@ -26364,13 +28148,645 @@ struct hwrm_cfa_pair_info_output {\n \tuint8_t\tvalid;\n } __attribute__((packed));\n \n-/***************************************\n- * hwrm_cfa_redirect_query_tunnel_type *\n- ***************************************/\n+/***************************************\n+ * hwrm_cfa_redirect_query_tunnel_type *\n+ ***************************************/\n+\n+\n+/* hwrm_cfa_redirect_query_tunnel_type_input (size:192b/24B) */\n+struct hwrm_cfa_redirect_query_tunnel_type_input {\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/*\n+\t * The completion ring to send the completion event on. This should\n+\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n+\t */\n+\tuint16_t\tcmpl_ring;\n+\t/*\n+\t * The sequence ID is used by the driver for tracking multiple\n+\t * commands. This ID is treated as opaque data by the firmware and\n+\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n+\t */\n+\tuint16_t\tseq_id;\n+\t/*\n+\t * The target ID of the command:\n+\t * * 0x0-0xFFF8 - The function ID\n+\t * * 0xFFF8-0xFFFE - Reserved for internal processors\n+\t * * 0xFFFF - HWRM\n+\t */\n+\tuint16_t\ttarget_id;\n+\t/*\n+\t * A physical address pointer pointing to a host buffer that the\n+\t * command's response data will be written. This can be either a host\n+\t * physical address (HPA) or a guest physical address (GPA) and must\n+\t * point to a physically contiguous block of memory.\n+\t */\n+\tuint64_t\tresp_addr;\n+\t/* The source function id. */\n+\tuint16_t\tsrc_fid;\n+\tuint8_t\tunused_0[6];\n+} __attribute__((packed));\n+\n+/* hwrm_cfa_redirect_query_tunnel_type_output (size:128b/16B) */\n+struct hwrm_cfa_redirect_query_tunnel_type_output {\n+\t/* The specific error status for the command. */\n+\tuint16_t\terror_code;\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/* The sequence ID from the original command. */\n+\tuint16_t\tseq_id;\n+\t/* The length of the response data in number of bytes. */\n+\tuint16_t\tresp_len;\n+\t/* Tunnel Mask. */\n+\tuint32_t\ttunnel_mask;\n+\t/* Non-tunnel */\n+\t#define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_NONTUNNEL \\\n+\t\tUINT32_C(0x1)\n+\t/* Virtual eXtensible Local Area Network (VXLAN) */\n+\t#define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_VXLAN \\\n+\t\tUINT32_C(0x2)\n+\t/* Network Virtualization Generic Routing Encapsulation (NVGRE) */\n+\t#define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_NVGRE \\\n+\t\tUINT32_C(0x4)\n+\t/* Generic Routing Encapsulation (GRE) inside Ethernet payload */\n+\t#define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_L2GRE \\\n+\t\tUINT32_C(0x8)\n+\t/* IP in IP */\n+\t#define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_IPIP \\\n+\t\tUINT32_C(0x10)\n+\t/* Generic Network Virtualization Encapsulation (Geneve) */\n+\t#define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_GENEVE \\\n+\t\tUINT32_C(0x20)\n+\t/* Multi-Protocol Lable Switching (MPLS) */\n+\t#define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_MPLS \\\n+\t\tUINT32_C(0x40)\n+\t/* Stateless Transport Tunnel (STT) */\n+\t#define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_STT \\\n+\t\tUINT32_C(0x80)\n+\t/* Generic Routing Encapsulation (GRE) inside IP datagram payload */\n+\t#define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_IPGRE \\\n+\t\tUINT32_C(0x100)\n+\t/* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */\n+\t#define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_VXLAN_V4 \\\n+\t\tUINT32_C(0x200)\n+\t/* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */\n+\t#define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_IPGRE_V1 \\\n+\t\tUINT32_C(0x400)\n+\t/* Any tunneled traffic */\n+\t#define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_ANYTUNNEL \\\n+\t\tUINT32_C(0x800)\n+\t/* Use fixed layer 2 ether type of 0xFFFF */\n+\t#define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_L2_ETYPE \\\n+\t\tUINT32_C(0x1000)\n+\t/* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */\n+\t#define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_VXLAN_GPE_V6 \\\n+\t\tUINT32_C(0x2000)\n+\tuint8_t\tunused_0[3];\n+\t/*\n+\t * This field is used in Output records to indicate that the output\n+\t * is completely written to RAM. This field should be read as '1'\n+\t * to indicate that the output has been completely written.\n+\t * When writing a command completion or response to an internal processor,\n+\t * the order of writes has to be such that this field is written last.\n+\t */\n+\tuint8_t\tvalid;\n+} __attribute__((packed));\n+\n+/*************************\n+ * hwrm_cfa_ctx_mem_rgtr *\n+ *************************/\n+\n+\n+/* hwrm_cfa_ctx_mem_rgtr_input (size:256b/32B) */\n+struct hwrm_cfa_ctx_mem_rgtr_input {\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/*\n+\t * The completion ring to send the completion event on. This should\n+\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n+\t */\n+\tuint16_t\tcmpl_ring;\n+\t/*\n+\t * The sequence ID is used by the driver for tracking multiple\n+\t * commands. This ID is treated as opaque data by the firmware and\n+\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n+\t */\n+\tuint16_t\tseq_id;\n+\t/*\n+\t * The target ID of the command:\n+\t * * 0x0-0xFFF8 - The function ID\n+\t * * 0xFFF8-0xFFFE - Reserved for internal processors\n+\t * * 0xFFFF - HWRM\n+\t */\n+\tuint16_t\ttarget_id;\n+\t/*\n+\t * A physical address pointer pointing to a host buffer that the\n+\t * command's response data will be written. This can be either a host\n+\t * physical address (HPA) or a guest physical address (GPA) and must\n+\t * point to a physically contiguous block of memory.\n+\t */\n+\tuint64_t\tresp_addr;\n+\tuint16_t\tflags;\n+\t/* Counter PBL indirect levels. */\n+\tuint8_t\tpage_level;\n+\t/* PBL pointer is physical start address. */\n+\t#define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_0 UINT32_C(0x0)\n+\t/* PBL pointer points to PTE table. */\n+\t#define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_1 UINT32_C(0x1)\n+\t/* PBL pointer points to PDE table with each entry pointing to PTE tables. */\n+\t#define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_2 UINT32_C(0x2)\n+\t#define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LAST \\\n+\t\tHWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_2\n+\t/* Page size. */\n+\tuint8_t\tpage_size;\n+\t/* 4KB page size. */\n+\t#define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_4K UINT32_C(0x0)\n+\t/* 8KB page size. */\n+\t#define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_8K UINT32_C(0x1)\n+\t/* 64KB page size. */\n+\t#define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_64K UINT32_C(0x4)\n+\t/* 256KB page size. */\n+\t#define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_256K UINT32_C(0x6)\n+\t/* 1MB page size. */\n+\t#define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_1M UINT32_C(0x8)\n+\t/* 2MB page size. */\n+\t#define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_2M UINT32_C(0x9)\n+\t/* 4MB page size. */\n+\t#define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_4M UINT32_C(0xa)\n+\t/* 1GB page size. */\n+\t#define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_1G UINT32_C(0x12)\n+\t#define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_LAST \\\n+\t\tHWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_1G\n+\tuint32_t\tunused_0;\n+\t/* Pointer to the PBL, or PDL depending on number of levels */\n+\tuint64_t\tpage_dir;\n+} __attribute__((packed));\n+\n+/* hwrm_cfa_ctx_mem_rgtr_output (size:128b/16B) */\n+struct hwrm_cfa_ctx_mem_rgtr_output {\n+\t/* The specific error status for the command. */\n+\tuint16_t\terror_code;\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/* The sequence ID from the original command. */\n+\tuint16_t\tseq_id;\n+\t/* The length of the response data in number of bytes. */\n+\tuint16_t\tresp_len;\n+\t/*\n+\t * Id/Handle to the recently register context memory. This handle is passed\n+\t * to the CFA feature.\n+\t */\n+\tuint16_t\tctx_id;\n+\tuint8_t\tunused_0[5];\n+\t/*\n+\t * This field is used in Output records to indicate that the output\n+\t * is completely written to RAM. This field should be read as '1'\n+\t * to indicate that the output has been completely written.\n+\t * When writing a command completion or response to an internal processor,\n+\t * the order of writes has to be such that this field is written last.\n+\t */\n+\tuint8_t\tvalid;\n+} __attribute__((packed));\n+\n+/***************************\n+ * hwrm_cfa_ctx_mem_unrgtr *\n+ ***************************/\n+\n+\n+/* hwrm_cfa_ctx_mem_unrgtr_input (size:192b/24B) */\n+struct hwrm_cfa_ctx_mem_unrgtr_input {\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/*\n+\t * The completion ring to send the completion event on. This should\n+\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n+\t */\n+\tuint16_t\tcmpl_ring;\n+\t/*\n+\t * The sequence ID is used by the driver for tracking multiple\n+\t * commands. This ID is treated as opaque data by the firmware and\n+\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n+\t */\n+\tuint16_t\tseq_id;\n+\t/*\n+\t * The target ID of the command:\n+\t * * 0x0-0xFFF8 - The function ID\n+\t * * 0xFFF8-0xFFFE - Reserved for internal processors\n+\t * * 0xFFFF - HWRM\n+\t */\n+\tuint16_t\ttarget_id;\n+\t/*\n+\t * A physical address pointer pointing to a host buffer that the\n+\t * command's response data will be written. This can be either a host\n+\t * physical address (HPA) or a guest physical address (GPA) and must\n+\t * point to a physically contiguous block of memory.\n+\t */\n+\tuint64_t\tresp_addr;\n+\t/*\n+\t * Id/Handle to the recently register context memory. This handle is passed\n+\t * to the CFA feature.\n+\t */\n+\tuint16_t\tctx_id;\n+\tuint8_t\tunused_0[6];\n+} __attribute__((packed));\n+\n+/* hwrm_cfa_ctx_mem_unrgtr_output (size:128b/16B) */\n+struct hwrm_cfa_ctx_mem_unrgtr_output {\n+\t/* The specific error status for the command. */\n+\tuint16_t\terror_code;\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/* The sequence ID from the original command. */\n+\tuint16_t\tseq_id;\n+\t/* The length of the response data in number of bytes. */\n+\tuint16_t\tresp_len;\n+\tuint8_t\tunused_0[7];\n+\t/*\n+\t * This field is used in Output records to indicate that the output\n+\t * is completely written to RAM. This field should be read as '1'\n+\t * to indicate that the output has been completely written.\n+\t * When writing a command completion or response to an internal processor,\n+\t * the order of writes has to be such that this field is written last.\n+\t */\n+\tuint8_t\tvalid;\n+} __attribute__((packed));\n+\n+/*************************\n+ * hwrm_cfa_ctx_mem_qctx *\n+ *************************/\n+\n+\n+/* hwrm_cfa_ctx_mem_qctx_input (size:192b/24B) */\n+struct hwrm_cfa_ctx_mem_qctx_input {\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/*\n+\t * The completion ring to send the completion event on. This should\n+\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n+\t */\n+\tuint16_t\tcmpl_ring;\n+\t/*\n+\t * The sequence ID is used by the driver for tracking multiple\n+\t * commands. This ID is treated as opaque data by the firmware and\n+\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n+\t */\n+\tuint16_t\tseq_id;\n+\t/*\n+\t * The target ID of the command:\n+\t * * 0x0-0xFFF8 - The function ID\n+\t * * 0xFFF8-0xFFFE - Reserved for internal processors\n+\t * * 0xFFFF - HWRM\n+\t */\n+\tuint16_t\ttarget_id;\n+\t/*\n+\t * A physical address pointer pointing to a host buffer that the\n+\t * command's response data will be written. This can be either a host\n+\t * physical address (HPA) or a guest physical address (GPA) and must\n+\t * point to a physically contiguous block of memory.\n+\t */\n+\tuint64_t\tresp_addr;\n+\t/*\n+\t * Id/Handle to the recently register context memory. This handle is passed\n+\t * to the CFA feature.\n+\t */\n+\tuint16_t\tctx_id;\n+\tuint8_t\tunused_0[6];\n+} __attribute__((packed));\n+\n+/* hwrm_cfa_ctx_mem_qctx_output (size:256b/32B) */\n+struct hwrm_cfa_ctx_mem_qctx_output {\n+\t/* The specific error status for the command. */\n+\tuint16_t\terror_code;\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/* The sequence ID from the original command. */\n+\tuint16_t\tseq_id;\n+\t/* The length of the response data in number of bytes. */\n+\tuint16_t\tresp_len;\n+\tuint16_t\tflags;\n+\t/* Counter PBL indirect levels. */\n+\tuint8_t\tpage_level;\n+\t/* PBL pointer is physical start address. */\n+\t#define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LVL_0 UINT32_C(0x0)\n+\t/* PBL pointer points to PTE table. */\n+\t#define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LVL_1 UINT32_C(0x1)\n+\t/* PBL pointer points to PDE table with each entry pointing to PTE tables. */\n+\t#define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LVL_2 UINT32_C(0x2)\n+\t#define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LAST \\\n+\t\tHWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LVL_2\n+\t/* Page size. */\n+\tuint8_t\tpage_size;\n+\t/* 4KB page size. */\n+\t#define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_4K UINT32_C(0x0)\n+\t/* 8KB page size. */\n+\t#define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_8K UINT32_C(0x1)\n+\t/* 64KB page size. */\n+\t#define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_64K UINT32_C(0x4)\n+\t/* 256KB page size. */\n+\t#define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_256K UINT32_C(0x6)\n+\t/* 1MB page size. */\n+\t#define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_1M UINT32_C(0x8)\n+\t/* 2MB page size. */\n+\t#define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_2M UINT32_C(0x9)\n+\t/* 4MB page size. */\n+\t#define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_4M UINT32_C(0xa)\n+\t/* 1GB page size. */\n+\t#define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_1G UINT32_C(0x12)\n+\t#define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_LAST \\\n+\t\tHWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_1G\n+\tuint8_t\tunused_0[4];\n+\t/* Pointer to the PBL, or PDL depending on number of levels */\n+\tuint64_t\tpage_dir;\n+\tuint8_t\tunused_1[7];\n+\t/*\n+\t * This field is used in Output records to indicate that the output\n+\t * is completely written to RAM. This field should be read as '1'\n+\t * to indicate that the output has been completely written.\n+\t * When writing a command completion or response to an internal processor,\n+\t * the order of writes has to be such that this field is written last.\n+\t */\n+\tuint8_t\tvalid;\n+} __attribute__((packed));\n+\n+/**************************\n+ * hwrm_cfa_ctx_mem_qcaps *\n+ **************************/\n+\n+\n+/* hwrm_cfa_ctx_mem_qcaps_input (size:128b/16B) */\n+struct hwrm_cfa_ctx_mem_qcaps_input {\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/*\n+\t * The completion ring to send the completion event on. This should\n+\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n+\t */\n+\tuint16_t\tcmpl_ring;\n+\t/*\n+\t * The sequence ID is used by the driver for tracking multiple\n+\t * commands. This ID is treated as opaque data by the firmware and\n+\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n+\t */\n+\tuint16_t\tseq_id;\n+\t/*\n+\t * The target ID of the command:\n+\t * * 0x0-0xFFF8 - The function ID\n+\t * * 0xFFF8-0xFFFE - Reserved for internal processors\n+\t * * 0xFFFF - HWRM\n+\t */\n+\tuint16_t\ttarget_id;\n+\t/*\n+\t * A physical address pointer pointing to a host buffer that the\n+\t * command's response data will be written. This can be either a host\n+\t * physical address (HPA) or a guest physical address (GPA) and must\n+\t * point to a physically contiguous block of memory.\n+\t */\n+\tuint64_t\tresp_addr;\n+} __attribute__((packed));\n+\n+/* hwrm_cfa_ctx_mem_qcaps_output (size:128b/16B) */\n+struct hwrm_cfa_ctx_mem_qcaps_output {\n+\t/* The specific error status for the command. */\n+\tuint16_t\terror_code;\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/* The sequence ID from the original command. */\n+\tuint16_t\tseq_id;\n+\t/* The length of the response data in number of bytes. */\n+\tuint16_t\tresp_len;\n+\t/* Indicates the maximum number of context memory which can be registered. */\n+\tuint16_t\tmax_entries;\n+\tuint8_t\tunused_0[6];\n+} __attribute__((packed));\n+\n+/**********************\n+ * hwrm_cfa_eem_qcaps *\n+ **********************/\n+\n+\n+/* hwrm_cfa_eem_qcaps_input (size:192b/24B) */\n+struct hwrm_cfa_eem_qcaps_input {\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/*\n+\t * The completion ring to send the completion event on. This should\n+\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n+\t */\n+\tuint16_t\tcmpl_ring;\n+\t/*\n+\t * The sequence ID is used by the driver for tracking multiple\n+\t * commands. This ID is treated as opaque data by the firmware and\n+\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n+\t */\n+\tuint16_t\tseq_id;\n+\t/*\n+\t * The target ID of the command:\n+\t * * 0x0-0xFFF8 - The function ID\n+\t * * 0xFFF8-0xFFFE - Reserved for internal processors\n+\t * * 0xFFFF - HWRM\n+\t */\n+\tuint16_t\ttarget_id;\n+\t/*\n+\t * A physical address pointer pointing to a host buffer that the\n+\t * command's response data will be written. This can be either a host\n+\t * physical address (HPA) or a guest physical address (GPA) and must\n+\t * point to a physically contiguous block of memory.\n+\t */\n+\tuint64_t\tresp_addr;\n+\tuint32_t\tflags;\n+\t/*\n+\t * When set to 1, indicates the configuration will apply to TX flows\n+\t * which are to be offloaded.\n+\t * Note if this bit is set then the path_rx bit can't be set.\n+\t */\n+\t#define HWRM_CFA_EEM_QCAPS_INPUT_FLAGS_PATH_TX \\\n+\t\tUINT32_C(0x1)\n+\t/*\n+\t * When set to 1, indicates the configuration will apply to RX flows\n+\t * which are to be offloaded.\n+\t * Note if this bit is set then the path_tx bit can't be set.\n+\t */\n+\t#define HWRM_CFA_EEM_QCAPS_INPUT_FLAGS_PATH_RX \\\n+\t\tUINT32_C(0x2)\n+\t/* When set to 1, all offloaded flows will be sent to EEM. */\n+\t#define HWRM_CFA_EEM_QCAPS_INPUT_FLAGS_PREFERRED_OFFLOAD \\\n+\t\tUINT32_C(0x4)\n+\tuint32_t\tunused_0;\n+} __attribute__((packed));\n+\n+/* hwrm_cfa_eem_qcaps_output (size:256b/32B) */\n+struct hwrm_cfa_eem_qcaps_output {\n+\t/* The specific error status for the command. */\n+\tuint16_t\terror_code;\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/* The sequence ID from the original command. */\n+\tuint16_t\tseq_id;\n+\t/* The length of the response data in number of bytes. */\n+\tuint16_t\tresp_len;\n+\tuint32_t\tflags;\n+\t/*\n+\t * When set to 1, indicates the configuration will apply to TX flows\n+\t * which are to be offloaded.\n+\t * Note if this bit is set then the path_rx bit can't be set.\n+\t */\n+\t#define HWRM_CFA_EEM_QCAPS_OUTPUT_FLAGS_PATH_TX UINT32_C(0x1)\n+\t/*\n+\t * When set to 1, indicates the configuration will apply to RX flows\n+\t * which are to be offloaded.\n+\t * Note if this bit is set then the path_tx bit can't be set.\n+\t */\n+\t#define HWRM_CFA_EEM_QCAPS_OUTPUT_FLAGS_PATH_RX UINT32_C(0x2)\n+\tuint32_t\tunused_0;\n+\tuint32_t\tsupported;\n+\t/*\n+\t * If set to 1, then EEM KEY0 table is supported using crc32 hash.\n+\t * If set to 0 EEM KEY0 table is not supported.\n+\t */\n+\t#define HWRM_CFA_EEM_QCAPS_OUTPUT_SUPPORTED_KEY0_TABLE \\\n+\t\tUINT32_C(0x1)\n+\t/*\n+\t * If set to 1, then EEM KEY1 table is supported using lookup3 hash.\n+\t * If set to 0 EEM KEY1 table is not supported.\n+\t */\n+\t#define HWRM_CFA_EEM_QCAPS_OUTPUT_SUPPORTED_KEY1_TABLE \\\n+\t\tUINT32_C(0x2)\n+\t/*\n+\t * If set to 1, then EEM External Record table is supported.\n+\t * If set to 0 EEM External Record table is not supported.\n+\t * (This table includes action record, EFC pointers, encap pointers)\n+\t */\n+\t#define HWRM_CFA_EEM_QCAPS_OUTPUT_SUPPORTED_EXTERNAL_RECORD_TABLE \\\n+\t\tUINT32_C(0x4)\n+\t/*\n+\t * If set to 1, then EEM External Flow Counters table is supported.\n+\t * If set to 0 EEM External Flow Counters table is not supported.\n+\t */\n+\t#define HWRM_CFA_EEM_QCAPS_OUTPUT_SUPPORTED_EXTERNAL_FLOW_COUNTERS_TABLE \\\n+\t\tUINT32_C(0x8)\n+\t/*\n+\t * The maximum number of entries supported by EEM. When configuring the host memory\n+\t * the number of numbers of entries that can supported are -\n+\t * 32k, 64k 128k, 256k, 512k, 1M, 2M, 4M, 8M, 32M, 64M, 128M entries.\n+\t * Any value that are not these values, the FW will round down to the closest support\n+\t * number of entries.\n+\t */\n+\tuint32_t\tmax_entries_supported;\n+\t/* The entry size in bytes of each entry in the KEY0/KEY1 EEM tables. */\n+\tuint16_t\tkey_entry_size;\n+\t/* The entry size in bytes of each entry in the RECORD EEM tables. */\n+\tuint16_t\trecord_entry_size;\n+\t/* The entry size in bytes of each entry in the EFC EEM tables. */\n+\tuint16_t\tefc_entry_size;\n+\tuint8_t\tunused_1;\n+\t/*\n+\t * This field is used in Output records to indicate that the output\n+\t * is completely written to RAM. This field should be read as '1'\n+\t * to indicate that the output has been completely written.\n+\t * When writing a command completion or response to an internal processor,\n+\t * the order of writes has to be such that this field is written last.\n+\t */\n+\tuint8_t\tvalid;\n+} __attribute__((packed));\n+\n+/********************\n+ * hwrm_cfa_eem_cfg *\n+ ********************/\n+\n+\n+/* hwrm_cfa_eem_cfg_input (size:320b/40B) */\n+struct hwrm_cfa_eem_cfg_input {\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/*\n+\t * The completion ring to send the completion event on. This should\n+\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n+\t */\n+\tuint16_t\tcmpl_ring;\n+\t/*\n+\t * The sequence ID is used by the driver for tracking multiple\n+\t * commands. This ID is treated as opaque data by the firmware and\n+\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n+\t */\n+\tuint16_t\tseq_id;\n+\t/*\n+\t * The target ID of the command:\n+\t * * 0x0-0xFFF8 - The function ID\n+\t * * 0xFFF8-0xFFFE - Reserved for internal processors\n+\t * * 0xFFFF - HWRM\n+\t */\n+\tuint16_t\ttarget_id;\n+\t/*\n+\t * A physical address pointer pointing to a host buffer that the\n+\t * command's response data will be written. This can be either a host\n+\t * physical address (HPA) or a guest physical address (GPA) and must\n+\t * point to a physically contiguous block of memory.\n+\t */\n+\tuint64_t\tresp_addr;\n+\tuint32_t\tflags;\n+\t/*\n+\t * When set to 1, indicates the configuration will apply to TX flows\n+\t * which are to be offloaded.\n+\t * Note if this bit is set then the path_rx bit can't be set.\n+\t */\n+\t#define HWRM_CFA_EEM_CFG_INPUT_FLAGS_PATH_TX \\\n+\t\tUINT32_C(0x1)\n+\t/*\n+\t * When set to 1, indicates the configuration will apply to RX flows\n+\t * which are to be offloaded.\n+\t * Note if this bit is set then the path_tx bit can't be set.\n+\t */\n+\t#define HWRM_CFA_EEM_CFG_INPUT_FLAGS_PATH_RX \\\n+\t\tUINT32_C(0x2)\n+\t/* When set to 1, all offloaded flows will be sent to EEM. */\n+\t#define HWRM_CFA_EEM_CFG_INPUT_FLAGS_PREFERRED_OFFLOAD \\\n+\t\tUINT32_C(0x4)\n+\tuint32_t\tunused_0;\n+\t/*\n+\t * Configured EEM with the given number of entries. All the EEM tables KEY0, KEY1,\n+\t * RECORD, EFC all have the same number of entries and all tables will be configured\n+\t * using this value. Current minimum value is 32k. Current maximum value is 128M.\n+\t */\n+\tuint32_t\tnum_entries;\n+\tuint32_t\tunused_1;\n+\t/* Configured EEM with the given context if for KEY0 table. */\n+\tuint16_t\tkey0_ctx_id;\n+\t/* Configured EEM with the given context if for KEY1 table. */\n+\tuint16_t\tkey1_ctx_id;\n+\t/* Configured EEM with the given context if for RECORD table. */\n+\tuint16_t\trecord_ctx_id;\n+\t/* Configured EEM with the given context if for EFC table. */\n+\tuint16_t\tefc_ctx_id;\n+} __attribute__((packed));\n+\n+/* hwrm_cfa_eem_cfg_output (size:128b/16B) */\n+struct hwrm_cfa_eem_cfg_output {\n+\t/* The specific error status for the command. */\n+\tuint16_t\terror_code;\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/* The sequence ID from the original command. */\n+\tuint16_t\tseq_id;\n+\t/* The length of the response data in number of bytes. */\n+\tuint16_t\tresp_len;\n+\tuint8_t\tunused_0[7];\n+\t/*\n+\t * This field is used in Output records to indicate that the output\n+\t * is completely written to RAM. This field should be read as '1'\n+\t * to indicate that the output has been completely written.\n+\t * When writing a command completion or response to an internal processor,\n+\t * the order of writes has to be such that this field is written last.\n+\t */\n+\tuint8_t\tvalid;\n+} __attribute__((packed));\n+\n+/*********************\n+ * hwrm_cfa_eem_qcfg *\n+ *********************/\n \n \n-/* hwrm_cfa_redirect_query_tunnel_type_input (size:192b/24B) */\n-struct hwrm_cfa_redirect_query_tunnel_type_input {\n+/* hwrm_cfa_eem_qcfg_input (size:192b/24B) */\n+struct hwrm_cfa_eem_qcfg_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n \t/*\n@@ -26398,13 +28814,16 @@ struct hwrm_cfa_redirect_query_tunnel_type_input {\n \t * point to a physically contiguous block of memory.\n \t */\n \tuint64_t\tresp_addr;\n-\t/* The source function id. */\n-\tuint16_t\tsrc_fid;\n-\tuint8_t\tunused_0[6];\n+\tuint32_t\tflags;\n+\t/* When set to 1, indicates the configuration is the TX flow. */\n+\t#define HWRM_CFA_EEM_QCFG_INPUT_FLAGS_PATH_TX UINT32_C(0x1)\n+\t/* When set to 1, indicates the configuration is the RX flow. */\n+\t#define HWRM_CFA_EEM_QCFG_INPUT_FLAGS_PATH_RX UINT32_C(0x2)\n+\tuint32_t\tunused_0;\n } __attribute__((packed));\n \n-/* hwrm_cfa_redirect_query_tunnel_type_output (size:128b/16B) */\n-struct hwrm_cfa_redirect_query_tunnel_type_output {\n+/* hwrm_cfa_eem_qcfg_output (size:192b/24B) */\n+struct hwrm_cfa_eem_qcfg_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n \t/* The HWRM command request type. */\n@@ -26413,50 +28832,219 @@ struct hwrm_cfa_redirect_query_tunnel_type_output {\n \tuint16_t\tseq_id;\n \t/* The length of the response data in number of bytes. */\n \tuint16_t\tresp_len;\n-\t/* Tunnel Mask. */\n-\tuint32_t\ttunnel_mask;\n-\t/* Non-tunnel */\n-\t#define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_NONTUNNEL \\\n+\tuint32_t\tflags;\n+\t/* When set to 1, indicates the configuration is the TX flow. */\n+\t#define HWRM_CFA_EEM_QCFG_OUTPUT_FLAGS_PATH_TX \\\n \t\tUINT32_C(0x1)\n-\t/* Virtual eXtensible Local Area Network (VXLAN) */\n-\t#define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_VXLAN \\\n+\t/* When set to 1, indicates the configuration is the RX flow. */\n+\t#define HWRM_CFA_EEM_QCFG_OUTPUT_FLAGS_PATH_RX \\\n \t\tUINT32_C(0x2)\n-\t/* Network Virtualization Generic Routing Encapsulation (NVGRE) */\n-\t#define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_NVGRE \\\n+\t/* When set to 1, all offloaded flows will be sent to EEM. */\n+\t#define HWRM_CFA_EEM_QCFG_OUTPUT_FLAGS_PREFERRED_OFFLOAD \\\n \t\tUINT32_C(0x4)\n-\t/* Generic Routing Encapsulation (GRE) inside Ethernet payload */\n-\t#define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_L2GRE \\\n+\t/* The number of entries the FW has configured for EEM. */\n+\tuint32_t\tnum_entries;\n+\tuint8_t\tunused_0[7];\n+\t/*\n+\t * This field is used in Output records to indicate that the output\n+\t * is completely written to RAM. This field should be read as '1'\n+\t * to indicate that the output has been completely written.\n+\t * When writing a command completion or response to an internal processor,\n+\t * the order of writes has to be such that this field is written last.\n+\t */\n+\tuint8_t\tvalid;\n+} __attribute__((packed));\n+\n+/*******************\n+ * hwrm_cfa_eem_op *\n+ *******************/\n+\n+\n+/* hwrm_cfa_eem_op_input (size:192b/24B) */\n+struct hwrm_cfa_eem_op_input {\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/*\n+\t * The completion ring to send the completion event on. This should\n+\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n+\t */\n+\tuint16_t\tcmpl_ring;\n+\t/*\n+\t * The sequence ID is used by the driver for tracking multiple\n+\t * commands. This ID is treated as opaque data by the firmware and\n+\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n+\t */\n+\tuint16_t\tseq_id;\n+\t/*\n+\t * The target ID of the command:\n+\t * * 0x0-0xFFF8 - The function ID\n+\t * * 0xFFF8-0xFFFE - Reserved for internal processors\n+\t * * 0xFFFF - HWRM\n+\t */\n+\tuint16_t\ttarget_id;\n+\t/*\n+\t * A physical address pointer pointing to a host buffer that the\n+\t * command's response data will be written. This can be either a host\n+\t * physical address (HPA) or a guest physical address (GPA) and must\n+\t * point to a physically contiguous block of memory.\n+\t */\n+\tuint64_t\tresp_addr;\n+\tuint32_t\tflags;\n+\t/*\n+\t * When set to 1, indicates the host memory which is passed will be\n+\t * used for the TX flow offload function specified in fid.\n+\t * Note if this bit is set then the path_rx bit can't be set.\n+\t */\n+\t#define HWRM_CFA_EEM_OP_INPUT_FLAGS_PATH_TX UINT32_C(0x1)\n+\t/*\n+\t * When set to 1, indicates the host memory which is passed will be\n+\t * used for the RX flow offload function specified in fid.\n+\t * Note if this bit is set then the path_tx bit can't be set.\n+\t */\n+\t#define HWRM_CFA_EEM_OP_INPUT_FLAGS_PATH_RX UINT32_C(0x2)\n+\tuint16_t\tunused_0;\n+\t/* The number of EEM key table entries to be configured. */\n+\tuint16_t\top;\n+\t/* This value is reserved and should not be used. */\n+\t#define HWRM_CFA_EEM_OP_INPUT_OP_RESERVED UINT32_C(0x0)\n+\t/*\n+\t * To properly stop EEM and ensure there are no DMA's, the caller\n+\t * must disable EEM for the given PF, using this call. This will\n+\t * safely disable EEM and ensure that all DMA'ed to the\n+\t * keys/records/efc have been completed.\n+\t */\n+\t#define HWRM_CFA_EEM_OP_INPUT_OP_EEM_DISABLE UINT32_C(0x1)\n+\t/*\n+\t * Once the EEM host memory has been configured, EEM options have\n+\t * been configured. Then the caller should enable EEM for the given\n+\t * PF. Note once this call has been made, then the EEM mechanism\n+\t * will be active and DMA's will occur as packets are processed.\n+\t */\n+\t#define HWRM_CFA_EEM_OP_INPUT_OP_EEM_ENABLE UINT32_C(0x2)\n+\t/*\n+\t * Clear EEM settings for the given PF so that the register values\n+\t * are reset back to there initial state.\n+\t */\n+\t#define HWRM_CFA_EEM_OP_INPUT_OP_EEM_CLEANUP UINT32_C(0x3)\n+\t#define HWRM_CFA_EEM_OP_INPUT_OP_LAST \\\n+\t\tHWRM_CFA_EEM_OP_INPUT_OP_EEM_CLEANUP\n+} __attribute__((packed));\n+\n+/* hwrm_cfa_eem_op_output (size:128b/16B) */\n+struct hwrm_cfa_eem_op_output {\n+\t/* The specific error status for the command. */\n+\tuint16_t\terror_code;\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/* The sequence ID from the original command. */\n+\tuint16_t\tseq_id;\n+\t/* The length of the response data in number of bytes. */\n+\tuint16_t\tresp_len;\n+\tuint8_t\tunused_0[7];\n+\t/*\n+\t * This field is used in Output records to indicate that the output\n+\t * is completely written to RAM. This field should be read as '1'\n+\t * to indicate that the output has been completely written.\n+\t * When writing a command completion or response to an internal processor,\n+\t * the order of writes has to be such that this field is written last.\n+\t */\n+\tuint8_t\tvalid;\n+} __attribute__((packed));\n+\n+/********************************\n+ * hwrm_cfa_adv_flow_mgnt_qcaps *\n+ ********************************/\n+\n+\n+/* hwrm_cfa_adv_flow_mgnt_qcaps_input (size:256b/32B) */\n+struct hwrm_cfa_adv_flow_mgnt_qcaps_input {\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/*\n+\t * The completion ring to send the completion event on. This should\n+\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n+\t */\n+\tuint16_t\tcmpl_ring;\n+\t/*\n+\t * The sequence ID is used by the driver for tracking multiple\n+\t * commands. This ID is treated as opaque data by the firmware and\n+\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n+\t */\n+\tuint16_t\tseq_id;\n+\t/*\n+\t * The target ID of the command:\n+\t * * 0x0-0xFFF8 - The function ID\n+\t * * 0xFFF8-0xFFFE - Reserved for internal processors\n+\t * * 0xFFFF - HWRM\n+\t */\n+\tuint16_t\ttarget_id;\n+\t/*\n+\t * A physical address pointer pointing to a host buffer that the\n+\t * command's response data will be written. This can be either a host\n+\t * physical address (HPA) or a guest physical address (GPA) and must\n+\t * point to a physically contiguous block of memory.\n+\t */\n+\tuint64_t\tresp_addr;\n+\tuint32_t\tunused_0[4];\n+} __attribute__((packed));\n+\n+/* hwrm_cfa_adv_flow_mgnt_qcaps_output (size:128b/16B) */\n+struct hwrm_cfa_adv_flow_mgnt_qcaps_output {\n+\t/* The specific error status for the command. */\n+\tuint16_t\terror_code;\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/* The sequence ID from the original command. */\n+\tuint16_t\tseq_id;\n+\t/* The length of the response data in number of bytes. */\n+\tuint16_t\tresp_len;\n+\tuint32_t\tflags;\n+\t/*\n+\t * Value of 1 to indicate firmware support 16-bit flow handle.\n+\t * Value of 0 to indicate firmware not support 16-bit flow handle.\n+\t */\n+\t#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_HND_16BIT_SUPPORTED \\\n+\t\tUINT32_C(0x1)\n+\t/*\n+\t * Value of 1 to indicate firmware support 64-bit flow handle.\n+\t * Value of 0 to indicate firmware not support 64-bit flow handle.\n+\t */\n+\t#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_HND_64BIT_SUPPORTED \\\n+\t\tUINT32_C(0x2)\n+\t/*\n+\t * Value of 1 to indicate firmware support flow batch delete operation through\n+\t * HWRM_CFA_FLOW_FLUSH command.\n+\t * Value of 0 to indicate that the firmware does not support flow batch delete\n+\t * operation.\n+\t */\n+\t#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_BATCH_DELETE_SUPPORTED \\\n+\t\tUINT32_C(0x4)\n+\t/*\n+\t * Value of 1 to indicate that the firmware support flow reset all operation through\n+\t * HWRM_CFA_FLOW_FLUSH command.\n+\t * Value of 0 indicates firmware does not support flow reset all operation.\n+\t */\n+\t#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_RESET_ALL_SUPPORTED \\\n \t\tUINT32_C(0x8)\n-\t/* IP in IP */\n-\t#define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_IPIP \\\n+\t/*\n+\t * Value of 1 to indicate that firmware supports use of FID as dest_id in\n+\t * HWRM_CFA_NTUPLE_ALLOC/CFG commands.\n+\t * Value of 0 indicates firmware does not support use of FID as dest_id.\n+\t */\n+\t#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_NTUPLE_FLOW_DEST_FUNC_SUPPORTED \\\n \t\tUINT32_C(0x10)\n-\t/* Generic Network Virtualization Encapsulation (Geneve) */\n-\t#define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_GENEVE \\\n+\t/*\n+\t * Value of 1 to indicate that firmware supports TX EEM flows.\n+\t * Value of 0 indicates firmware does not support TX EEM flows.\n+\t */\n+\t#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_TX_EEM_FLOW_SUPPORTED \\\n \t\tUINT32_C(0x20)\n-\t/* Multi-Protocol Lable Switching (MPLS) */\n-\t#define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_MPLS \\\n+\t/*\n+\t * Value of 1 to indicate that firmware supports RX EEM flows.\n+\t * Value of 0 indicates firmware does not support RX EEM flows.\n+\t */\n+\t#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_RX_EEM_FLOW_SUPPORTED \\\n \t\tUINT32_C(0x40)\n-\t/* Stateless Transport Tunnel (STT) */\n-\t#define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_STT \\\n-\t\tUINT32_C(0x80)\n-\t/* Generic Routing Encapsulation (GRE) inside IP datagram payload */\n-\t#define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_IPGRE \\\n-\t\tUINT32_C(0x100)\n-\t/* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */\n-\t#define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_VXLAN_V4 \\\n-\t\tUINT32_C(0x200)\n-\t/* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */\n-\t#define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_IPGRE_V1 \\\n-\t\tUINT32_C(0x400)\n-\t/* Any tunneled traffic */\n-\t#define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_ANYTUNNEL \\\n-\t\tUINT32_C(0x800)\n-\t/* Use fixed layer 2 ether type of 0xFFFF */\n-\t#define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_L2_ETYPE \\\n-\t\tUINT32_C(0x1000)\n-\t/* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */\n-\t#define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_VXLAN_GPE_V6 \\\n-\t\tUINT32_C(0x2000)\n \tuint8_t\tunused_0[3];\n \t/*\n \t * This field is used in Output records to indicate that the output\n@@ -26874,7 +29462,11 @@ struct hwrm_stat_ctx_alloc_input {\n \t * point to a physically contiguous block of memory.\n \t */\n \tuint64_t\tresp_addr;\n-\t/* This is the address for statistic block. */\n+\t/*\n+\t * This is the address for statistic block.\n+\t * > For new versions of the chip, this address should be 128B\n+\t * > aligned.\n+\t */\n \tuint64_t\tstats_dma_addr;\n \t/*\n \t * The statistic block update period in ms.\n", "prefixes": [ "09/11" ] }