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{
    "id": 53565,
    "url": "http://patches.dpdk.org/api/patches/53565/?format=api",
    "web_url": "http://patches.dpdk.org/project/dpdk/patch/1558426944-187230-1-git-send-email-xuanziyang2@huawei.com/",
    "project": {
        "id": 1,
        "url": "http://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<1558426944-187230-1-git-send-email-xuanziyang2@huawei.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/1558426944-187230-1-git-send-email-xuanziyang2@huawei.com",
    "date": "2019-05-21T08:22:24",
    "name": "[07/11] net/hinic/base: add various headers",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": true,
    "hash": "98c707514f2f85530652b3e33186c2bfbea7156e",
    "submitter": {
        "id": 1321,
        "url": "http://patches.dpdk.org/api/people/1321/?format=api",
        "name": "Ziyang Xuan",
        "email": "xuanziyang2@huawei.com"
    },
    "delegate": {
        "id": 319,
        "url": "http://patches.dpdk.org/api/users/319/?format=api",
        "username": "fyigit",
        "first_name": "Ferruh",
        "last_name": "Yigit",
        "email": "ferruh.yigit@amd.com"
    },
    "mbox": "http://patches.dpdk.org/project/dpdk/patch/1558426944-187230-1-git-send-email-xuanziyang2@huawei.com/mbox/",
    "series": [
        {
            "id": 4727,
            "url": "http://patches.dpdk.org/api/series/4727/?format=api",
            "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=4727",
            "date": "2019-05-21T08:13:07",
            "name": "A new net PMD - hinic",
            "version": 1,
            "mbox": "http://patches.dpdk.org/series/4727/mbox/"
        }
    ],
    "comments": "http://patches.dpdk.org/api/patches/53565/comments/",
    "check": "fail",
    "checks": "http://patches.dpdk.org/api/patches/53565/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@dpdk.org",
        "Delivered-To": "patchwork@dpdk.org",
        "Received": [
            "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 20E7F4CA7;\n\tTue, 21 May 2019 10:11:50 +0200 (CEST)",
            "from huawei.com (szxga05-in.huawei.com [45.249.212.191])\n\tby dpdk.org (Postfix) with ESMTP id 9FF8F4C96\n\tfor <dev@dpdk.org>; Tue, 21 May 2019 10:11:48 +0200 (CEST)",
            "from DGGEMS405-HUB.china.huawei.com (unknown [172.30.72.58])\n\tby Forcepoint Email with ESMTP id 4D91799557137CDD124E\n\tfor <dev@dpdk.org>; Tue, 21 May 2019 16:11:47 +0800 (CST)",
            "from tester_149.localdomain (10.175.119.39) by\n\tDGGEMS405-HUB.china.huawei.com (10.3.19.205) with Microsoft SMTP\n\tServer id 14.3.439.0; Tue, 21 May 2019 16:11:38 +0800"
        ],
        "From": "Ziyang Xuan <xuanziyang2@huawei.com>",
        "To": "<dev@dpdk.org>",
        "CC": "<ferruh.yigit@intel.com>, <cloud.wangxiaoyun@huawei.com>,\n\t<zhouguoyang@huawei.com>, <rami.rosen@huawei.com>, Ziyang Xuan\n\t<xuanziyang2@huawei.com>",
        "Date": "Tue, 21 May 2019 16:22:24 +0800",
        "Message-ID": "<1558426944-187230-1-git-send-email-xuanziyang2@huawei.com>",
        "X-Mailer": "git-send-email 1.8.3.1",
        "MIME-Version": "1.0",
        "Content-Type": "text/plain",
        "X-Originating-IP": "[10.175.119.39]",
        "X-CFilter-Loop": "Reflected",
        "Subject": "[dpdk-dev] [PATCH 07/11] net/hinic/base: add various headers",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.15",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "Add various headers that define mgmt commands, cmdq commands,\nrx data structures, tx data structures and basic defines for\nuse in the code.\n\nSigned-off-by: Ziyang Xuan <xuanziyang2@huawei.com>\n---\n drivers/net/hinic/base/hinic_compat.h   | 257 +++++++++++++++++\n drivers/net/hinic/base/hinic_port_cmd.h | 494 ++++++++++++++++++++++++++++++++\n drivers/net/hinic/base/hinic_qe_def.h   | 461 +++++++++++++++++++++++++++++\n drivers/net/hinic/hinic_pmd_ethdev.h    | 106 +++++++\n drivers/net/hinic/hinic_pmd_rx.h        | 135 +++++++++\n drivers/net/hinic/hinic_pmd_tx.h        |  97 +++++++\n 6 files changed, 1550 insertions(+)\n create mode 100644 drivers/net/hinic/base/hinic_compat.h\n create mode 100644 drivers/net/hinic/base/hinic_port_cmd.h\n create mode 100644 drivers/net/hinic/base/hinic_qe_def.h\n create mode 100644 drivers/net/hinic/hinic_pmd_ethdev.h\n create mode 100644 drivers/net/hinic/hinic_pmd_rx.h\n create mode 100644 drivers/net/hinic/hinic_pmd_tx.h",
    "diff": "diff --git a/drivers/net/hinic/base/hinic_compat.h b/drivers/net/hinic/base/hinic_compat.h\nnew file mode 100644\nindex 0000000..ca42c50\n--- /dev/null\n+++ b/drivers/net/hinic/base/hinic_compat.h\n@@ -0,0 +1,257 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2017 Huawei Technologies Co., Ltd\n+ */\n+\n+#ifndef _HINIC_COMPAT_H_\n+#define _HINIC_COMPAT_H_\n+\n+#ifdef __cplusplus\n+#if __cplusplus\n+extern \"C\"{\n+#endif\n+#endif /* __cplusplus */\n+\n+#include <stdint.h>\n+#include <sys/time.h>\n+\n+#include <rte_common.h>\n+#include <rte_byteorder.h>\n+#include <rte_memzone.h>\n+#include <rte_memcpy.h>\n+#include <rte_malloc.h>\n+#include <rte_atomic.h>\n+#include <rte_spinlock.h>\n+#include <rte_cycles.h>\n+#include <rte_log.h>\n+#include <rte_config.h>\n+\n+typedef uint8_t   u8;\n+typedef int8_t    s8;\n+typedef uint16_t  u16;\n+typedef uint32_t  u32;\n+typedef int32_t   s32;\n+typedef uint64_t  u64;\n+\n+#ifndef dma_addr_t\n+typedef uint64_t  dma_addr_t;\n+#endif\n+\n+#ifndef gfp_t\n+#define gfp_t unsigned\n+#endif\n+\n+#ifndef bool\n+#define bool int\n+#endif\n+\n+#ifndef FALSE\n+#define FALSE\t(0)\n+#endif\n+\n+#ifndef TRUE\n+#define TRUE\t(1)\n+#endif\n+\n+#ifndef false\n+#define false\t(0)\n+#endif\n+\n+#ifndef true\n+#define true\t(1)\n+#endif\n+\n+#ifndef NULL\n+#define NULL ((void *)0)\n+#endif\n+\n+#define HINIC_ERROR\t(-1)\n+#define HINIC_OK\t(0)\n+\n+#ifndef BIT\n+#define BIT(n) (1 << (n))\n+#endif\n+\n+#define upper_32_bits(n) ((u32)(((n) >> 16) >> 16))\n+#define lower_32_bits(n) ((u32)(n))\n+\n+/* Returns X / Y, rounding up.  X must be nonnegative to round correctly. */\n+#define DIV_ROUND_UP(X, Y) (((X) + ((Y) - 1)) / (Y))\n+\n+/* Returns X rounded up to the nearest multiple of Y. */\n+#define ROUND_UP(X, Y) (DIV_ROUND_UP(X, Y) * (Y))\n+\n+#undef  ALIGN\n+#define ALIGN(x, a)  RTE_ALIGN(x, a)\n+\n+#undef container_of\n+#define container_of(ptr, type, member) ({ \\\n+\t\ttypeof(((type *)0)->member)(*__mptr) = (ptr); \\\n+\t\t(type *)((char *)__mptr - offsetof(type, member)); })\n+\n+#define PTR_ALIGN(p, a)\t\t((typeof(p))ALIGN((unsigned long)(p), (a)))\n+\n+/* Reported driver name. */\n+#define HINIC_DRIVER_NAME \"net_hinic\"\n+\n+extern int hinic_logtype;\n+\n+#define PMD_DRV_LOG(level, fmt, args...) \\\n+\trte_log(RTE_LOG_ ## level, hinic_logtype, \\\n+\t\tHINIC_DRIVER_NAME\": \" fmt \"\\n\", ##args)\n+\n+#define HINIC_ASSERT_EN\n+\n+#ifdef HINIC_ASSERT_EN\n+#define HINIC_ASSERT(exp)\t\\\n+\tdo {\t\t\t\\\n+\t\tif (!(exp)) {\t\\\n+\t\t\trte_panic(\"line%d\\tassert \\\"\" #exp \"\\\" failed\\n\", \\\n+\t\t\t\t  __LINE__);\t\\\n+\t\t}\t\t\\\n+\t} while (0)\n+#else\n+#define HINIC_ASSERT(exp)\tdo {} while (0)\n+#endif\n+\n+#define HINIC_BUG_ON(x) HINIC_ASSERT(!(x))\n+\n+/* common definition */\n+#ifndef ETH_ALEN\n+#define ETH_ALEN 6\n+#endif\n+#define ETH_HLEN\t\t\t14\n+#define ETH_CRC_LEN\t\t\t4\n+#define VLAN_PRIO_SHIFT\t\t\t13\n+#define VLAN_N_VID\t\t\t4096\n+\n+/* bit order interface */\n+#define cpu_to_be16(o) rte_cpu_to_be_16(o)\n+#define cpu_to_be32(o) rte_cpu_to_be_32(o)\n+#define cpu_to_be64(o) rte_cpu_to_be_64(o)\n+#define cpu_to_le32(o) rte_cpu_to_le_32(o)\n+#define be16_to_cpu(o) rte_be_to_cpu_16(o)\n+#define be32_to_cpu(o) rte_be_to_cpu_32(o)\n+#define be64_to_cpu(o) rte_be_to_cpu_64(o)\n+#define le32_to_cpu(o) rte_le_to_cpu_32(o)\n+\n+/* virt memory and dma phy memory */\n+#define __iomem\n+#define __force\n+#define GFP_KERNEL\tRTE_MEMZONE_IOVA_CONTIG\n+#define PAGE_SHIFT\t12\n+#define PAGE_SIZE\tRTE_PGSIZE_4K\n+#define HINIC_MEM_ALLOC_ALIGNE_MIN\t8\n+\n+static inline int hinic_test_bit(int nr, volatile unsigned long *addr)\n+{\n+\tint res;\n+\n+\trte_mb();\n+\tres = ((*addr) & (1UL << nr)) != 0;\n+\trte_mb();\n+\treturn res;\n+}\n+\n+static inline void hinic_set_bit(unsigned int nr, volatile unsigned long *addr)\n+{\n+\t__sync_fetch_and_or(addr, (1UL << nr));\n+}\n+\n+static inline void hinic_clear_bit(int nr, volatile unsigned long *addr)\n+{\n+\t__sync_fetch_and_and(addr, ~(1UL << nr));\n+}\n+\n+static inline int hinic_test_and_clear_bit(int nr, volatile unsigned long *addr)\n+{\n+\tunsigned long mask = (1UL << nr);\n+\n+\treturn __sync_fetch_and_and(addr, ~mask) & mask;\n+}\n+\n+static inline int hinic_test_and_set_bit(int nr, volatile unsigned long *addr)\n+{\n+\tunsigned long mask = (1UL << nr);\n+\n+\treturn __sync_fetch_and_or(addr, mask) & mask;\n+}\n+\n+void *dma_zalloc_coherent(void *dev, size_t size, dma_addr_t *dma_handle,\n+\t\t\t  gfp_t flag);\n+void *dma_zalloc_coherent_aligned(void *dev, size_t size,\n+\t\t\t\tdma_addr_t *dma_handle, gfp_t flag);\n+void *dma_zalloc_coherent_aligned256k(void *dev, size_t size,\n+\t\t\t\tdma_addr_t *dma_handle, gfp_t flag);\n+void dma_free_coherent(void *dev, size_t size, void *virt, dma_addr_t phys);\n+\n+/* dma pool alloc and free */\n+#define\tpci_pool dma_pool\n+#define\tpci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle)\n+#define\tpci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr)\n+\n+struct dma_pool *dma_pool_create(const char *name, void *dev, size_t size,\n+\t\t\t\tsize_t align, size_t boundary);\n+void dma_pool_destroy(struct dma_pool *pool);\n+void *dma_pool_alloc(struct pci_pool *pool, int flags, dma_addr_t *dma_addr);\n+void dma_pool_free(struct pci_pool *pool, void *vaddr, dma_addr_t dma);\n+\n+#define kzalloc(size, flag) rte_zmalloc(NULL, size, HINIC_MEM_ALLOC_ALIGNE_MIN)\n+#define kzalloc_aligned(size, flag) rte_zmalloc(NULL, size, RTE_CACHE_LINE_SIZE)\n+#define kfree(ptr)            rte_free(ptr)\n+\n+/* mmio interface */\n+static inline void writel(u32 value, volatile void  *addr)\n+{\n+\t*(volatile u32 *)addr = value;\n+}\n+\n+static inline u32 readl(const volatile void *addr)\n+{\n+\treturn *(const volatile u32 *)addr;\n+}\n+\n+#define __raw_writel(value, reg) writel((value), (reg))\n+#define __raw_readl(reg) readl((reg))\n+\n+/* Spinlock related interface */\n+#define hinic_spinlock_t rte_spinlock_t\n+\n+#define spinlock_t rte_spinlock_t\n+#define spin_lock_init(spinlock_prt)\trte_spinlock_init(spinlock_prt)\n+#define spin_lock_deinit(lock)\n+#define spin_lock(spinlock_prt)\t\trte_spinlock_lock(spinlock_prt)\n+#define spin_unlock(spinlock_prt)\trte_spinlock_unlock(spinlock_prt)\n+\n+static inline unsigned long get_timeofday_ms(void)\n+{\n+\tstruct timeval tv;\n+\n+\t(void)gettimeofday(&tv, NULL);\n+\n+\treturn (unsigned long)tv.tv_sec * 1000 + tv.tv_usec / 1000;\n+}\n+\n+#define jiffies\tget_timeofday_ms()\n+#define msecs_to_jiffies(ms)\t(ms)\n+#define time_before(now, end)\t((now) < (end))\n+\n+/* misc kernel utils */\n+static inline u16 ilog2(u32 n)\n+{\n+\tu16 res = 0;\n+\n+\twhile (n > 1) {\n+\t\tn >>= 1;\n+\t\tres++;\n+\t}\n+\n+\treturn res;\n+}\n+\n+#ifdef __cplusplus\n+#if __cplusplus\n+}\n+#endif\n+#endif /* __cplusplus */\n+\n+#endif /* _HINIC_COMPAT_H_ */\ndiff --git a/drivers/net/hinic/base/hinic_port_cmd.h b/drivers/net/hinic/base/hinic_port_cmd.h\nnew file mode 100644\nindex 0000000..f0db19f\n--- /dev/null\n+++ b/drivers/net/hinic/base/hinic_port_cmd.h\n@@ -0,0 +1,494 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2017 Huawei Technologies Co., Ltd\n+ */\n+\n+#ifndef _HINIC_PORT_CMD_H_\n+#define _HINIC_PORT_CMD_H_\n+\n+#ifdef __cplusplus\n+    #if __cplusplus\n+extern \"C\"{\n+    #endif\n+#endif /* __cplusplus */\n+\n+/* cmd of mgmt CPU message for NIC module */\n+enum hinic_port_cmd {\n+\tHINIC_PORT_CMD_MGMT_RESET\t\t= 0x0,\n+\n+\tHINIC_PORT_CMD_CHANGE_MTU\t\t= 0x2,\n+\n+\tHINIC_PORT_CMD_ADD_VLAN\t\t\t= 0x3,\n+\tHINIC_PORT_CMD_DEL_VLAN,\n+\n+\tHINIC_PORT_CMD_SET_PFC\t\t\t= 0x5,\n+\tHINIC_PORT_CMD_GET_PFC,\n+\tHINIC_PORT_CMD_SET_ETS,\n+\tHINIC_PORT_CMD_GET_ETS,\n+\n+\tHINIC_PORT_CMD_SET_MAC\t\t\t= 0x9,\n+\tHINIC_PORT_CMD_GET_MAC,\n+\tHINIC_PORT_CMD_DEL_MAC,\n+\n+\tHINIC_PORT_CMD_SET_RX_MODE\t\t= 0xc,\n+\tHINIC_PORT_CMD_SET_ANTI_ATTACK_RATE\t= 0xd,\n+\n+\tHINIC_PORT_CMD_GET_AUTONEG_CAP\t\t= 0xf,\n+\t/* not defined in base line */\n+\tHINIC_PORT_CMD_GET_AUTONET_STATE,\n+\t/* not defined in base line */\n+\tHINIC_PORT_CMD_GET_SPEED,\n+\t/* not defined in base line */\n+\tHINIC_PORT_CMD_GET_DUPLEX,\n+\t/* not defined in base line */\n+\tHINIC_PORT_CMD_GET_MEDIA_TYPE,\n+\t/* not defined in base line */\n+\n+\tHINIC_PORT_CMD_GET_PAUSE_INFO\t\t= 0x14,\n+\tHINIC_PORT_CMD_SET_PAUSE_INFO,\n+\n+\tHINIC_PORT_CMD_GET_LINK_STATE\t\t= 0x18,\n+\tHINIC_PORT_CMD_SET_LRO\t\t\t= 0x19,\n+\tHINIC_PORT_CMD_SET_RX_CSUM\t\t= 0x1a,\n+\tHINIC_PORT_CMD_SET_RX_VLAN_OFFLOAD\t= 0x1b,\n+\n+\tHINIC_PORT_CMD_GET_PORT_STATISTICS\t= 0x1c,\n+\tHINIC_PORT_CMD_CLEAR_PORT_STATISTICS,\n+\tHINIC_PORT_CMD_GET_VPORT_STAT,\n+\tHINIC_PORT_CMD_CLEAN_VPORT_STAT,\n+\n+\tHINIC_PORT_CMD_GET_RSS_TEMPLATE_INDIR_TBL = 0x25,\n+\tHINIC_PORT_CMD_SET_RSS_TEMPLATE_INDIR_TBL,\n+\n+\tHINIC_PORT_CMD_SET_PORT_ENABLE\t\t= 0x29,\n+\tHINIC_PORT_CMD_GET_PORT_ENABLE,\n+\n+\tHINIC_PORT_CMD_SET_RSS_TEMPLATE_TBL\t= 0x2b,\n+\tHINIC_PORT_CMD_GET_RSS_TEMPLATE_TBL,\n+\tHINIC_PORT_CMD_SET_RSS_HASH_ENGINE,\n+\tHINIC_PORT_CMD_GET_RSS_HASH_ENGINE,\n+\tHINIC_PORT_CMD_GET_RSS_CTX_TBL,\n+\tHINIC_PORT_CMD_SET_RSS_CTX_TBL,\n+\tHINIC_PORT_CMD_RSS_TEMP_MGR,\n+\n+\t/* 0x36 ~ 0x40 have defined in base line*/\n+\tHINIC_PORT_CMD_RSS_CFG\t\t\t= 0x42,\n+\n+\tHINIC_PORT_CMD_GET_PHY_TYPE\t\t= 0x44,\n+\tHINIC_PORT_CMD_INIT_FUNC\t\t= 0x45,\n+\tHINIC_PORT_CMD_SET_LLI_PRI\t\t= 0x46,\n+\n+\tHINIC_PORT_CMD_GET_LOOPBACK_MODE\t= 0x48,\n+\tHINIC_PORT_CMD_SET_LOOPBACK_MODE,\n+\n+\tHINIC_PORT_CMD_GET_JUMBO_FRAME_SIZE\t= 0x4a,\n+\tHINIC_PORT_CMD_SET_JUMBO_FRAME_SIZE,\n+\n+\t/* 0x4c ~ 0x57 have defined in base line*/\n+\n+\tHINIC_PORT_CMD_GET_MGMT_VERSION\t\t= 0x58,\n+\tHINIC_PORT_CMD_GET_BOOT_VERSION,\n+\tHINIC_PORT_CMD_GET_MICROCODE_VERSION,\n+\n+\tHINIC_PORT_CMD_GET_PORT_TYPE\t\t= 0x5b,\n+\n+\t/* not defined in base line */\n+\tHINIC_PORT_CMD_GET_VPORT_ENABLE\t\t= 0x5c,\n+\tHINIC_PORT_CMD_SET_VPORT_ENABLE,\n+\n+\tHINIC_PORT_CMD_GET_PORT_ID_BY_FUNC_ID\t= 0x5e,\n+\n+\tHINIC_PORT_CMD_SET_LED_TEST\t\t= 0x5f,\n+\n+\tHINIC_PORT_CMD_SET_LLI_STATE\t\t= 0x60,\n+\tHINIC_PORT_CMD_SET_LLI_TYPE,\n+\tHINIC_PORT_CMD_GET_LLI_CFG,\n+\n+\tHINIC_PORT_CMD_GET_LRO\t\t\t= 0x63,\n+\n+\tHINIC_PORT_CMD_GET_DMA_CS\t\t= 0x64,\n+\tHINIC_PORT_CMD_SET_DMA_CS,\n+\n+\tHINIC_PORT_CMD_GET_GLOBAL_QPN\t\t= 0x66,\n+\n+\tHINIC_PORT_CMD_SET_PFC_MISC\t\t= 0x67,\n+\tHINIC_PORT_CMD_GET_PFC_MISC,\n+\n+\tHINIC_PORT_CMD_SET_VF_RATE\t\t= 0x69,\n+\tHINIC_PORT_CMD_SET_VF_VLAN,\n+\tHINIC_PORT_CMD_CLR_VF_VLAN,\n+\n+\t/* 0x6c,0x6e have defined in base line*/\n+\tHINIC_PORT_CMD_SET_UCAPTURE_OPT\t\t= 0x6F,\n+\n+\tHINIC_PORT_CMD_SET_TSO\t\t\t= 0x70,\n+\tHINIC_PORT_CMD_SET_PHY_POWER\t\t= 0x71,\n+\tHINIC_PORT_CMD_UPDATE_FW\t\t= 0x72,\n+\tHINIC_PORT_CMD_SET_RQ_IQ_MAP\t\t= 0x73,\n+\t/* not defined in base line */\n+\tHINIC_PORT_CMD_SET_PFC_THD\t\t= 0x75,\n+\t/* not defined in base line */\n+\n+\tHINIC_PORT_CMD_LINK_STATUS_REPORT\t= 0xa0,\n+\n+\tHINIC_PORT_CMD_SET_LOSSLESS_ETH\t\t= 0xa3,\n+\tHINIC_PORT_CMD_UPDATE_MAC\t\t= 0xa4,\n+\n+\tHINIC_PORT_CMD_GET_UART_LOG\t\t= 0xa5,\n+\tHINIC_PORT_CMD_SET_UART_LOG,\n+\n+\tHINIC_PORT_CMD_GET_PORT_INFO\t\t= 0xaa,\n+\n+\tHINIC_MISC_SET_FUNC_SF_ENBITS\t\t= 0xab,\n+\t/* not defined in base line */\n+\tHINIC_MISC_GET_FUNC_SF_ENBITS,\n+\t/* not defined in base line */\n+\n+\tHINIC_PORT_CMD_GET_SFP_INFO\t\t= 0xad,\n+\tHINIC_PORT_CMD_GET_FW_LOG\t\t= 0xca,\n+\tHINIC_PORT_CMD_SET_IPSU_MAC\t\t= 0xcb,\n+\tHINIC_PORT_CMD_GET_IPSU_MAC\t\t= 0xcc,\n+\n+\tHINIC_PORT_CMD_SET_IQ_ENABLE\t\t= 0xd6,\n+\n+\tHINIC_PORT_CMD_GET_LINK_MODE\t\t= 0xD9,\n+\tHINIC_PORT_CMD_SET_SPEED\t\t= 0xDA,\n+\tHINIC_PORT_CMD_SET_AUTONEG\t\t= 0xDB,\n+\n+\tHINIC_PORT_CMD_CLEAR_QP_RES\t\t= 0xDD,\n+\tHINIC_PORT_CMD_SET_SUPER_CQE\t\t= 0xDE,\n+\tHINIC_PORT_CMD_SET_VF_COS\t\t= 0xDF,\n+\tHINIC_PORT_CMD_GET_VF_COS\t\t= 0xE1,\n+\n+\tHINIC_PORT_CMD_CABLE_PLUG_EVENT\t\t= 0xE5,\n+\tHINIC_PORT_CMD_LINK_ERR_EVENT\t\t= 0xE6,\n+\n+\tHINIC_PORT_CMD_SET_PORT_FUNCS_STATE\t= 0xE7,\n+\tHINIC_PORT_CMD_SET_COS_UP_MAP\t\t= 0xE8,\n+\n+\tHINIC_PORT_CMD_RESET_LINK_CFG\t\t= 0xEB,\n+\tHINIC_PORT_CMD_GET_STD_SFP_INFO\t\t= 0xF0,\n+\n+\tHINIC_PORT_CMD_FORCE_PKT_DROP\t\t= 0xF3,\n+\tHINIC_PORT_CMD_SET_LRO_TIMER\t\t= 0xF4,\n+\n+\tHINIC_PORT_CMD_SET_VHD_CFG\t\t= 0xF7,\n+\tHINIC_PORT_CMD_SET_LINK_FOLLOW\t\t= 0xF8,\n+\tHINIC_PORT_CMD_SET_VF_MAX_MIN_RATE\t= 0xF9,\n+\tHINIC_PORT_CMD_SET_RXQ_LRO_ADPT\t\t= 0xFA,\n+\tHINIC_PORT_CMD_SET_Q_FILTER\t\t= 0xFC,\n+\tHINIC_PORT_CMD_SET_VLAN_FILTER\t\t= 0xFF\n+};\n+\n+/* cmd of mgmt CPU message for HW module */\n+enum hinic_mgmt_cmd {\n+\tHINIC_MGMT_CMD_RESET_MGMT\t\t= 0x0,\n+\tHINIC_MGMT_CMD_START_FLR\t\t= 0x1,\n+\tHINIC_MGMT_CMD_FLUSH_DOORBELL\t\t= 0x2,\n+\tHINIC_MGMT_CMD_GET_IO_STATUS\t\t= 0x3,\n+\tHINIC_MGMT_CMD_DMA_ATTR_SET\t\t= 0x4,\n+\n+\tHINIC_MGMT_CMD_CMDQ_CTXT_SET\t\t= 0x10,\n+\tHINIC_MGMT_CMD_CMDQ_CTXT_GET,\n+\n+\tHINIC_MGMT_CMD_VAT_SET\t\t\t= 0x12,\n+\tHINIC_MGMT_CMD_VAT_GET,\n+\n+\tHINIC_MGMT_CMD_L2NIC_SQ_CI_ATTR_SET\t= 0x14,\n+\tHINIC_MGMT_CMD_L2NIC_SQ_CI_ATTR_GET,\n+\n+\tHINIC_MGMT_CMD_PPF_HT_GPA_SET\t\t= 0x23,\n+\tHINIC_MGMT_CMD_RES_STATE_SET\t\t= 0x24,\n+\tHINIC_MGMT_CMD_FUNC_CACHE_OUT\t\t= 0x25,\n+\tHINIC_MGMT_CMD_FFM_SET\t\t\t= 0x26,\n+\n+\t/* 0x29 not defined in base line,\n+\t * only used in open source driver\n+\t */\n+\tHINIC_MGMT_CMD_FUNC_RES_CLEAR\t\t= 0x29,\n+\n+\tHINIC_MGMT_CMD_CEQ_CTRL_REG_WR_BY_UP\t= 0x33,\n+\tHINIC_MGMT_CMD_MSI_CTRL_REG_WR_BY_UP,\n+\tHINIC_MGMT_CMD_MSI_CTRL_REG_RD_BY_UP,\n+\n+\tHINIC_MGMT_CMD_VF_RANDOM_ID_SET\t\t= 0x36,\n+\tHINIC_MGMT_CMD_FAULT_REPORT\t\t= 0x37,\n+\tHINIC_MGMT_CMD_HEART_LOST_REPORT\t= 0x38,\n+\n+\tHINIC_MGMT_CMD_VPD_SET\t\t\t= 0x40,\n+\tHINIC_MGMT_CMD_VPD_GET,\n+\tHINIC_MGMT_CMD_LABEL_SET,\n+\tHINIC_MGMT_CMD_LABEL_GET,\n+\tHINIC_MGMT_CMD_SATIC_MAC_SET,\n+\tHINIC_MGMT_CMD_SATIC_MAC_GET,\n+\tHINIC_MGMT_CMD_SYNC_TIME\t\t= 0x46,\n+\tHINIC_MGMT_CMD_SET_LED_STATUS\t\t= 0x4A,\n+\tHINIC_MGMT_CMD_L2NIC_RESET\t\t= 0x4b,\n+\tHINIC_MGMT_CMD_FAST_RECYCLE_MODE_SET\t= 0x4d,\n+\tHINIC_MGMT_CMD_BIOS_NV_DATA_MGMT\t= 0x4E,\n+\tHINIC_MGMT_CMD_ACTIVATE_FW\t\t= 0x4F,\n+\tHINIC_MGMT_CMD_PAGESIZE_SET\t\t= 0x50,\n+\tHINIC_MGMT_CMD_PAGESIZE_GET\t\t= 0x51,\n+\tHINIC_MGMT_CMD_GET_BOARD_INFO\t\t= 0x52,\n+\tHINIC_MGMT_CMD_WATCHDOG_INFO\t\t= 0x56,\n+\tHINIC_MGMT_CMD_FMW_ACT_NTC\t\t= 0x57,\n+\tHINIC_MGMT_CMD_SET_VF_RANDOM_ID\t\t= 0x61,\n+\tHINIC_MGMT_CMD_GET_PPF_STATE\t\t= 0x63,\n+\tHINIC_MGMT_CMD_PCIE_DFX_NTC\t\t= 0x65,\n+\tHINIC_MGMT_CMD_PCIE_DFX_GET\t\t= 0x66,\n+\n+\tHINIC_MGMT_CMD_GET_HOST_INFO\t\t= 0x67,\n+\n+\tHINIC_MGMT_CMD_GET_PHY_INIT_STATUS\t= 0x6A,\n+\tHINIC_MGMT_CMD_GET_HW_PF_INFOS\t\t= 0x6D,\n+};\n+\n+/* uCode related commands */\n+enum hinic_ucode_cmd {\n+\tHINIC_UCODE_CMD_MDY_QUEUE_CONTEXT\t= 0,\n+\tHINIC_UCODE_CMD_CLEAN_QUEUE_CONTEXT,\n+\tHINIC_UCODE_CMD_ARM_SQ,\n+\tHINIC_UCODE_CMD_ARM_RQ,\n+\tHINIC_UCODE_CMD_SET_RSS_INDIR_TABLE,\n+\tHINIC_UCODE_CMD_SET_RSS_CONTEXT_TABLE,\n+\tHINIC_UCODE_CMD_GET_RSS_INDIR_TABLE,\n+\tHINIC_UCODE_CMD_GET_RSS_CONTEXT_TABLE,\n+\tHINIC_UCODE_CMD_SET_IQ_ENABLE,\n+\tHINIC_UCODE_CMD_SET_RQ_FLUSH\t\t= 10\n+};\n+\n+enum sq_l4offload_type {\n+\tOFFLOAD_DISABLE   = 0,\n+\tTCP_OFFLOAD_ENABLE  = 1,\n+\tSCTP_OFFLOAD_ENABLE = 2,\n+\tUDP_OFFLOAD_ENABLE  = 3,\n+};\n+\n+enum sq_vlan_offload_flag {\n+\tVLAN_OFFLOAD_DISABLE = 0,\n+\tVLAN_OFFLOAD_ENABLE  = 1,\n+};\n+\n+enum sq_pkt_parsed_flag {\n+\tPKT_NOT_PARSED = 0,\n+\tPKT_PARSED     = 1,\n+};\n+\n+enum sq_l3_type {\n+\tUNKNOWN_L3TYPE = 0,\n+\tIPV6_PKT = 1,\n+\tIPV4_PKT_NO_CHKSUM_OFFLOAD = 2,\n+\tIPV4_PKT_WITH_CHKSUM_OFFLOAD = 3,\n+};\n+\n+enum sq_md_type {\n+\tUNKNOWN_MD_TYPE = 0,\n+};\n+\n+enum sq_l2type {\n+\tETHERNET = 0,\n+};\n+\n+enum sq_tunnel_l4_type {\n+\tNOT_TUNNEL,\n+\tTUNNEL_UDP_NO_CSUM,\n+\tTUNNEL_UDP_CSUM,\n+};\n+\n+#define NIC_RSS_CMD_TEMP_ALLOC  0x01\n+#define NIC_RSS_CMD_TEMP_FREE   0x02\n+\n+#define HINIC_RSS_TYPE_VALID_SHIFT\t\t\t23\n+#define HINIC_RSS_TYPE_TCP_IPV6_EXT_SHIFT\t\t24\n+#define HINIC_RSS_TYPE_IPV6_EXT_SHIFT\t\t\t25\n+#define HINIC_RSS_TYPE_TCP_IPV6_SHIFT\t\t\t26\n+#define HINIC_RSS_TYPE_IPV6_SHIFT\t\t\t27\n+#define HINIC_RSS_TYPE_TCP_IPV4_SHIFT\t\t\t28\n+#define HINIC_RSS_TYPE_IPV4_SHIFT\t\t\t29\n+#define HINIC_RSS_TYPE_UDP_IPV6_SHIFT\t\t\t30\n+#define HINIC_RSS_TYPE_UDP_IPV4_SHIFT\t\t\t31\n+\n+#define HINIC_RSS_TYPE_SET(val, member)\t\t\\\n+\t\t(((u32)(val) & 0x1) << HINIC_RSS_TYPE_##member##_SHIFT)\n+\n+#define HINIC_RSS_TYPE_GET(val, member)\t\t\\\n+\t\t(((u32)(val) >> HINIC_RSS_TYPE_##member##_SHIFT) & 0x1)\n+\n+enum hinic_speed {\n+\tHINIC_SPEED_10MB_LINK = 0,\n+\tHINIC_SPEED_100MB_LINK,\n+\tHINIC_SPEED_1000MB_LINK,\n+\tHINIC_SPEED_10GB_LINK,\n+\tHINIC_SPEED_25GB_LINK,\n+\tHINIC_SPEED_40GB_LINK,\n+\tHINIC_SPEED_100GB_LINK,\n+\tHINIC_SPEED_UNKNOWN = 0xFF,\n+};\n+\n+enum {\n+\tHINIC_IFLA_VF_LINK_STATE_AUTO,\t/* link state of the uplink */\n+\tHINIC_IFLA_VF_LINK_STATE_ENABLE, /* link always up */\n+\tHINIC_IFLA_VF_LINK_STATE_DISABLE, /* link always down */\n+};\n+\n+#define HINIC_AF0_FUNC_GLOBAL_IDX_SHIFT\t\t0\n+#define HINIC_AF0_P2P_IDX_SHIFT\t\t\t10\n+#define HINIC_AF0_PCI_INTF_IDX_SHIFT\t\t14\n+#define HINIC_AF0_VF_IN_PF_SHIFT\t\t16\n+#define HINIC_AF0_FUNC_TYPE_SHIFT\t\t24\n+\n+#define HINIC_AF0_FUNC_GLOBAL_IDX_MASK\t\t0x3FF\n+#define HINIC_AF0_P2P_IDX_MASK\t\t\t0xF\n+#define HINIC_AF0_PCI_INTF_IDX_MASK\t\t0x3\n+#define HINIC_AF0_VF_IN_PF_MASK\t\t\t0xFF\n+#define HINIC_AF0_FUNC_TYPE_MASK\t\t0x1\n+\n+#define HINIC_AF0_GET(val, member)\t\t\t\t\\\n+\t(((val) >> HINIC_AF0_##member##_SHIFT) & HINIC_AF0_##member##_MASK)\n+\n+#define HINIC_AF1_PPF_IDX_SHIFT\t\t\t0\n+#define HINIC_AF1_AEQS_PER_FUNC_SHIFT\t\t8\n+#define HINIC_AF1_CEQS_PER_FUNC_SHIFT\t\t12\n+#define HINIC_AF1_IRQS_PER_FUNC_SHIFT\t\t20\n+#define HINIC_AF1_DMA_ATTR_PER_FUNC_SHIFT\t24\n+#define HINIC_AF1_MGMT_INIT_STATUS_SHIFT\t30\n+#define HINIC_AF1_PF_INIT_STATUS_SHIFT\t\t31\n+\n+#define HINIC_AF1_PPF_IDX_MASK\t\t\t0x1F\n+#define HINIC_AF1_AEQS_PER_FUNC_MASK\t\t0x3\n+#define HINIC_AF1_CEQS_PER_FUNC_MASK\t\t0x7\n+#define HINIC_AF1_IRQS_PER_FUNC_MASK\t\t0xF\n+#define HINIC_AF1_DMA_ATTR_PER_FUNC_MASK\t0x7\n+#define HINIC_AF1_MGMT_INIT_STATUS_MASK\t\t0x1\n+#define HINIC_AF1_PF_INIT_STATUS_MASK\t\t0x1\n+\n+#define HINIC_AF1_GET(val, member)\t\t\t\t\\\n+\t(((val) >> HINIC_AF1_##member##_SHIFT) & HINIC_AF1_##member##_MASK)\n+\n+#define HINIC_AF2_GLOBAL_VF_ID_OF_PF_SHIFT\t16\n+#define HINIC_AF2_GLOBAL_VF_ID_OF_PF_MASK\t0x3FF\n+\n+#define HINIC_AF2_GET(val, member)\t\t\t\t\\\n+\t(((val) >> HINIC_AF2_##member##_SHIFT) & HINIC_AF2_##member##_MASK)\n+\n+#define HINIC_AF4_OUTBOUND_CTRL_SHIFT\t\t0\n+#define HINIC_AF4_DOORBELL_CTRL_SHIFT\t\t1\n+#define HINIC_AF4_OUTBOUND_CTRL_MASK\t\t0x1\n+#define HINIC_AF4_DOORBELL_CTRL_MASK\t\t0x1\n+\n+#define HINIC_AF4_GET(val, member)\t\t\t\t\\\n+\t(((val) >> HINIC_AF4_##member##_SHIFT) & HINIC_AF4_##member##_MASK)\n+\n+#define HINIC_AF4_SET(val, member)\t\t\t\t\\\n+\t(((val) & HINIC_AF4_##member##_MASK) << HINIC_AF4_##member##_SHIFT)\n+\n+#define HINIC_AF4_CLEAR(val, member)\t\t\t\t\\\n+\t((val) & (~(HINIC_AF4_##member##_MASK <<\t\t\\\n+\tHINIC_AF4_##member##_SHIFT)))\n+\n+#define HINIC_AF5_PF_STATUS_SHIFT\t\t0\n+#define HINIC_AF5_PF_STATUS_MASK\t\t0xFFFF\n+\n+#define HINIC_AF5_SET(val, member)\t\t\t\t\\\n+\t(((val) & HINIC_AF5_##member##_MASK) << HINIC_AF5_##member##_SHIFT)\n+\n+#define HINIC_AF5_GET(val, member)\t\t\t\t\\\n+\t(((val) >> HINIC_AF5_##member##_SHIFT) & HINIC_AF5_##member##_MASK)\n+\n+#define HINIC_AF5_CLEAR(val, member)\t\t\t\t\\\n+\t((val) & (~(HINIC_AF5_##member##_MASK <<\t\t\\\n+\tHINIC_AF5_##member##_SHIFT)))\n+\n+#define HINIC_PPF_ELECTION_IDX_SHIFT\t\t0\n+\n+#define HINIC_PPF_ELECTION_IDX_MASK\t\t0x1F\n+\n+#define HINIC_PPF_ELECTION_SET(val, member)\t\t\t\\\n+\t(((val) & HINIC_PPF_ELECTION_##member##_MASK) <<\t\\\n+\t\tHINIC_PPF_ELECTION_##member##_SHIFT)\n+\n+#define HINIC_PPF_ELECTION_GET(val, member)\t\t\t\\\n+\t(((val) >> HINIC_PPF_ELECTION_##member##_SHIFT) &\t\\\n+\t\tHINIC_PPF_ELECTION_##member##_MASK)\n+\n+#define HINIC_PPF_ELECTION_CLEAR(val, member)\t\t\t\\\n+\t((val) & (~(HINIC_PPF_ELECTION_##member##_MASK\t\\\n+\t\t<< HINIC_PPF_ELECTION_##member##_SHIFT)))\n+\n+#define HINIC_MPF_ELECTION_IDX_SHIFT\t\t0\n+\n+#define HINIC_MPF_ELECTION_IDX_MASK\t\t0x1F\n+\n+#define HINIC_MPF_ELECTION_SET(val, member)\t\t\t\\\n+\t(((val) & HINIC_MPF_ELECTION_##member##_MASK) <<\t\\\n+\t\tHINIC_MPF_ELECTION_##member##_SHIFT)\n+\n+#define HINIC_MPF_ELECTION_GET(val, member)\t\t\t\\\n+\t(((val) >> HINIC_MPF_ELECTION_##member##_SHIFT) &\t\\\n+\t\tHINIC_MPF_ELECTION_##member##_MASK)\n+\n+#define HINIC_MPF_ELECTION_CLEAR(val, member)\t\t\t\\\n+\t((val) & (~(HINIC_MPF_ELECTION_##member##_MASK\t\\\n+\t\t<< HINIC_MPF_ELECTION_##member##_SHIFT)))\n+\n+#define HINIC_HWIF_NUM_AEQS(hwif)\t\t((hwif)->attr.num_aeqs)\n+#define HINIC_HWIF_NUM_CEQS(hwif)\t\t((hwif)->attr.num_ceqs)\n+#define HINIC_HWIF_NUM_IRQS(hwif)\t\t((hwif)->attr.num_irqs)\n+#define HINIC_HWIF_GLOBAL_IDX(hwif)\t\t((hwif)->attr.func_global_idx)\n+#define HINIC_HWIF_GLOBAL_VF_OFFSET(hwif) ((hwif)->attr.global_vf_id_of_pf)\n+#define HINIC_HWIF_PPF_IDX(hwif)\t\t((hwif)->attr.ppf_idx)\n+#define HINIC_PCI_INTF_IDX(hwif)\t\t((hwif)->attr.pci_intf_idx)\n+\n+#define HINIC_FUNC_TYPE(dev)\t\t((dev)->hwif->attr.func_type)\n+#define HINIC_IS_PF(dev)\t\t(HINIC_FUNC_TYPE(dev) == TYPE_PF)\n+#define HINIC_IS_VF(dev)\t\t(HINIC_FUNC_TYPE(dev) == TYPE_VF)\n+#define HINIC_IS_PPF(dev)\t\t(HINIC_FUNC_TYPE(dev) == TYPE_PPF)\n+\n+#define DB_IDX(db, db_base)\t\\\n+\t((u32)(((unsigned long)(db) - (unsigned long)(db_base)) /\t\\\n+\tHINIC_DB_PAGE_SIZE))\n+\n+enum hinic_pcie_nosnoop {\n+\tHINIC_PCIE_SNOOP = 0,\n+\tHINIC_PCIE_NO_SNOOP = 1,\n+};\n+\n+enum hinic_pcie_tph {\n+\tHINIC_PCIE_TPH_DISABLE = 0,\n+\tHINIC_PCIE_TPH_ENABLE = 1,\n+};\n+\n+enum hinic_outbound_ctrl {\n+\tENABLE_OUTBOUND  = 0x0,\n+\tDISABLE_OUTBOUND = 0x1,\n+};\n+\n+enum hinic_doorbell_ctrl {\n+\tENABLE_DOORBELL  = 0x0,\n+\tDISABLE_DOORBELL = 0x1,\n+};\n+\n+enum hinic_pf_status {\n+\tHINIC_PF_STATUS_INIT = 0X0,\n+\tHINIC_PF_STATUS_ACTIVE_FLAG = 0x11,\n+\tHINIC_PF_STATUS_FLR_START_FLAG = 0x12,\n+\tHINIC_PF_STATUS_FLR_FINISH_FLAG = 0x13,\n+};\n+\n+/* total doorbell or direct wqe size is 512kB, db num: 128, dwqe: 128 */\n+#define HINIC_DB_DWQE_SIZE       0x00080000\n+\n+/* db/dwqe page size: 4K */\n+#define HINIC_DB_PAGE_SIZE\t\t0x00001000ULL\n+\n+#define HINIC_DB_MAX_AREAS         (HINIC_DB_DWQE_SIZE / HINIC_DB_PAGE_SIZE)\n+\n+#define HINIC_PCI_MSIX_ENTRY_SIZE\t\t\t16\n+#define HINIC_PCI_MSIX_ENTRY_VECTOR_CTRL\t\t12\n+#define HINIC_PCI_MSIX_ENTRY_CTRL_MASKBIT\t\t1\n+\n+#ifdef __cplusplus\n+    #if __cplusplus\n+}\n+    #endif\n+#endif /* __cplusplus */\n+#endif /* _HINIC_PORT_CMD_H_ */\ndiff --git a/drivers/net/hinic/base/hinic_qe_def.h b/drivers/net/hinic/base/hinic_qe_def.h\nnew file mode 100644\nindex 0000000..3e1dd22\n--- /dev/null\n+++ b/drivers/net/hinic/base/hinic_qe_def.h\n@@ -0,0 +1,461 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2017 Huawei Technologies Co., Ltd\n+ */\n+\n+#ifndef _HINIC_QE_DEF_H_\n+#define _HINIC_QE_DEF_H_\n+\n+#ifdef __cplusplus\n+    #if __cplusplus\n+extern \"C\"{\n+    #endif\n+#endif /* __cplusplus */\n+\n+#define HINIC_SQ_WQEBB_SIZE\t64\n+#define HINIC_RQ_WQE_SIZE\t32\n+#define HINIC_SQ_WQEBB_SHIFT\t6\n+#define HINIC_RQ_WQEBB_SHIFT\t5\n+\n+#define HINIC_MAX_QUEUE_DEPTH\t\t4096\n+#define HINIC_MIN_QUEUE_DEPTH\t\t128\n+#define HINIC_TXD_ALIGN                 1\n+#define HINIC_RXD_ALIGN                 1\n+\n+#define HINIC_SQ_DEPTH\t\t\t1024\n+#define HINIC_RQ_DEPTH\t\t\t1024\n+\n+#define HINIC_RQ_WQE_MAX_SIZE\t\t32\n+\n+#define SIZE_8BYTES(size)\t(ALIGN((u32)(size), 8) >> 3)\n+\n+/* SQ_CTRL */\n+#define SQ_CTRL_BUFDESC_SECT_LEN_SHIFT\t\t0\n+#define SQ_CTRL_TASKSECT_LEN_SHIFT\t\t16\n+#define SQ_CTRL_DATA_FORMAT_SHIFT\t\t22\n+#define SQ_CTRL_LEN_SHIFT\t\t\t29\n+#define SQ_CTRL_OWNER_SHIFT\t\t\t31\n+\n+#define SQ_CTRL_BUFDESC_SECT_LEN_MASK\t\t0xFFU\n+#define SQ_CTRL_TASKSECT_LEN_MASK\t\t0x1FU\n+#define SQ_CTRL_DATA_FORMAT_MASK\t\t0x1U\n+#define SQ_CTRL_LEN_MASK\t\t\t0x3U\n+#define SQ_CTRL_OWNER_MASK\t\t\t0x1U\n+\n+#define SQ_CTRL_GET(val, member)\t(((val) >> SQ_CTRL_##member##_SHIFT) \\\n+\t\t\t\t\t& SQ_CTRL_##member##_MASK)\n+\n+#define SQ_CTRL_CLEAR(val, member)\t((val) & \\\n+\t\t\t\t\t(~(SQ_CTRL_##member##_MASK << \\\n+\t\t\t\t\tSQ_CTRL_##member##_SHIFT)))\n+\n+#define SQ_CTRL_QUEUE_INFO_PLDOFF_SHIFT\t\t2\n+#define SQ_CTRL_QUEUE_INFO_UFO_SHIFT\t\t10\n+#define SQ_CTRL_QUEUE_INFO_TSO_SHIFT\t\t11\n+#define SQ_CTRL_QUEUE_INFO_TCPUDP_CS_SHIFT\t12\n+#define SQ_CTRL_QUEUE_INFO_MSS_SHIFT\t\t13\n+#define SQ_CTRL_QUEUE_INFO_SCTP_SHIFT\t\t27\n+#define SQ_CTRL_QUEUE_INFO_UC_SHIFT\t\t28\n+#define SQ_CTRL_QUEUE_INFO_PRI_SHIFT\t\t29\n+\n+#define SQ_CTRL_QUEUE_INFO_PLDOFF_MASK\t\t0xFFU\n+#define SQ_CTRL_QUEUE_INFO_UFO_MASK\t\t0x1U\n+#define SQ_CTRL_QUEUE_INFO_TSO_MASK\t\t0x1U\n+#define SQ_CTRL_QUEUE_INFO_TCPUDP_CS_MASK\t0x1U\n+#define SQ_CTRL_QUEUE_INFO_MSS_MASK\t\t0x3FFFU\n+#define SQ_CTRL_QUEUE_INFO_SCTP_MASK\t\t0x1U\n+#define SQ_CTRL_QUEUE_INFO_UC_MASK\t\t0x1U\n+#define SQ_CTRL_QUEUE_INFO_PRI_MASK\t\t0x7U\n+\n+#define SQ_CTRL_QUEUE_INFO_SET(val, member)\t\\\n+\t(((u32)(val) & SQ_CTRL_QUEUE_INFO_##member##_MASK) \\\n+\t<< SQ_CTRL_QUEUE_INFO_##member##_SHIFT)\n+\n+#define SQ_CTRL_QUEUE_INFO_GET(val, member)\t\\\n+\t(((val) >> SQ_CTRL_QUEUE_INFO_##member##_SHIFT) \\\n+\t& SQ_CTRL_QUEUE_INFO_##member##_MASK)\n+\n+#define SQ_CTRL_QUEUE_INFO_CLEAR(val, member)\t\\\n+\t((val) & (~(SQ_CTRL_QUEUE_INFO_##member##_MASK << \\\n+\tSQ_CTRL_QUEUE_INFO_##member##_SHIFT)))\n+\n+#define\tSQ_TASK_INFO0_L2HDR_LEN_SHIFT\t\t0\n+#define\tSQ_TASK_INFO0_L4OFFLOAD_SHIFT\t\t8\n+#define\tSQ_TASK_INFO0_INNER_L3TYPE_SHIFT\t10\n+#define\tSQ_TASK_INFO0_VLAN_OFFLOAD_SHIFT\t12\n+#define\tSQ_TASK_INFO0_PARSE_FLAG_SHIFT\t\t13\n+#define\tSQ_TASK_INFO0_UFO_AVD_SHIFT\t\t14\n+#define\tSQ_TASK_INFO0_TSO_UFO_SHIFT\t\t15\n+#define   SQ_TASK_INFO0_VLAN_TAG_SHIFT\t\t16\n+\n+#define\tSQ_TASK_INFO0_L2HDR_LEN_MASK\t\t0xFFU\n+#define\tSQ_TASK_INFO0_L4OFFLOAD_MASK\t\t0x3U\n+#define\tSQ_TASK_INFO0_INNER_L3TYPE_MASK\t\t0x3U\n+#define\tSQ_TASK_INFO0_VLAN_OFFLOAD_MASK\t\t0x1U\n+#define\tSQ_TASK_INFO0_PARSE_FLAG_MASK\t\t0x1U\n+#define\tSQ_TASK_INFO0_UFO_AVD_MASK\t\t0x1U\n+#define   SQ_TASK_INFO0_TSO_UFO_MASK\t\t0x1U\n+#define   SQ_TASK_INFO0_VLAN_TAG_MASK\t\t0xFFFFU\n+\n+#define SQ_TASK_INFO0_SET(val, member)\t\t\t\\\n+\t\t(((u32)(val) & SQ_TASK_INFO0_##member##_MASK) <<\t\\\n+\t\tSQ_TASK_INFO0_##member##_SHIFT)\n+#define SQ_TASK_INFO0_GET(val, member)\t\t\t\\\n+\t\t(((val) >> SQ_TASK_INFO0_##member##_SHIFT) &\t\\\n+\t\tSQ_TASK_INFO0_##member##_MASK)\n+\n+#define\tSQ_TASK_INFO1_MD_TYPE_SHIFT\t\t8\n+#define SQ_TASK_INFO1_INNER_L4LEN_SHIFT\t\t16\n+#define SQ_TASK_INFO1_INNER_L3LEN_SHIFT\t\t24\n+\n+#define\tSQ_TASK_INFO1_MD_TYPE_MASK\t\t0xFFU\n+#define SQ_TASK_INFO1_INNER_L4LEN_MASK\t\t0xFFU\n+#define SQ_TASK_INFO1_INNER_L3LEN_MASK\t\t0xFFU\n+\n+#define SQ_TASK_INFO1_SET(val, member)\t\t\t\\\n+\t\t(((val) & SQ_TASK_INFO1_##member##_MASK) <<\t\\\n+\t\tSQ_TASK_INFO1_##member##_SHIFT)\n+#define SQ_TASK_INFO1_GET(val, member)\t\t\t\\\n+\t\t(((val) >> SQ_TASK_INFO1_##member##_SHIFT) &\t\\\n+\t\tSQ_TASK_INFO1_##member##_MASK)\n+\n+#define SQ_TASK_INFO2_TUNNEL_L4LEN_SHIFT\t0\n+#define SQ_TASK_INFO2_OUTER_L3LEN_SHIFT\t\t8\n+#define SQ_TASK_INFO2_TUNNEL_L4TYPE_SHIFT\t16\n+#define SQ_TASK_INFO2_OUTER_L3TYPE_SHIFT\t24\n+\n+#define SQ_TASK_INFO2_TUNNEL_L4LEN_MASK\t\t0xFFU\n+#define SQ_TASK_INFO2_OUTER_L3LEN_MASK\t\t0xFFU\n+#define SQ_TASK_INFO2_TUNNEL_L4TYPE_MASK\t0x7U\n+#define SQ_TASK_INFO2_OUTER_L3TYPE_MASK\t\t0x3U\n+\n+#define SQ_TASK_INFO2_SET(val, member)\t\t\t\\\n+\t\t(((val) & SQ_TASK_INFO2_##member##_MASK) <<\t\\\n+\t\tSQ_TASK_INFO2_##member##_SHIFT)\n+#define SQ_TASK_INFO2_GET(val, member)\t\t\t\\\n+\t\t(((val) >> SQ_TASK_INFO2_##member##_SHIFT) &\t\\\n+\t\tSQ_TASK_INFO2_##member##_MASK)\n+\n+#define\tSQ_TASK_INFO4_L2TYPE_SHIFT\t\t31\n+\n+#define\tSQ_TASK_INFO4_L2TYPE_MASK\t\t0x1U\n+\n+#define SQ_TASK_INFO4_SET(val, member)\t\t\\\n+\t\t(((u32)(val) & SQ_TASK_INFO4_##member##_MASK) << \\\n+\t\tSQ_TASK_INFO4_##member##_SHIFT)\n+\n+/* SQ_DB */\n+#define SQ_DB_OFF\t\t\t\t0x00000800\n+#define SQ_DB_INFO_HI_PI_SHIFT\t\t\t0\n+#define SQ_DB_INFO_QID_SHIFT\t\t\t8\n+#define SQ_DB_INFO_CFLAG_SHIFT\t\t\t23\n+#define SQ_DB_INFO_COS_SHIFT\t\t\t24\n+#define SQ_DB_INFO_TYPE_SHIFT\t\t\t27\n+#define SQ_DB_INFO_HI_PI_MASK\t\t\t0xFFU\n+#define SQ_DB_INFO_QID_MASK\t\t\t0x3FFU\n+#define SQ_DB_INFO_CFLAG_MASK\t\t\t0x1U\n+#define SQ_DB_INFO_COS_MASK\t\t\t0x7U\n+#define SQ_DB_INFO_TYPE_MASK\t\t\t0x1FU\n+#define SQ_DB_INFO_SET(val, member)\t\t\t(((u32)(val) & \\\n+\t\t\t\t\tSQ_DB_INFO_##member##_MASK) << \\\n+\t\t\t\t\tSQ_DB_INFO_##member##_SHIFT)\n+\n+#define SQ_DB_PI_LOW_MASK\t\t\t0xFF\n+#define SQ_DB_PI_LOW(pi)\t\t\t((pi) & SQ_DB_PI_LOW_MASK)\n+#define SQ_DB_PI_HI_SHIFT\t\t\t8\n+#define SQ_DB_PI_HIGH(pi)\t\t\t((pi) >> SQ_DB_PI_HI_SHIFT)\n+#define SQ_DB_ADDR(sq, pi)\t((u64 *)((u8 __iomem *)((sq)->db_addr) + \\\n+\t\t\t\t\t\tSQ_DB_OFF) + SQ_DB_PI_LOW(pi))\n+#define SQ_DB\t\t\t\t\t1\n+#define SQ_CFLAG_DP\t\t\t\t0\t/* CFLAG_DATA_PATH */\n+\n+/* RQ_CTRL */\n+#define\tRQ_CTRL_BUFDESC_SECT_LEN_SHIFT\t\t0\n+#define\tRQ_CTRL_COMPLETE_FORMAT_SHIFT\t\t15\n+#define RQ_CTRL_COMPLETE_LEN_SHIFT\t\t27\n+#define RQ_CTRL_LEN_SHIFT\t\t\t29\n+\n+#define\tRQ_CTRL_BUFDESC_SECT_LEN_MASK\t\t0xFFU\n+#define\tRQ_CTRL_COMPLETE_FORMAT_MASK\t\t0x1U\n+#define RQ_CTRL_COMPLETE_LEN_MASK\t\t0x3U\n+#define RQ_CTRL_LEN_MASK\t\t\t0x3U\n+\n+#define RQ_CTRL_SET(val, member)\t\t\t(((val) & \\\n+\t\t\t\t\tRQ_CTRL_##member##_MASK) << \\\n+\t\t\t\t\tRQ_CTRL_##member##_SHIFT)\n+\n+#define RQ_CTRL_GET(val, member)\t\t\t(((val) >> \\\n+\t\t\t\t\tRQ_CTRL_##member##_SHIFT) & \\\n+\t\t\t\t\tRQ_CTRL_##member##_MASK)\n+\n+#define RQ_CTRL_CLEAR(val, member)\t\t\t((val) & \\\n+\t\t\t\t\t(~(RQ_CTRL_##member##_MASK << \\\n+\t\t\t\t\tRQ_CTRL_##member##_SHIFT)))\n+\n+#define RQ_CQE_STATUS_CSUM_ERR_SHIFT\t\t0\n+#define RQ_CQE_STATUS_NUM_LRO_SHIFT\t\t16\n+#define RQ_CQE_STATUS_LRO_PUSH_SHIFT\t\t25\n+#define RQ_CQE_STATUS_LRO_ENTER_SHIFT\t\t26\n+#define RQ_CQE_STATUS_LRO_INTR_SHIFT\t\t27\n+\n+#define RQ_CQE_STATUS_BP_EN_SHIFT\t\t30\n+#define RQ_CQE_STATUS_RXDONE_SHIFT\t\t31\n+#define RQ_CQE_STATUS_FLUSH_SHIFT\t\t28\n+\n+#define RQ_CQE_STATUS_CSUM_ERR_MASK\t\t0xFFFFU\n+#define RQ_CQE_STATUS_NUM_LRO_MASK\t\t0xFFU\n+#define RQ_CQE_STATUS_LRO_PUSH_MASK\t\t0X1U\n+#define RQ_CQE_STATUS_LRO_ENTER_MASK\t\t0X1U\n+#define RQ_CQE_STATUS_LRO_INTR_MASK\t\t0X1U\n+#define RQ_CQE_STATUS_BP_EN_MASK\t\t0X1U\n+#define RQ_CQE_STATUS_RXDONE_MASK\t\t0x1U\n+#define RQ_CQE_STATUS_FLUSH_MASK\t\t0x1U\n+\n+#define RQ_CQE_STATUS_GET(val, member)\t\t\t(((val) >> \\\n+\t\t\t\t\tRQ_CQE_STATUS_##member##_SHIFT) & \\\n+\t\t\t\t\tRQ_CQE_STATUS_##member##_MASK)\n+\n+#define RQ_CQE_STATUS_CLEAR(val, member)\t\t((val) & \\\n+\t\t\t\t\t(~(RQ_CQE_STATUS_##member##_MASK << \\\n+\t\t\t\t\tRQ_CQE_STATUS_##member##_SHIFT)))\n+\n+#define RQ_CQE_SGE_VLAN_SHIFT\t\t\t0\n+#define RQ_CQE_SGE_LEN_SHIFT\t\t\t16\n+\n+#define RQ_CQE_SGE_VLAN_MASK\t\t\t0xFFFFU\n+#define RQ_CQE_SGE_LEN_MASK\t\t\t0xFFFFU\n+\n+#define RQ_CQE_SGE_GET(val, member)\t\t\t(((val) >> \\\n+\t\t\t\t\tRQ_CQE_SGE_##member##_SHIFT) & \\\n+\t\t\t\t\tRQ_CQE_SGE_##member##_MASK)\n+\n+#define RQ_CQE_PKT_NUM_SHIFT\t\t\t1\n+#define RQ_CQE_PKT_FIRST_LEN_SHIFT\t\t19\n+#define RQ_CQE_PKT_LAST_LEN_SHIFT\t\t6\n+#define RQ_CQE_SUPER_CQE_EN_SHIFT\t\t0\n+\n+#define RQ_CQE_PKT_FIRST_LEN_MASK\t\t0x1FFFU\n+#define RQ_CQE_PKT_LAST_LEN_MASK\t\t0x1FFFU\n+#define RQ_CQE_PKT_NUM_MASK\t\t\t0x1FU\n+#define RQ_CQE_SUPER_CQE_EN_MASK\t\t0x1\n+\n+#define RQ_CQE_PKT_NUM_GET(val, member)\t\t\t(((val) >> \\\n+\t\t\t\t\tRQ_CQE_PKT_##member##_SHIFT) & \\\n+\t\t\t\t\tRQ_CQE_PKT_##member##_MASK)\n+#define HINIC_GET_RQ_CQE_PKT_NUM(pkt_info) RQ_CQE_PKT_NUM_GET(pkt_info, NUM)\n+\n+#define RQ_CQE_SUPER_CQE_EN_GET(val, member)\t(((val) >> \\\n+\t\t\t\t\tRQ_CQE_##member##_SHIFT) & \\\n+\t\t\t\t\tRQ_CQE_##member##_MASK)\n+#define HINIC_GET_SUPER_CQE_EN(pkt_info)\t\\\n+\tRQ_CQE_SUPER_CQE_EN_GET(pkt_info, SUPER_CQE_EN)\n+\n+#define HINIC_GET_SUPER_CQE_EN_BE(pkt_info)\t((pkt_info) & 0x1000000U)\n+#define RQ_CQE_PKT_LEN_GET(val, member)\t\t\t(((val) >> \\\n+\t\t\t\t\t\tRQ_CQE_PKT_##member##_SHIFT) & \\\n+\t\t\t\t\t\tRQ_CQE_PKT_##member##_MASK)\n+\n+#define RQ_CQE_OFFOLAD_TYPE_VLAN_EN_SHIFT\t\t21\n+#define RQ_CQE_OFFOLAD_TYPE_VLAN_EN_MASK\t\t0x1U\n+\n+#define RQ_CQE_OFFOLAD_TYPE_PKT_TYPE_SHIFT\t\t0\n+#define RQ_CQE_OFFOLAD_TYPE_PKT_TYPE_MASK\t\t0xFFFU\n+\n+#define RQ_CQE_OFFOLAD_TYPE_PKT_UMBCAST_SHIFT\t\t19\n+#define RQ_CQE_OFFOLAD_TYPE_PKT_UMBCAST_MASK\t\t0x3U\n+\n+#define RQ_CQE_OFFOLAD_TYPE_RSS_TYPE_SHIFT\t\t24\n+#define RQ_CQE_OFFOLAD_TYPE_RSS_TYPE_MASK\t\t0xFFU\n+\n+#define RQ_CQE_OFFOLAD_TYPE_GET(val, member)\t\t(((val) >> \\\n+\t\t\t\tRQ_CQE_OFFOLAD_TYPE_##member##_SHIFT) & \\\n+\t\t\t\tRQ_CQE_OFFOLAD_TYPE_##member##_MASK)\n+\n+#define RQ_CQE_PKT_TYPES_NON_L2_MASK\t\t\t0x800U\n+#define RQ_CQE_PKT_TYPES_L2_MASK\t\t\t0x7FU\n+\n+#define RQ_CQE_STATUS_CSUM_BYPASS_VAL\t\t\t0x80U\n+#define RQ_CQE_STATUS_CSUM_ERR_IP_MASK\t\t\t0x39U\n+#define RQ_CQE_STATUS_CSUM_ERR_L4_MASK\t\t\t0x46U\n+#define RQ_CQE_STATUS_CSUM_ERR_OTHER\t\t\t0x100U\n+\n+#define SECT_SIZE_BYTES(size)\t((size) << 3)\n+\n+#define HINIC_PF_SET_VF_ALREADY\t\t\t\t0x4\n+\n+#define WQS_BLOCKS_PER_PAGE\t\t4\n+\n+#define WQ_SIZE(wq)\t\t(u32)((u64)(wq)->q_depth * (wq)->wqebb_size)\n+\n+#define\tWQE_PAGE_NUM(wq, idx)\t(((idx) >> ((wq)->wqebbs_per_page_shift)) & \\\n+\t\t\t\t((wq)->num_q_pages - 1))\n+\n+#define\tWQE_PAGE_OFF(wq, idx)\t((u64)((wq)->wqebb_size) * \\\n+\t\t\t\t((idx) & ((wq)->num_wqebbs_per_page - 1)))\n+\n+#define WQ_PAGE_ADDR_SIZE\t\tsizeof(u64)\n+#define WQ_PAGE_ADDR_SIZE_SHIFT\t\t3\n+#define WQ_PAGE_ADDR(wq, idx)\t\t\\\n+\t\t(u8 *)(*(u64 *)((u64)((wq)->shadow_block_vaddr) + \\\n+\t\t(WQE_PAGE_NUM(wq, idx) << WQ_PAGE_ADDR_SIZE_SHIFT)))\n+\n+#define WQ_BLOCK_SIZE\t\t4096UL\n+#define WQS_PAGE_SIZE\t\t(WQS_BLOCKS_PER_PAGE * WQ_BLOCK_SIZE)\n+#define WQ_MAX_PAGES\t\t(WQ_BLOCK_SIZE >> WQ_PAGE_ADDR_SIZE_SHIFT)\n+\n+#define CMDQ_BLOCKS_PER_PAGE\t\t8\n+#define CMDQ_BLOCK_SIZE\t\t\t512UL\n+#define CMDQ_PAGE_SIZE\t\t\tALIGN((CMDQ_BLOCKS_PER_PAGE * \\\n+\t\t\t\t\t\tCMDQ_BLOCK_SIZE), PAGE_SIZE)\n+\n+#define ADDR_4K_ALIGNED(addr)\t\t(0 == ((addr) & 0xfff))\n+#define ADDR_256K_ALIGNED(addr)\t\t(0 == ((addr) & 0x3ffff))\n+\n+#define WQ_BASE_VADDR(wqs, wq)\t\t\\\n+\t\t(u64 *)(((u64)((wqs)->page_vaddr[(wq)->page_idx])) \\\n+\t\t\t\t+ (wq)->block_idx * WQ_BLOCK_SIZE)\n+\n+#define WQ_BASE_PADDR(wqs, wq)\t(((wqs)->page_paddr[(wq)->page_idx]) \\\n+\t\t\t\t+ (u64)(wq)->block_idx * WQ_BLOCK_SIZE)\n+\n+#define WQ_BASE_ADDR(wqs, wq)\t\t\\\n+\t\t(u64 *)(((u64)((wqs)->shadow_page_vaddr[(wq)->page_idx])) \\\n+\t\t\t\t+ (wq)->block_idx * WQ_BLOCK_SIZE)\n+\n+#define CMDQ_BASE_VADDR(cmdq_pages, wq)\t\\\n+\t\t\t(u64 *)(((u64)((cmdq_pages)->cmdq_page_vaddr)) \\\n+\t\t\t\t+ (wq)->block_idx * CMDQ_BLOCK_SIZE)\n+\n+#define CMDQ_BASE_PADDR(cmdq_pages, wq)\t\\\n+\t\t\t(((u64)((cmdq_pages)->cmdq_page_paddr)) \\\n+\t\t\t\t+ (u64)(wq)->block_idx * CMDQ_BLOCK_SIZE)\n+\n+#define CMDQ_BASE_ADDR(cmdq_pages, wq)\t\\\n+\t\t\t(u64 *)(((u64)((cmdq_pages)->cmdq_shadow_page_vaddr)) \\\n+\t\t\t\t+ (wq)->block_idx * CMDQ_BLOCK_SIZE)\n+\n+#define MASKED_WQE_IDX(wq, idx)\t((idx) & (wq)->mask)\n+\n+#define WQE_SHADOW_PAGE(wq, wqe)\t\\\n+\t\t(u16)(((unsigned long)(wqe) - (unsigned long)(wq)->shadow_wqe) \\\n+\t\t/ (wq)->max_wqe_size)\n+\n+#define WQE_IN_RANGE(wqe, start, end)\t\\\n+\t\t(((unsigned long)(wqe) >= (unsigned long)(start)) && \\\n+\t\t((unsigned long)(wqe) < (unsigned long)(end)))\n+\n+#define WQ_NUM_PAGES(num_wqs)\t\\\n+\t(ALIGN((u32)num_wqs, WQS_BLOCKS_PER_PAGE) / WQS_BLOCKS_PER_PAGE)\n+\n+/* Queue buffer related define */\n+enum hinic_rx_buf_size {\n+\tHINIC_RX_BUF_SIZE_32B = 0x20,\n+\tHINIC_RX_BUF_SIZE_64B = 0x40,\n+\tHINIC_RX_BUF_SIZE_96B = 0x60,\n+\tHINIC_RX_BUF_SIZE_128B = 0x80,\n+\tHINIC_RX_BUF_SIZE_192B = 0xC0,\n+\tHINIC_RX_BUF_SIZE_256B = 0x100,\n+\tHINIC_RX_BUF_SIZE_384B = 0x180,\n+\tHINIC_RX_BUF_SIZE_512B = 0x200,\n+\tHINIC_RX_BUF_SIZE_768B = 0x300,\n+\tHINIC_RX_BUF_SIZE_1K = 0x400,\n+\tHINIC_RX_BUF_SIZE_1_5K = 0x600,\n+\tHINIC_RX_BUF_SIZE_2K = 0x800,\n+\tHINIC_RX_BUF_SIZE_3K = 0xC00,\n+\tHINIC_RX_BUF_SIZE_4K = 0x1000,\n+\tHINIC_RX_BUF_SIZE_8K = 0x2000,\n+\tHINIC_RX_BUF_SIZE_16K = 0x4000,\n+};\n+\n+enum hinic_res_state {\n+\tHINIC_RES_CLEAN = 0,\n+\tHINIC_RES_ACTIVE = 1,\n+};\n+\n+#define DEFAULT_RX_BUF_SIZE\t((u16)0xB)\n+\n+#define BUF_DESC_SIZE_SHIFT\t\t\t4\n+\n+#define HINIC_SQ_WQE_SIZE(num_sge)\t\t\\\n+\t\t(sizeof(struct hinic_sq_ctrl) + \\\n+\t\tsizeof(struct hinic_sq_task) +  \\\n+\t\t(unsigned int)((num_sge) << BUF_DESC_SIZE_SHIFT))\n+\n+#define HINIC_SQ_WQEBB_CNT(num_sge)\t\\\n+\t\t(int)(ALIGN(HINIC_SQ_WQE_SIZE((u32)num_sge), \\\n+\t\t\t    HINIC_SQ_WQEBB_SIZE) >> HINIC_SQ_WQEBB_SHIFT)\n+\n+#define HINIC_GET_RX_VLAN_OFFLOAD_EN(offload_type)\t\\\n+\t\tRQ_CQE_OFFOLAD_TYPE_GET(offload_type, VLAN_EN)\n+\n+#define HINIC_GET_RSS_TYPES(offload_type)\t\\\n+\t\tRQ_CQE_OFFOLAD_TYPE_GET(offload_type, RSS_TYPE)\n+\n+#define HINIC_GET_PKT_TYPES(offload_type)\t\\\n+\t\tRQ_CQE_OFFOLAD_TYPE_GET(offload_type, PKT_TYPE)\n+\n+#define HINIC_GET_RX_PKT_TYPE(offload_type)\t\\\n+\t\tRQ_CQE_OFFOLAD_TYPE_GET(offload_type, PKT_TYPE)\n+\n+#define HINIC_GET_RX_PKT_UMBCAST(offload_type)\t\\\n+\t\tRQ_CQE_OFFOLAD_TYPE_GET(offload_type, PKT_UMBCAST)\n+\n+\n+#define HINIC_GET_RX_VLAN_TAG(vlan_len)\t\\\n+\t\tRQ_CQE_SGE_GET(vlan_len, VLAN)\n+\n+#define HINIC_GET_RX_PKT_LEN(vlan_len)\t\\\n+\t\tRQ_CQE_SGE_GET(vlan_len, LEN)\n+\n+#define HINIC_GET_RX_CSUM_ERR(status)\t\\\n+\t\tRQ_CQE_STATUS_GET(status, CSUM_ERR)\n+\n+#define HINIC_GET_RX_DONE(status)\t\\\n+\t\tRQ_CQE_STATUS_GET(status, RXDONE)\n+\n+#define HINIC_GET_RX_FLUSH(status)\t\\\n+\t\tRQ_CQE_STATUS_GET(status, FLUSH)\n+\n+#define HINIC_GET_RX_BP_EN(status)\t\\\n+\t\tRQ_CQE_STATUS_GET(status, BP_EN)\n+\n+#define HINIC_GET_RX_NUM_LRO(status)\t\\\n+\t\tRQ_CQE_STATUS_GET(status, NUM_LRO)\n+\n+#define HINIC_PKT_TYPES_UNKNOWN(pkt_types)\t \\\n+\t((pkt_types) & RQ_CQE_PKT_TYPES_NON_L2_MASK)\n+\n+#define HINIC_PKT_TYPES_L2(pkt_types)\t \\\n+\t((pkt_types) & RQ_CQE_PKT_TYPES_L2_MASK)\n+\n+#define HINIC_CSUM_ERR_BYPASSED(csum_err)\t \\\n+\t((csum_err) == RQ_CQE_STATUS_CSUM_BYPASS_VAL)\n+\n+#define HINIC_CSUM_ERR_IP(csum_err)\t \\\n+\t((csum_err) & RQ_CQE_STATUS_CSUM_ERR_IP_MASK)\n+\n+#define HINIC_CSUM_ERR_L4(csum_err)\t \\\n+\t((csum_err) & RQ_CQE_STATUS_CSUM_ERR_L4_MASK)\n+\n+#define HINIC_CSUM_ERR_OTHER(csum_err)\t \\\n+\t((csum_err) == RQ_CQE_STATUS_CSUM_ERR_OTHER)\n+\n+#define TX_MSS_DEFAULT\t\t0x3E00\n+#define TX_MSS_MIN\t\t0x50\n+\n+enum sq_wqe_type {\n+\tSQ_NORMAL_WQE = 0,\n+};\n+\n+enum rq_completion_fmt {\n+\tRQ_COMPLETE_SGE = 1\n+};\n+\n+#define HINIC_VLAN_FILTER_EN\t\t(1U << 0)\n+#define HINIC_BROADCAST_FILTER_EX_EN\t(1U << 1)\n+\n+#ifdef __cplusplus\n+    #if __cplusplus\n+}\n+    #endif\n+#endif /* __cplusplus */\n+#endif /* _HINIC_QE_DEF_H_ */\ndiff --git a/drivers/net/hinic/hinic_pmd_ethdev.h b/drivers/net/hinic/hinic_pmd_ethdev.h\nnew file mode 100644\nindex 0000000..4a7d148\n--- /dev/null\n+++ b/drivers/net/hinic/hinic_pmd_ethdev.h\n@@ -0,0 +1,106 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2017 Huawei Technologies Co., Ltd\n+ */\n+\n+#ifndef _HINIC_PMD_ETHDEV_H_\n+#define _HINIC_PMD_ETHDEV_H_\n+\n+#include \"base/hinic_pmd_dpdev.h\"\n+\n+#define PMD_DRIVER_VERSION\t\"2.0.0.1\"\n+\n+/* Vendor ID used by Huawei devices */\n+#define HINIC_HUAWEI_VENDOR_ID 0x19E5\n+\n+/* Hinic devices */\n+#define HINIC_DEV_ID_PRD\t\t0x1822\n+#define HINIC_DEV_ID_MEZZ_25GE\t\t0x0210\n+#define HINIC_DEV_ID_MEZZ_40GE\t\t0x020D\n+#define HINIC_DEV_ID_MEZZ_100GE\t\t0x0205\n+\n+#define HINIC_PMD_DEV_BOND\t\t\t(1)\n+#define HINIC_PMD_DEV_EMPTY\t\t\t(-1)\n+#define HINIC_DEV_NAME_MAX_LEN\t(32)\n+\n+#define HINIC_RSS_OFFLOAD_ALL ( \\\n+\tETH_RSS_IPV4 | \\\n+\tETH_RSS_FRAG_IPV4 |\\\n+\tETH_RSS_NONFRAG_IPV4_TCP | \\\n+\tETH_RSS_NONFRAG_IPV4_UDP | \\\n+\tETH_RSS_IPV6 | \\\n+\tETH_RSS_FRAG_IPV6 | \\\n+\tETH_RSS_NONFRAG_IPV6_TCP | \\\n+\tETH_RSS_NONFRAG_IPV6_UDP | \\\n+\tETH_RSS_IPV6_EX | \\\n+\tETH_RSS_IPV6_TCP_EX | \\\n+\tETH_RSS_IPV6_UDP_EX)\n+\n+#define HINIC_MTU_TO_PKTLEN(mtu)\t\\\n+\t((mtu) + ETH_HLEN + ETH_CRC_LEN)\n+\n+#define HINIC_PKTLEN_TO_MTU(pktlen)\t\\\n+\t((pktlen) - (ETH_HLEN + ETH_CRC_LEN))\n+\n+/* vhd type */\n+#define HINIC_VHD_TYPE_0B\t\t(2)\n+#define HINIC_VHD_TYPE_10B\t\t(1)\n+#define HINIC_VHD_TYPE_12B\t\t(0)\n+\n+/* vlan_id is a 12 bit number.\n+ * The VFTA array is actually a 4096 bit array, 128 of 32bit elements.\n+ * 2^5 = 32. The val of lower 5 bits specifies the bit in the 32bit element.\n+ * The higher 7 bit val specifies VFTA array index.\n+ */\n+#define HINIC_VFTA_BIT(vlan_id)    (1 << ((vlan_id) & 0x1F))\n+#define HINIC_VFTA_IDX(vlan_id)    ((vlan_id) >> 5)\n+\n+#define HINIC_INTR_CB_UNREG_MAX_RETRIES\t\t10\n+\n+/* eth_dev ops */\n+int hinic_dev_configure(struct rte_eth_dev *dev);\n+void hinic_dev_infos_get(struct rte_eth_dev *dev,\n+\t\t\t struct rte_eth_dev_info *dev_info);\n+int hinic_dev_start(struct rte_eth_dev *dev);\n+int hinic_link_update(struct rte_eth_dev *dev, int wait_to_complete);\n+void hinic_rx_queue_release(void *queue);\n+void hinic_tx_queue_release(void *queue);\n+void hinic_dev_stop(struct rte_eth_dev *dev);\n+void hinic_dev_close(struct rte_eth_dev *dev);\n+int hinic_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats);\n+void hinic_dev_stats_reset(struct rte_eth_dev *dev);\n+void hinic_dev_xstats_reset(struct rte_eth_dev *dev);\n+void hinic_dev_promiscuous_enable(struct rte_eth_dev *dev);\n+void hinic_dev_promiscuous_disable(struct rte_eth_dev *dev);\n+\n+int hinic_vlan_offload_set(struct rte_eth_dev *dev, int mask);\n+int hinic_dev_atomic_write_link_status(struct rte_eth_dev *dev,\n+\t\t\t\t       struct rte_eth_link *link);\n+int hinic_dev_atomic_read_link_status(struct rte_eth_dev *dev,\n+\t\t\t\t      struct rte_eth_link *link);\n+int hinic_link_event_process(struct rte_eth_dev *dev, u8 status);\n+void hinic_disable_interrupt(struct rte_eth_dev *dev);\n+void hinic_free_all_sq(hinic_nic_dev *nic_dev);\n+void hinic_free_all_rq(hinic_nic_dev *nic_dev);\n+\n+int hinic_rxtx_configure(struct rte_eth_dev *dev);\n+int hinic_rss_hash_update(struct rte_eth_dev *dev,\n+\t\t\t  struct rte_eth_rss_conf *rss_conf);\n+int hinic_rss_conf_get(struct rte_eth_dev *dev,\n+\t\t       struct rte_eth_rss_conf *rss_conf);\n+int hinic_rss_indirtbl_update(struct rte_eth_dev *dev,\n+\t\t\t      struct rte_eth_rss_reta_entry64 *reta_conf,\n+\t\t\t      uint16_t reta_size);\n+int hinic_rss_indirtbl_query(struct rte_eth_dev *dev,\n+\t\t\t     struct rte_eth_rss_reta_entry64 *reta_conf,\n+\t\t\t     uint16_t reta_size);\n+\n+int hinic_dev_xstats_get(struct rte_eth_dev *dev,\n+\t\t\t struct rte_eth_xstat *xstats, unsigned int n);\n+int hinic_dev_xstats_get_names(struct rte_eth_dev *dev,\n+\t\t\t       struct rte_eth_xstat_name *xstats_names,\n+\t\t\t       __rte_unused unsigned int limit);\n+\n+int hinic_fw_version_get(struct rte_eth_dev *dev,\n+\t\t\tchar *fw_version, size_t fw_size);\n+\n+#endif /* _HINIC_PMD_ETHDEV_H_ */\ndiff --git a/drivers/net/hinic/hinic_pmd_rx.h b/drivers/net/hinic/hinic_pmd_rx.h\nnew file mode 100644\nindex 0000000..da1b6d6\n--- /dev/null\n+++ b/drivers/net/hinic/hinic_pmd_rx.h\n@@ -0,0 +1,135 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2017 Huawei Technologies Co., Ltd\n+ */\n+\n+#ifndef _HINIC_PMD_RX_H_\n+#define _HINIC_PMD_RX_H_\n+\n+/* rxq wq operations */\n+#define HINIC_GET_RQ_WQE_MASK(rxq)\t\\\n+\t((rxq)->wq->mask)\n+\n+#define HINIC_GET_RQ_LOCAL_CI(rxq)\t\\\n+\t(((rxq)->wq->cons_idx) & HINIC_GET_RQ_WQE_MASK(rxq))\n+\n+#define HINIC_GET_RQ_LOCAL_PI(rxq)\t\\\n+\t(((rxq)->wq->prod_idx) & HINIC_GET_RQ_WQE_MASK(rxq))\n+\n+#define HINIC_UPDATE_RQ_LOCAL_CI(rxq, wqebb_cnt)\t\\\n+\tdo {\t\t\t\t\t\t\\\n+\t\t(rxq)->wq->cons_idx += (wqebb_cnt);\t\\\n+\t\t(rxq)->wq->delta += (wqebb_cnt);\t\\\n+\t} while (0)\n+\n+#define HINIC_GET_RQ_FREE_WQEBBS(rxq)\t\\\n+\t((rxq)->wq->delta - 1)\n+\n+#define HINIC_UPDATE_RQ_HW_PI(rxq, pi)\t\\\n+\t(*((rxq)->pi_virt_addr) =\t\\\n+\t\tcpu_to_be16((pi) & HINIC_GET_RQ_WQE_MASK(rxq)))\n+\n+/* rxq cqe done and status bit */\n+#define HINIC_GET_RX_DONE_BE(status)\t\\\n+\t((status) & 0x80U)\n+\n+#define HINIC_GET_RX_FLUSH_BE(status)\t\\\n+\t((status) & 0x10U)\n+\n+#define HINIC_DEFAULT_RX_FREE_THRESH\t32\n+\n+#define HINIC_RX_CSUM_OFFLOAD_EN\t0xFFF\n+\n+struct hinic_rxq_stats {\n+\tu64 packets;\n+\tu64 bytes;\n+\tu64 rx_nombuf;\n+\tu64 errors;\n+\tu64 rx_discards;\n+\n+#ifdef HINIC_XSTAT_MBUF_USE\n+\tu64 alloc_mbuf;\n+\tu64 free_mbuf;\n+\tu64 left_mbuf;\n+#endif\n+\n+#ifdef HINIC_XSTAT_RXBUF_INFO\n+\tu64 rx_mbuf;\n+\tu64 rx_avail;\n+\tu64 rx_hole;\n+\tu64 burst_pkts;\n+#endif\n+\n+#ifdef HINIC_XSTAT_PROF_RX\n+\tu64 app_tsc;\n+\tu64 pmd_tsc;\n+#endif\n+};\n+\n+/* Attention, Do not add any member in hinic_rx_info\n+ * as rxq bulk rearm mode will write mbuf in rx_info\n+ */\n+struct hinic_rx_info {\n+\tstruct rte_mbuf *mbuf;\n+};\n+\n+struct hinic_rxq {\n+\tstruct hinic_wq *wq;\n+\tvolatile u16 *pi_virt_addr;\n+\n+\tu16 port_id;\n+\tu16 q_id;\n+\tu16 q_depth;\n+\tu16 buf_len;\n+\n+\tu16 rx_free_thresh;\n+\tu16 rxinfo_align_end;\n+\n+\tunsigned long status;\n+\tstruct hinic_rxq_stats rxq_stats;\n+\n+\thinic_nic_dev *nic_dev;\n+\n+\tstruct hinic_rx_info\t*rx_info;\n+\tvolatile struct hinic_rq_cqe *rx_cqe;\n+\n+\tdma_addr_t cqe_start_paddr;\n+\tvoid *cqe_start_vaddr;\n+\tstruct rte_mempool *mb_pool;\n+\n+#ifdef HINIC_XSTAT_PROF_RX\n+\t/* performance profiling */\n+\tuint64_t prof_rx_end_tsc;\n+#endif\n+};\n+\n+#ifdef HINIC_XSTAT_MBUF_USE\n+void hinic_rx_free_mbuf(struct hinic_rxq *rxq, struct rte_mbuf *m);\n+#else\n+void hinic_rx_free_mbuf(struct rte_mbuf *m);\n+#endif\n+\n+int hinic_setup_rx_resources(struct hinic_rxq *rxq);\n+\n+void hinic_free_all_rx_resources(struct rte_eth_dev *dev);\n+\n+void hinic_free_all_rx_mbuf(struct rte_eth_dev *dev);\n+\n+void hinic_free_rx_resources(struct hinic_rxq *rxq);\n+\n+u16 hinic_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, u16 nb_pkts);\n+\n+void hinic_free_all_rx_skbs(struct hinic_rxq *rxq);\n+\n+void hinic_rx_alloc_pkts(struct hinic_rxq *rxq);\n+\n+void hinic_rxq_get_stats(struct hinic_rxq *rxq, struct hinic_rxq_stats *stats);\n+\n+void hinic_rxq_stats_reset(struct hinic_rxq *rxq);\n+\n+int hinic_config_mq_mode(struct rte_eth_dev *dev, bool on);\n+\n+int hinic_rx_configure(struct rte_eth_dev *dev);\n+\n+void hinic_rx_remove_configure(struct rte_eth_dev *dev);\n+\n+#endif /* _HINIC_PMD_RX_H_ */\ndiff --git a/drivers/net/hinic/hinic_pmd_tx.h b/drivers/net/hinic/hinic_pmd_tx.h\nnew file mode 100644\nindex 0000000..5a015a7\n--- /dev/null\n+++ b/drivers/net/hinic/hinic_pmd_tx.h\n@@ -0,0 +1,97 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2017 Huawei Technologies Co., Ltd\n+ */\n+\n+#ifndef _HINIC_PMD_TX_H_\n+#define _HINIC_PMD_TX_H_\n+\n+#define HINIC_DEFAULT_TX_FREE_THRESH\t32\n+#define HINIC_MAX_TX_FREE_BULK\t\t64\n+\n+/* txq wq operations */\n+#define HINIC_GET_SQ_WQE_MASK(txq)\t\\\n+\t((txq)->wq->mask)\n+\n+#define HINIC_GET_SQ_HW_CI(txq)\t\\\n+\t((be16_to_cpu(*(txq)->cons_idx_addr)) & HINIC_GET_SQ_WQE_MASK(txq))\n+\n+#define HINIC_GET_SQ_LOCAL_CI(txq)\t\\\n+\t(((txq)->wq->cons_idx) & HINIC_GET_SQ_WQE_MASK(txq))\n+\n+#define HINIC_UPDATE_SQ_LOCAL_CI(txq, wqebb_cnt)\t\\\n+\tdo {\t\t\t\t\t\t\\\n+\t\t(txq)->wq->cons_idx += wqebb_cnt;\t\\\n+\t\t(txq)->wq->delta += wqebb_cnt;\t\t\\\n+\t} while (0)\n+\n+#define HINIC_GET_SQ_FREE_WQEBBS(txq)\t\\\n+\t\t((txq)->wq->delta - 1)\n+\n+#define HINIC_IS_SQ_EMPTY(txq)\t\\\n+\t\t(((txq)->wq->delta) == ((txq)->q_depth))\n+\n+#define HINIC_GET_WQ_TAIL(txq) ((txq)->wq->queue_buf_vaddr + \\\n+\t\t\t\t(txq)->wq->wq_buf_size)\n+#define HINIC_GET_WQ_HEAD(txq) ((txq)->wq->queue_buf_vaddr)\n+\n+struct hinic_txq_stats {\n+\tu64 packets;\n+\tu64 bytes;\n+\tu64 rl_drop;\n+\tu64 tx_busy;\n+\tu64 off_errs;\n+\tu64 cpy_pkts;\n+\n+#ifdef HINIC_XSTAT_PROF_TX\n+\tu64 app_tsc;\n+\tu64 pmd_tsc;\n+\tu64 burst_pkts;\n+#endif\n+};\n+\n+struct hinic_tx_info {\n+\tstruct rte_mbuf *mbuf;\n+\tint wqebb_cnt;\n+\tstruct rte_mbuf *cpy_mbuf;\n+};\n+\n+struct hinic_txq {\n+\t/* cacheline0 */\n+\thinic_nic_dev *nic_dev;\n+\tstruct hinic_wq *wq;\n+\tstruct hinic_sq *sq;\n+\tvolatile u16 *cons_idx_addr;\n+\tstruct hinic_tx_info *tx_info;\n+\n+\tu16 tx_free_thresh;\n+\tu16 port_id;\n+\tu16 q_id;\n+\tu16 q_depth;\n+\tu32 cos;\n+\n+\t/* cacheline1 */\n+\tstruct hinic_txq_stats txq_stats;\n+\tu64 sq_head_addr;\n+\tu64 sq_bot_sge_addr;\n+#ifdef HINIC_XSTAT_PROF_TX\n+\tuint64_t prof_tx_end_tsc; /* performance profiling */\n+#endif\n+};\n+\n+int hinic_setup_tx_resources(struct hinic_txq *txq);\n+\n+void hinic_free_all_tx_resources(struct rte_eth_dev *eth_dev);\n+\n+void hinic_free_all_tx_mbuf(struct rte_eth_dev *eth_dev);\n+\n+void hinic_free_tx_resources(struct hinic_txq *txq);\n+\n+u16 hinic_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, u16 nb_pkts);\n+\n+void hinic_free_all_tx_skbs(struct hinic_txq *txq);\n+\n+void hinic_txq_get_stats(struct hinic_txq *txq, struct hinic_txq_stats *stats);\n+\n+void hinic_txq_stats_reset(struct hinic_txq *txq);\n+\n+#endif /* _HINIC_PMD_TX_H_ */\n",
    "prefixes": [
        "07/11"
    ]
}