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GET /api/patches/53123/?format=api
{ "id": 53123, "url": "http://patches.dpdk.org/api/patches/53123/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1556339577-18185-3-git-send-email-viacheslavo@mellanox.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1556339577-18185-3-git-send-email-viacheslavo@mellanox.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1556339577-18185-3-git-send-email-viacheslavo@mellanox.com", "date": "2019-04-27T04:32:57", "name": "[v3,2/2] net/mlx5: update memory event callback for shared context", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "a417920fe554b28bf5a1f567566c3ba947c887c1", "submitter": { "id": 1102, "url": "http://patches.dpdk.org/api/people/1102/?format=api", "name": "Slava Ovsiienko", "email": "viacheslavo@mellanox.com" }, "delegate": { "id": 6624, "url": "http://patches.dpdk.org/api/users/6624/?format=api", "username": "shahafs", "first_name": "Shahaf", "last_name": "Shuler", "email": "shahafs@mellanox.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1556339577-18185-3-git-send-email-viacheslavo@mellanox.com/mbox/", "series": [ { "id": 4492, "url": "http://patches.dpdk.org/api/series/4492/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=4492", "date": "2019-04-27T04:32:55", "name": "net/mlx5: share Memory Regions for multiport devices", "version": 3, "mbox": "http://patches.dpdk.org/series/4492/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/53123/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/53123/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 983BF1B7D5;\n\tSat, 27 Apr 2019 06:33:22 +0200 (CEST)", "from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129])\n\tby dpdk.org (Postfix) with ESMTP id 5A17D1B76E\n\tfor <dev@dpdk.org>; Sat, 27 Apr 2019 06:33:20 +0200 (CEST)", "from Internal Mail-Server by MTLPINE2 (envelope-from\n\tviacheslavo@mellanox.com)\n\twith ESMTPS (AES256-SHA encrypted); 27 Apr 2019 07:33:16 +0300", "from pegasus12.mtr.labs.mlnx. (pegasus12.mtr.labs.mlnx\n\t[10.210.17.40])\n\tby labmailer.mlnx (8.13.8/8.13.8) with ESMTP id x3R4X0eY020373;\n\tSat, 27 Apr 2019 07:33:15 +0300" ], "From": "Viacheslav Ovsiienko <viacheslavo@mellanox.com>", "To": "shahafs@mellanox.com", "Cc": "dev@dpdk.org, yskoh@mellanox.com", "Date": "Sat, 27 Apr 2019 04:32:57 +0000", "Message-Id": "<1556339577-18185-3-git-send-email-viacheslavo@mellanox.com>", "X-Mailer": "git-send-email 1.8.3.1", "In-Reply-To": "<1556339577-18185-1-git-send-email-viacheslavo@mellanox.com>", "References": "<1556095470-11407-1-git-send-email-viacheslavo@mellanox.com>\n\t<1556339577-18185-1-git-send-email-viacheslavo@mellanox.com>", "Subject": "[dpdk-dev] [PATCH v3 2/2] net/mlx5: update memory event callback\n\tfor shared context", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Mellanox mlx5 PMD implements the list of devices to process the memory\nfree events to reflect the actual memory state to Memory Regions.\nBecause this list contains the devices and devices may share the\nsame context the callback routine may be called multiple times\nwith the same parameter, that is not optimal. This patch modifies\nthe list to contain the device contexts instead of device objects\nand shared context is included in the list only once.\n\nSigned-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>\n---\n drivers/net/mlx5/mlx5.c | 6 +--\n drivers/net/mlx5/mlx5.h | 6 +--\n drivers/net/mlx5/mlx5_mr.c | 91 +++++++++++++++++++++-------------------------\n 3 files changed, 48 insertions(+), 55 deletions(-)", "diff": "diff --git a/drivers/net/mlx5/mlx5.c b/drivers/net/mlx5/mlx5.c\nindex b563e0f..de85e85 100644\n--- a/drivers/net/mlx5/mlx5.c\n+++ b/drivers/net/mlx5/mlx5.c\n@@ -673,9 +673,9 @@ struct mlx5_dev_spawn_data {\n \tmlx5_mprq_free_mp(dev);\n \t/* Remove from memory callback device list. */\n \trte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock);\n-\tLIST_REMOVE(priv, mem_event_cb);\n-\trte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);\n \tassert(priv->sh);\n+\tLIST_REMOVE(priv->sh, mem_event_cb);\n+\trte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);\n \tmlx5_free_shared_dr(priv);\n \tif (priv->rss_conf.rss_key != NULL)\n \t\trte_free(priv->rss_conf.rss_key);\n@@ -1574,7 +1574,7 @@ struct mlx5_dev_spawn_data {\n \t/* Add device to memory callback list. */\n \trte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock);\n \tLIST_INSERT_HEAD(&mlx5_shared_data->mem_event_cb_list,\n-\t\t\t priv, mem_event_cb);\n+\t\t\t sh, mem_event_cb);\n \trte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);\n \treturn eth_dev;\n error:\ndiff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h\nindex 2575732..82fcb29 100644\n--- a/drivers/net/mlx5/mlx5.h\n+++ b/drivers/net/mlx5/mlx5.h\n@@ -99,7 +99,7 @@ struct mlx5_switch_info {\n \tuint64_t switch_id; /**< Switch identifier. */\n };\n \n-LIST_HEAD(mlx5_dev_list, mlx5_priv);\n+LIST_HEAD(mlx5_dev_list, mlx5_ibv_shared);\n \n /* Shared data between primary and secondary processes. */\n struct mlx5_shared_data {\n@@ -276,6 +276,8 @@ struct mlx5_ibv_shared {\n \tchar ibdev_path[IBV_SYSFS_PATH_MAX]; /* IB device path for secondary */\n \tstruct ibv_device_attr_ex device_attr; /* Device properties. */\n \tstruct rte_pci_device *pci_dev; /* Backend PCI device. */\n+\tLIST_ENTRY(mlx5_ibv_shared) mem_event_cb;\n+\t/**< Called by memory event callback. */\n \tstruct {\n \t\tuint32_t dev_gen; /* Generation number to flush local caches. */\n \t\trte_rwlock_t rwlock; /* MR Lock. */\n@@ -322,8 +324,6 @@ struct mlx5_proc_priv {\n \t((struct mlx5_proc_priv *)rte_eth_devices[port_id].process_private)\n \n struct mlx5_priv {\n-\tLIST_ENTRY(mlx5_priv) mem_event_cb;\n-\t/**< Called by memory event callback. */\n \tstruct rte_eth_dev_data *dev_data; /* Pointer to device data. */\n \tstruct mlx5_ibv_shared *sh; /* Shared IB device context. */\n \tuint32_t ibv_port; /* IB device port number. */\ndiff --git a/drivers/net/mlx5/mlx5_mr.c b/drivers/net/mlx5/mlx5_mr.c\nindex a7a63b1..66e8e87 100644\n--- a/drivers/net/mlx5/mlx5_mr.c\n+++ b/drivers/net/mlx5/mlx5_mr.c\n@@ -327,7 +327,7 @@ struct mr_update_mp_data {\n * mlx5_mr_create() on miss.\n *\n * @param dev\n- * Pointer to Ethernet device.\n+ * Pointer to Ethernet device shared context.\n * @param mr\n * Pointer to MR to insert.\n *\n@@ -335,13 +335,12 @@ struct mr_update_mp_data {\n * 0 on success, -1 on failure.\n */\n static int\n-mr_insert_dev_cache(struct rte_eth_dev *dev, struct mlx5_mr *mr)\n+mr_insert_dev_cache(struct mlx5_ibv_shared *sh, struct mlx5_mr *mr)\n {\n-\tstruct mlx5_priv *priv = dev->data->dev_private;\n \tunsigned int n;\n \n-\tDRV_LOG(DEBUG, \"port %u inserting MR(%p) to global cache\",\n-\t\tdev->data->port_id, (void *)mr);\n+\tDRV_LOG(DEBUG, \"device %s inserting MR(%p) to global cache\",\n+\t\tsh->ibdev_name, (void *)mr);\n \tfor (n = 0; n < mr->ms_bmp_n; ) {\n \t\tstruct mlx5_mr_cache entry;\n \n@@ -350,7 +349,7 @@ struct mr_update_mp_data {\n \t\tn = mr_find_next_chunk(mr, &entry, n);\n \t\tif (!entry.end)\n \t\t\tbreak;\n-\t\tif (mr_btree_insert(&priv->sh->mr.cache, &entry) < 0) {\n+\t\tif (mr_btree_insert(&sh->mr.cache, &entry) < 0) {\n \t\t\t/*\n \t\t\t * Overflowed, but the global table cannot be expanded\n \t\t\t * because of deadlock.\n@@ -364,8 +363,8 @@ struct mr_update_mp_data {\n /**\n * Look up address in the original global MR list.\n *\n- * @param dev\n- * Pointer to Ethernet device.\n+ * @param sh\n+ * Pointer to Ethernet device shared context.\n * @param[out] entry\n * Pointer to returning MR cache entry. If no match, this will not be updated.\n * @param addr\n@@ -375,14 +374,13 @@ struct mr_update_mp_data {\n * Found MR on match, NULL otherwise.\n */\n static struct mlx5_mr *\n-mr_lookup_dev_list(struct rte_eth_dev *dev, struct mlx5_mr_cache *entry,\n+mr_lookup_dev_list(struct mlx5_ibv_shared *sh, struct mlx5_mr_cache *entry,\n \t\t uintptr_t addr)\n {\n-\tstruct mlx5_priv *priv = dev->data->dev_private;\n \tstruct mlx5_mr *mr;\n \n \t/* Iterate all the existing MRs. */\n-\tLIST_FOREACH(mr, &priv->sh->mr.mr_list, mr) {\n+\tLIST_FOREACH(mr, &sh->mr.mr_list, mr) {\n \t\tunsigned int n;\n \n \t\tif (mr->ms_n == 0)\n@@ -406,7 +404,7 @@ struct mr_update_mp_data {\n * Look up address on device.\n *\n * @param dev\n- * Pointer to Ethernet device.\n+ * Pointer to Ethernet device shared context.\n * @param[out] entry\n * Pointer to returning MR cache entry. If no match, this will not be updated.\n * @param addr\n@@ -416,11 +414,9 @@ struct mr_update_mp_data {\n * Searched LKey on success, UINT32_MAX on failure and rte_errno is set.\n */\n static uint32_t\n-mr_lookup_dev(struct rte_eth_dev *dev, struct mlx5_mr_cache *entry,\n+mr_lookup_dev(struct mlx5_ibv_shared *sh, struct mlx5_mr_cache *entry,\n \t uintptr_t addr)\n {\n-\tstruct mlx5_priv *priv = dev->data->dev_private;\n-\tstruct mlx5_ibv_shared *sh = priv->sh;\n \tuint16_t idx;\n \tuint32_t lkey = UINT32_MAX;\n \tstruct mlx5_mr *mr;\n@@ -437,7 +433,7 @@ struct mr_update_mp_data {\n \t\t\t*entry = (*sh->mr.cache.table)[idx];\n \t} else {\n \t\t/* Falling back to the slowest path. */\n-\t\tmr = mr_lookup_dev_list(dev, entry, addr);\n+\t\tmr = mr_lookup_dev_list(sh, entry, addr);\n \t\tif (mr != NULL)\n \t\t\tlkey = entry->lkey;\n \t}\n@@ -550,7 +546,7 @@ struct mr_update_mp_data {\n \t}\n \trte_rwlock_read_lock(&priv->sh->mr.rwlock);\n \t/* Fill in output data. */\n-\tmr_lookup_dev(dev, entry, addr);\n+\tmr_lookup_dev(priv->sh, entry, addr);\n \t/* Lookup can't fail. */\n \tassert(entry->lkey != UINT32_MAX);\n \trte_rwlock_read_unlock(&priv->sh->mr.rwlock);\n@@ -716,7 +712,7 @@ struct mr_update_mp_data {\n \t * Check the address is really missing. If other thread already created\n \t * one or it is not found due to overflow, abort and return.\n \t */\n-\tif (mr_lookup_dev(dev, entry, addr) != UINT32_MAX) {\n+\tif (mr_lookup_dev(sh, entry, addr) != UINT32_MAX) {\n \t\t/*\n \t\t * Insert to the global cache table. It may fail due to\n \t\t * low-on-memory. Then, this entry will have to be searched\n@@ -746,7 +742,7 @@ struct mr_update_mp_data {\n \t\tmemset(&ret, 0, sizeof(ret));\n \t\tstart = data_re.start + n * msl->page_sz;\n \t\t/* Exclude memsegs already registered by other MRs. */\n-\t\tif (mr_lookup_dev(dev, &ret, start) == UINT32_MAX) {\n+\t\tif (mr_lookup_dev(sh, &ret, start) == UINT32_MAX) {\n \t\t\t/*\n \t\t\t * Start from the first unregistered memseg in the\n \t\t\t * extended range.\n@@ -788,9 +784,9 @@ struct mr_update_mp_data {\n \t data.start, data.end, rte_cpu_to_be_32(mr->ibv_mr->lkey),\n \t mr->ms_base_idx, mr->ms_n, mr->ms_bmp_n);\n \t/* Insert to the global cache table. */\n-\tmr_insert_dev_cache(dev, mr);\n+\tmr_insert_dev_cache(sh, mr);\n \t/* Fill in output data. */\n-\tmr_lookup_dev(dev, entry, addr);\n+\tmr_lookup_dev(sh, entry, addr);\n \t/* Lookup can't fail. */\n \tassert(entry->lkey != UINT32_MAX);\n \trte_rwlock_write_unlock(&sh->mr.rwlock);\n@@ -848,23 +844,21 @@ struct mr_update_mp_data {\n /**\n * Rebuild the global B-tree cache of device from the original MR list.\n *\n- * @param dev\n- * Pointer to Ethernet device.\n+ * @param sh\n+ * Pointer to Ethernet device shared context.\n */\n static void\n-mr_rebuild_dev_cache(struct rte_eth_dev *dev)\n+mr_rebuild_dev_cache(struct mlx5_ibv_shared *sh)\n {\n-\tstruct mlx5_priv *priv = dev->data->dev_private;\n-\tstruct mlx5_ibv_shared *sh = priv->sh;\n \tstruct mlx5_mr *mr;\n \n-\tDRV_LOG(DEBUG, \"port %u rebuild dev cache[]\", dev->data->port_id);\n+\tDRV_LOG(DEBUG, \"device %s rebuild dev cache[]\", sh->ibdev_name);\n \t/* Flush cache to rebuild. */\n \tsh->mr.cache.len = 1;\n \tsh->mr.cache.overflow = 0;\n \t/* Iterate all the existing MRs. */\n \tLIST_FOREACH(mr, &sh->mr.mr_list, mr)\n-\t\tif (mr_insert_dev_cache(dev, mr) < 0)\n+\t\tif (mr_insert_dev_cache(sh, mr) < 0)\n \t\t\treturn;\n }\n \n@@ -879,26 +873,25 @@ struct mr_update_mp_data {\n * The global cache must be rebuilt if there's any change and this event has to\n * be propagated to dataplane threads to flush the local caches.\n *\n- * @param dev\n- * Pointer to Ethernet device.\n+ * @param sh\n+ * Pointer to the Ethernet device shared context.\n * @param addr\n * Address of freed memory.\n * @param len\n * Size of freed memory.\n */\n static void\n-mlx5_mr_mem_event_free_cb(struct rte_eth_dev *dev, const void *addr, size_t len)\n+mlx5_mr_mem_event_free_cb(struct mlx5_ibv_shared *sh,\n+\t\t\t const void *addr, size_t len)\n {\n-\tstruct mlx5_priv *priv = dev->data->dev_private;\n-\tstruct mlx5_ibv_shared *sh = priv->sh;\n \tconst struct rte_memseg_list *msl;\n \tstruct mlx5_mr *mr;\n \tint ms_n;\n \tint i;\n \tint rebuild = 0;\n \n-\tDEBUG(\"port %u free callback: addr=%p, len=%zu\",\n-\t dev->data->port_id, addr, len);\n+\tDEBUG(\"device %s free callback: addr=%p, len=%zu\",\n+\t sh->ibdev_name, addr, len);\n \tmsl = rte_mem_virt2memseg_list(addr);\n \t/* addr and len must be page-aligned. */\n \tassert((uintptr_t)addr == RTE_ALIGN((uintptr_t)addr, msl->page_sz));\n@@ -915,7 +908,7 @@ struct mr_update_mp_data {\n \n \t\t/* Find MR having this memseg. */\n \t\tstart = (uintptr_t)addr + i * msl->page_sz;\n-\t\tmr = mr_lookup_dev_list(dev, &entry, start);\n+\t\tmr = mr_lookup_dev_list(sh, &entry, start);\n \t\tif (mr == NULL)\n \t\t\tcontinue;\n \t\tassert(mr->msl); /* Can't be external memory. */\n@@ -926,14 +919,14 @@ struct mr_update_mp_data {\n \t\tpos = ms_idx - mr->ms_base_idx;\n \t\tassert(rte_bitmap_get(mr->ms_bmp, pos));\n \t\tassert(pos < mr->ms_bmp_n);\n-\t\tDEBUG(\"port %u MR(%p): clear bitmap[%u] for addr %p\",\n-\t\t dev->data->port_id, (void *)mr, pos, (void *)start);\n+\t\tDEBUG(\"device %s MR(%p): clear bitmap[%u] for addr %p\",\n+\t\t sh->ibdev_name, (void *)mr, pos, (void *)start);\n \t\trte_bitmap_clear(mr->ms_bmp, pos);\n \t\tif (--mr->ms_n == 0) {\n \t\t\tLIST_REMOVE(mr, mr);\n \t\t\tLIST_INSERT_HEAD(&sh->mr.mr_free_list, mr, mr);\n-\t\t\tDEBUG(\"port %u remove MR(%p) from list\",\n-\t\t\t dev->data->port_id, (void *)mr);\n+\t\t\tDEBUG(\"device %s remove MR(%p) from list\",\n+\t\t\t sh->ibdev_name, (void *)mr);\n \t\t}\n \t\t/*\n \t\t * MR is fragmented or will be freed. the global cache must be\n@@ -942,7 +935,7 @@ struct mr_update_mp_data {\n \t\trebuild = 1;\n \t}\n \tif (rebuild) {\n-\t\tmr_rebuild_dev_cache(dev);\n+\t\tmr_rebuild_dev_cache(sh);\n \t\t/*\n \t\t * Flush local caches by propagating invalidation across cores.\n \t\t * rte_smp_wmb() is enough to synchronize this event. If one of\n@@ -975,7 +968,7 @@ struct mr_update_mp_data {\n mlx5_mr_mem_event_cb(enum rte_mem_event event_type, const void *addr,\n \t\t size_t len, void *arg __rte_unused)\n {\n-\tstruct mlx5_priv *priv;\n+\tstruct mlx5_ibv_shared *sh;\n \tstruct mlx5_dev_list *dev_list = &mlx5_shared_data->mem_event_cb_list;\n \n \t/* Must be called from the primary process. */\n@@ -984,8 +977,8 @@ struct mr_update_mp_data {\n \tcase RTE_MEM_EVENT_FREE:\n \t\trte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock);\n \t\t/* Iterate all the existing mlx5 devices. */\n-\t\tLIST_FOREACH(priv, dev_list, mem_event_cb)\n-\t\t\tmlx5_mr_mem_event_free_cb(ETH_DEV(priv), addr, len);\n+\t\tLIST_FOREACH(sh, dev_list, mem_event_cb)\n+\t\t\tmlx5_mr_mem_event_free_cb(sh, addr, len);\n \t\trte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);\n \t\tbreak;\n \tcase RTE_MEM_EVENT_ALLOC:\n@@ -1276,7 +1269,7 @@ struct mr_update_mp_data {\n \tassert(rte_eal_process_type() == RTE_PROC_PRIMARY);\n \t/* If already registered, it should return. */\n \trte_rwlock_read_lock(&sh->mr.rwlock);\n-\tlkey = mr_lookup_dev(dev, &entry, addr);\n+\tlkey = mr_lookup_dev(sh, &entry, addr);\n \trte_rwlock_read_unlock(&sh->mr.rwlock);\n \tif (lkey != UINT32_MAX)\n \t\treturn;\n@@ -1294,7 +1287,7 @@ struct mr_update_mp_data {\n \trte_rwlock_write_lock(&sh->mr.rwlock);\n \tLIST_INSERT_HEAD(&sh->mr.mr_list, mr, mr);\n \t/* Insert to the global cache table. */\n-\tmr_insert_dev_cache(dev, mr);\n+\tmr_insert_dev_cache(sh, mr);\n \trte_rwlock_write_unlock(&sh->mr.rwlock);\n \t/* Insert to the local cache table */\n \tmlx5_mr_addr2mr_bh(dev, mr_ctrl, addr);\n@@ -1365,7 +1358,7 @@ struct mr_update_mp_data {\n \trte_rwlock_write_lock(&sh->mr.rwlock);\n \tLIST_INSERT_HEAD(&sh->mr.mr_list, mr, mr);\n \t/* Insert to the global cache table. */\n-\tmr_insert_dev_cache(dev, mr);\n+\tmr_insert_dev_cache(sh, mr);\n \trte_rwlock_write_unlock(&sh->mr.rwlock);\n \treturn 0;\n }\n@@ -1405,7 +1398,7 @@ struct mr_update_mp_data {\n \tpriv = dev->data->dev_private;\n \tsh = priv->sh;\n \trte_rwlock_read_lock(&sh->mr.rwlock);\n-\tmr = mr_lookup_dev_list(dev, &entry, (uintptr_t)addr);\n+\tmr = mr_lookup_dev_list(sh, &entry, (uintptr_t)addr);\n \tif (!mr) {\n \t\trte_rwlock_read_unlock(&sh->mr.rwlock);\n \t\tDRV_LOG(WARNING, \"address 0x%\" PRIxPTR \" wasn't registered \"\n@@ -1418,7 +1411,7 @@ struct mr_update_mp_data {\n \tLIST_INSERT_HEAD(&sh->mr.mr_free_list, mr, mr);\n \tDEBUG(\"port %u remove MR(%p) from list\", dev->data->port_id,\n \t (void *)mr);\n-\tmr_rebuild_dev_cache(dev);\n+\tmr_rebuild_dev_cache(sh);\n \t/*\n \t * Flush local caches by propagating invalidation across cores.\n \t * rte_smp_wmb() is enough to synchronize this event. If one of\n", "prefixes": [ "v3", "2/2" ] }