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{
    "id": 52538,
    "url": "http://patches.dpdk.org/api/patches/52538/?format=api",
    "web_url": "http://patches.dpdk.org/project/dpdk/patch/1554877672-19745-12-git-send-email-rosen.xu@intel.com/",
    "project": {
        "id": 1,
        "url": "http://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<1554877672-19745-12-git-send-email-rosen.xu@intel.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/1554877672-19745-12-git-send-email-rosen.xu@intel.com",
    "date": "2019-04-10T06:27:49",
    "name": "[v7,11/14] raw/ifpga_rawdev: add eth group driver",
    "commit_ref": null,
    "pull_url": null,
    "state": "changes-requested",
    "archived": true,
    "hash": "178eb6146ab6e1978e109c9e194650618b44e66b",
    "submitter": {
        "id": 946,
        "url": "http://patches.dpdk.org/api/people/946/?format=api",
        "name": "Xu, Rosen",
        "email": "rosen.xu@intel.com"
    },
    "delegate": {
        "id": 319,
        "url": "http://patches.dpdk.org/api/users/319/?format=api",
        "username": "fyigit",
        "first_name": "Ferruh",
        "last_name": "Yigit",
        "email": "ferruh.yigit@amd.com"
    },
    "mbox": "http://patches.dpdk.org/project/dpdk/patch/1554877672-19745-12-git-send-email-rosen.xu@intel.com/mbox/",
    "series": [
        {
            "id": 4223,
            "url": "http://patches.dpdk.org/api/series/4223/?format=api",
            "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=4223",
            "date": "2019-04-10T06:27:38",
            "name": "Add patch set for IPN3KE",
            "version": 7,
            "mbox": "http://patches.dpdk.org/series/4223/mbox/"
        }
    ],
    "comments": "http://patches.dpdk.org/api/patches/52538/comments/",
    "check": "success",
    "checks": "http://patches.dpdk.org/api/patches/52538/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@dpdk.org",
        "Delivered-To": "patchwork@dpdk.org",
        "Received": [
            "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 211331B10E;\n\tWed, 10 Apr 2019 08:27:50 +0200 (CEST)",
            "from mga18.intel.com (mga18.intel.com [134.134.136.126])\n\tby dpdk.org (Postfix) with ESMTP id 549501B0FF\n\tfor <dev@dpdk.org>; Wed, 10 Apr 2019 08:27:45 +0200 (CEST)",
            "from fmsmga003.fm.intel.com ([10.253.24.29])\n\tby orsmga106.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t09 Apr 2019 23:27:44 -0700",
            "from dpdkx8602.sh.intel.com ([10.67.110.200])\n\tby FMSMGA003.fm.intel.com with ESMTP; 09 Apr 2019 23:27:41 -0700"
        ],
        "X-Amp-Result": "SKIPPED(no attachment in message)",
        "X-Amp-File-Uploaded": "False",
        "X-ExtLoop1": "1",
        "X-IronPort-AV": "E=Sophos;i=\"5.60,332,1549958400\"; d=\"scan'208\";a=\"147981011\"",
        "From": "Rosen Xu <rosen.xu@intel.com>",
        "To": "dev@dpdk.org",
        "Cc": "ferruh.yigit@intel.com, tianfei.zhang@intel.com, dan.wei@intel.com,\n\trosen.xu@intel.com, andy.pei@intel.com, qiming.yang@intel.com,\n\thaiyue.wang@intel.com, santos.chen@intel.com, zhang.zhang@intel.com, \n\tdavid.lomartire@intel.com, jia.hu@intel.com",
        "Date": "Wed, 10 Apr 2019 14:27:49 +0800",
        "Message-Id": "<1554877672-19745-12-git-send-email-rosen.xu@intel.com>",
        "X-Mailer": "git-send-email 1.8.3.1",
        "In-Reply-To": "<1554877672-19745-1-git-send-email-rosen.xu@intel.com>",
        "References": "<1551338000-120348-1-git-send-email-rosen.xu@intel.com>\n\t<1554877672-19745-1-git-send-email-rosen.xu@intel.com>",
        "Subject": "[dpdk-dev] [PATCH v7 11/14] raw/ifpga_rawdev: add eth group driver",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.15",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "From: Tianfei zhang <tianfei.zhang@intel.com>\n\nThere is two eth group devices in PAC N3000 card,\neach eth group include PHY device and MAC device. Exposing\nAPIs for DPDK PMD driver to access those devices.\n\nSigned-off-by: Tianfei Zhang <tianfei.zhang@intel.com>\n---\n drivers/raw/ifpga_rawdev/base/Makefile            |   1 +\n drivers/raw/ifpga_rawdev/base/ifpga_api.c         |  74 ++++++-\n drivers/raw/ifpga_rawdev/base/ifpga_defines.h     |  39 ++++\n drivers/raw/ifpga_rawdev/base/ifpga_enumerate.c   |   6 +\n drivers/raw/ifpga_rawdev/base/ifpga_feature_dev.c |   2 +\n drivers/raw/ifpga_rawdev/base/ifpga_feature_dev.h |  12 ++\n drivers/raw/ifpga_rawdev/base/ifpga_fme.c         | 250 ++++++++++++++++++++++\n drivers/raw/ifpga_rawdev/base/ifpga_hw.h          |   7 +\n drivers/raw/ifpga_rawdev/base/meson.build         |   1 +\n drivers/raw/ifpga_rawdev/base/opae_eth_group.c    | 145 +++++++++++++\n drivers/raw/ifpga_rawdev/base/opae_eth_group.h    |  96 +++++++++\n drivers/raw/ifpga_rawdev/base/opae_hw_api.c       | 149 +++++++++++++\n drivers/raw/ifpga_rawdev/base/opae_hw_api.h       |  27 +++\n drivers/raw/ifpga_rawdev/base/opae_intel_max10.h  |  42 +++-\n drivers/raw/ifpga_rawdev/base/opae_osdep.h        |  16 +-\n 15 files changed, 858 insertions(+), 9 deletions(-)\n create mode 100644 drivers/raw/ifpga_rawdev/base/opae_eth_group.c\n create mode 100644 drivers/raw/ifpga_rawdev/base/opae_eth_group.h",
    "diff": "diff --git a/drivers/raw/ifpga_rawdev/base/Makefile b/drivers/raw/ifpga_rawdev/base/Makefile\nindex edb538f..c5bbcbd 100644\n--- a/drivers/raw/ifpga_rawdev/base/Makefile\n+++ b/drivers/raw/ifpga_rawdev/base/Makefile\n@@ -27,5 +27,6 @@ SRCS-y += opae_spi_transaction.c\n SRCS-y += opae_intel_max10.c\n SRCS-y += opae_i2c.c\n SRCS-y += opae_at24_eeprom.c\n+SRCS-y += opae_eth_group.c\n \n SRCS-y += $(wildcard $(SRCDIR)/base/$(OSDEP)/*.c)\ndiff --git a/drivers/raw/ifpga_rawdev/base/ifpga_api.c b/drivers/raw/ifpga_rawdev/base/ifpga_api.c\nindex c447b3c..3ddbcdc 100644\n--- a/drivers/raw/ifpga_rawdev/base/ifpga_api.c\n+++ b/drivers/raw/ifpga_rawdev/base/ifpga_api.c\n@@ -170,7 +170,6 @@ struct opae_accelerator_ops ifpga_acc_ops = {\n };\n \n /* Bridge APIs */\n-\n static int ifpga_br_reset(struct opae_bridge *br)\n {\n \tstruct ifpga_port_hw *port = br->data;\n@@ -192,8 +191,26 @@ static int ifpga_mgr_flash(struct opae_manager *mgr, int id, void *buf,\n \treturn ifpga_pr(hw, id, buf, size, status);\n }\n \n+static int ifpga_mgr_get_eth_group_region_info(struct opae_manager *mgr,\n+\t\tstruct opae_eth_group_region_info *info)\n+{\n+\tstruct ifpga_fme_hw *fme = mgr->data;\n+\n+\tif (info->group_id >= MAX_ETH_GROUP_DEVICES)\n+\t\treturn -EINVAL;\n+\n+\tinfo->phys_addr = fme->eth_group_region[info->group_id].phys_addr;\n+\tinfo->addr = fme->eth_group_region[info->group_id].addr;\n+\tinfo->len = fme->eth_group_region[info->group_id].len;\n+\n+\tinfo->mem_idx = fme->nums_acc_region + info->group_id;\n+\n+\treturn 0;\n+}\n+\n struct opae_manager_ops ifpga_mgr_ops = {\n \t.flash = ifpga_mgr_flash,\n+\t.get_eth_group_region_info = ifpga_mgr_get_eth_group_region_info,\n };\n \n static int ifpga_mgr_read_mac_rom(struct opae_manager *mgr, int offset,\n@@ -212,10 +229,65 @@ static int ifpga_mgr_write_mac_rom(struct opae_manager *mgr, int offset,\n \treturn fme_mgr_write_mac_rom(fme, offset, buf, size);\n }\n \n+static int ifpga_mgr_get_eth_group_nums(struct opae_manager *mgr)\n+{\n+\tstruct ifpga_fme_hw *fme = mgr->data;\n+\n+\treturn fme_mgr_get_eth_group_nums(fme);\n+}\n+\n+static int ifpga_mgr_get_eth_group_info(struct opae_manager *mgr,\n+\t\tu8 group_id, struct opae_eth_group_info *info)\n+{\n+\tstruct ifpga_fme_hw *fme = mgr->data;\n+\n+\treturn fme_mgr_get_eth_group_info(fme, group_id, info);\n+}\n+\n+static int ifpga_mgr_eth_group_reg_read(struct opae_manager *mgr, u8 group_id,\n+\t\tu8 type, u8 index, u16 addr, u32 *data)\n+{\n+\tstruct ifpga_fme_hw *fme = mgr->data;\n+\n+\treturn fme_mgr_eth_group_read_reg(fme, group_id,\n+\t\t\ttype, index, addr, data);\n+}\n+\n+static int ifpga_mgr_eth_group_reg_write(struct opae_manager *mgr, u8 group_id,\n+\t\tu8 type, u8 index, u16 addr, u32 data)\n+{\n+\tstruct ifpga_fme_hw *fme = mgr->data;\n+\n+\treturn fme_mgr_eth_group_write_reg(fme, group_id,\n+\t\t\ttype, index, addr, data);\n+}\n+\n+static int ifpga_mgr_get_retimer_info(struct opae_manager *mgr,\n+\t\tstruct opae_retimer_info *info)\n+{\n+\tstruct ifpga_fme_hw *fme = mgr->data;\n+\n+\treturn fme_mgr_get_retimer_info(fme, info);\n+}\n+\n+static int ifpga_mgr_get_retimer_status(struct opae_manager *mgr,\n+\t\tstruct opae_retimer_status *status)\n+{\n+\tstruct ifpga_fme_hw *fme = mgr->data;\n+\n+\treturn fme_mgr_get_retimer_status(fme, status);\n+}\n+\n /* Network APIs in FME */\n struct opae_manager_networking_ops ifpga_mgr_network_ops = {\n \t.read_mac_rom = ifpga_mgr_read_mac_rom,\n \t.write_mac_rom = ifpga_mgr_write_mac_rom,\n+\t.get_eth_group_nums = ifpga_mgr_get_eth_group_nums,\n+\t.get_eth_group_info = ifpga_mgr_get_eth_group_info,\n+\t.eth_group_reg_read = ifpga_mgr_eth_group_reg_read,\n+\t.eth_group_reg_write = ifpga_mgr_eth_group_reg_write,\n+\t.get_retimer_info = ifpga_mgr_get_retimer_info,\n+\t.get_retimer_status = ifpga_mgr_get_retimer_status,\n };\n \n /* Adapter APIs */\ndiff --git a/drivers/raw/ifpga_rawdev/base/ifpga_defines.h b/drivers/raw/ifpga_rawdev/base/ifpga_defines.h\nindex 62f71c7..b7151ca 100644\n--- a/drivers/raw/ifpga_rawdev/base/ifpga_defines.h\n+++ b/drivers/raw/ifpga_rawdev/base/ifpga_defines.h\n@@ -22,6 +22,7 @@\n #define FME_FEATURE_MAX10_SPI       \"fme_max10_spi\"\n #define FME_FEATURE_NIOS_SPI        \"fme_nios_spi\"\n #define FME_FEATURE_I2C_MASTER      \"fme_i2c_master\"\n+#define FME_FEATURE_ETH_GROUP       \"fme_eth_group\"\n \n #define PORT_FEATURE_HEADER         \"port_hdr\"\n #define PORT_FEATURE_UAFU           \"port_uafu\"\n@@ -88,6 +89,7 @@ enum fpga_id_type {\n #define FME_FEATURE_ID_MAX10_SPI  0xe\n #define FME_FEATURE_ID_NIOS_SPI 0xd\n #define FME_FEATURE_ID_I2C_MASTER  0xf\n+#define FME_FEATURE_ID_ETH_GROUP 0x10\n \n #define PORT_FEATURE_ID_HEADER FEATURE_ID_FIU_HEADER\n #define PORT_FEATURE_ID_ERROR 0x10\n@@ -1661,5 +1663,42 @@ struct bts_header {\n \t(((bts_hdr)->guid_h == GBS_GUID_H) &&\t\t\\\n \t((bts_hdr)->guid_l == GBS_GUID_L))\n \n+/* bitstream id definition */\n+struct fme_bitstream_id {\n+\tunion {\n+\t\tu64 id;\n+\t\tstruct {\n+\t\t\tu64 hash:32;\n+\t\t\tu64 interface:4;\n+\t\t\tu64 reserved:12;\n+\t\t\tu64 debug:4;\n+\t\t\tu64 patch:4;\n+\t\t\tu64 minor:4;\n+\t\t\tu64 major:4;\n+\t\t};\n+\t};\n+};\n+\n+enum board_interface {\n+\tVC_8_10G = 0,\n+\tVC_4_25G = 1,\n+\tVC_2_1_25 = 2,\n+\tVC_4_25G_2_25G = 3,\n+\tVC_2_2_25G = 4,\n+};\n+\n+struct ifpga_fme_board_info {\n+\tenum board_interface type;\n+\tu32 build_hash;\n+\tu32 debug_version;\n+\tu32 patch_version;\n+\tu32 minor_version;\n+\tu32 major_version;\n+\tu32 nums_of_retimer;\n+\tu32 ports_per_retimer;\n+\tu32 nums_of_fvl;\n+\tu32 ports_per_fvl;\n+};\n+\n #pragma pack(pop)\n #endif /* _BASE_IFPGA_DEFINES_H_ */\ndiff --git a/drivers/raw/ifpga_rawdev/base/ifpga_enumerate.c b/drivers/raw/ifpga_rawdev/base/ifpga_enumerate.c\nindex 666dae1..44086c1 100644\n--- a/drivers/raw/ifpga_rawdev/base/ifpga_enumerate.c\n+++ b/drivers/raw/ifpga_rawdev/base/ifpga_enumerate.c\n@@ -232,6 +232,7 @@ static int build_info_commit_dev(struct build_feature_devs_info *binfo)\n \tstruct opae_bridge *br;\n \tstruct opae_accelerator *acc;\n \tstruct ifpga_port_hw *port;\n+\tstruct ifpga_fme_hw *fme;\n \tstruct feature *feature;\n \n \tif (!binfo->fiu)\n@@ -264,8 +265,13 @@ static int build_info_commit_dev(struct build_feature_devs_info *binfo)\n \t\t}\n \n \t\tacc->br = br;\n+\t\tif (hw->adapter->mgr)\n+\t\t\tacc->mgr = hw->adapter->mgr;\n \t\tacc->index = br->id;\n \n+\t\tfme = &hw->fme;\n+\t\tfme->nums_acc_region = info->num_regions;\n+\n \t\topae_adapter_add_acc(hw->adapter, acc);\n \n \t} else if (binfo->current_type == FME_ID) {\ndiff --git a/drivers/raw/ifpga_rawdev/base/ifpga_feature_dev.c b/drivers/raw/ifpga_rawdev/base/ifpga_feature_dev.c\nindex 0454f80..5ebc449 100644\n--- a/drivers/raw/ifpga_rawdev/base/ifpga_feature_dev.c\n+++ b/drivers/raw/ifpga_rawdev/base/ifpga_feature_dev.c\n@@ -203,6 +203,8 @@ int port_clear_error(struct ifpga_port_hw *port)\n \t&fme_nios_spi_master_ops),},\n \t{FEATURE_DRV(FME_FEATURE_ID_I2C_MASTER, FME_FEATURE_I2C_MASTER,\n \t&fme_i2c_master_ops),},\n+\t{FEATURE_DRV(FME_FEATURE_ID_ETH_GROUP, FME_FEATURE_ETH_GROUP,\n+\t&fme_eth_group_ops),},\n \t{0, NULL, NULL}, /* end of arrary */\n };\n \ndiff --git a/drivers/raw/ifpga_rawdev/base/ifpga_feature_dev.h b/drivers/raw/ifpga_rawdev/base/ifpga_feature_dev.h\nindex a398a98..3f63f5a 100644\n--- a/drivers/raw/ifpga_rawdev/base/ifpga_feature_dev.h\n+++ b/drivers/raw/ifpga_rawdev/base/ifpga_feature_dev.h\n@@ -173,6 +173,7 @@ int do_pr(struct ifpga_hw *hw, u32 port_id, void *buffer, u32 size,\n extern struct feature_ops fme_emif_ops;\n extern struct feature_ops fme_spi_master_ops;\n extern struct feature_ops fme_i2c_master_ops;\n+extern struct feature_ops fme_eth_group_ops;\n extern struct feature_ops fme_nios_spi_master_ops;\n \n int port_get_prop(struct ifpga_port_hw *port, struct feature_prop *prop);\n@@ -204,4 +205,15 @@ int fme_mgr_read_mac_rom(struct ifpga_fme_hw *fme, int offset,\n \t\tvoid *buf, int size);\n int fme_mgr_write_mac_rom(struct ifpga_fme_hw *fme, int offset,\n \t\tvoid *buf, int size);\n+int fme_mgr_get_eth_group_nums(struct ifpga_fme_hw *fme);\n+int fme_mgr_get_eth_group_info(struct ifpga_fme_hw *fme,\n+\t\tu8 group_id, struct opae_eth_group_info *info);\n+int fme_mgr_eth_group_read_reg(struct ifpga_fme_hw *fme, u8 group_id,\n+\t\tu8 type, u8 index, u16 addr, u32 *data);\n+int fme_mgr_eth_group_write_reg(struct ifpga_fme_hw *fme, u8 group_id,\n+\t\tu8 type, u8 index, u16 addr, u32 data);\n+int fme_mgr_get_retimer_info(struct ifpga_fme_hw *fme,\n+\t\tstruct opae_retimer_info *info);\n+int fme_mgr_get_retimer_status(struct ifpga_fme_hw *fme,\n+\t\tstruct opae_retimer_status *status);\n #endif /* _IFPGA_FEATURE_DEV_H_ */\ndiff --git a/drivers/raw/ifpga_rawdev/base/ifpga_fme.c b/drivers/raw/ifpga_rawdev/base/ifpga_fme.c\nindex 95e022e..2cfb158 100644\n--- a/drivers/raw/ifpga_rawdev/base/ifpga_fme.c\n+++ b/drivers/raw/ifpga_rawdev/base/ifpga_fme.c\n@@ -769,6 +769,90 @@ struct feature_ops fme_emif_ops = {\n \t.uinit = fme_emif_uinit,\n };\n \n+static const char *board_type_to_string(u32 type)\n+{\n+\tswitch (type) {\n+\tcase VC_8_10G:\n+\t\treturn \"VC_8x10G\";\n+\tcase VC_4_25G:\n+\t\treturn \"VC_4x25G\";\n+\tcase VC_2_1_25:\n+\t\treturn \"VC_2x1x25G\";\n+\tcase VC_4_25G_2_25G:\n+\t\treturn \"VC_4x25G+2x25G\";\n+\tcase VC_2_2_25G:\n+\t\treturn \"VC_2x2x25G\";\n+\t}\n+\n+\treturn \"unknown\";\n+}\n+\n+static int board_type_to_info(u32 type,\n+\t\tstruct ifpga_fme_board_info *info)\n+{\n+\tswitch (type) {\n+\tcase VC_8_10G:\n+\t\tinfo->nums_of_retimer = 2;\n+\t\tinfo->ports_per_retimer = 4;\n+\t\tinfo->nums_of_fvl = 2;\n+\t\tinfo->ports_per_fvl = 4;\n+\t\tbreak;\n+\tcase VC_4_25G:\n+\t\tinfo->nums_of_retimer = 1;\n+\t\tinfo->ports_per_retimer = 4;\n+\t\tinfo->nums_of_fvl = 2;\n+\t\tinfo->ports_per_fvl = 2;\n+\t\tbreak;\n+\tcase VC_2_1_25:\n+\t\tinfo->nums_of_retimer = 2;\n+\t\tinfo->ports_per_retimer = 1;\n+\t\tinfo->nums_of_fvl = 1;\n+\t\tinfo->ports_per_fvl = 2;\n+\t\tbreak;\n+\tcase VC_2_2_25G:\n+\t\tinfo->nums_of_retimer = 2;\n+\t\tinfo->ports_per_retimer = 2;\n+\t\tinfo->nums_of_fvl = 2;\n+\t\tinfo->ports_per_fvl = 2;\n+\t\tbreak;\n+\tdefault:\n+\t\treturn -EINVAL;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int fme_get_board_interface(struct ifpga_fme_hw *fme)\n+{\n+\tstruct fme_bitstream_id id;\n+\n+\tif (fme_hdr_get_bitstream_id(fme, &id.id))\n+\t\treturn -EINVAL;\n+\n+\tfme->board_info.type = id.interface;\n+\tfme->board_info.build_hash = id.hash;\n+\tfme->board_info.debug_version = id.debug;\n+\tfme->board_info.major_version = id.major;\n+\tfme->board_info.minor_version = id.minor;\n+\n+\tdev_info(fme, \"board type: %s major_version:%u minor_version:%u build_hash:%u\\n\",\n+\t\t\tboard_type_to_string(fme->board_info.type),\n+\t\t\tfme->board_info.major_version,\n+\t\t\tfme->board_info.minor_version,\n+\t\t\tfme->board_info.build_hash);\n+\n+\tif (board_type_to_info(fme->board_info.type, &fme->board_info))\n+\t\treturn -EINVAL;\n+\n+\tdev_info(fme, \"get board info: nums_retimers %d ports_per_retimer %d nums_fvl %d ports_per_fvl %d\\n\",\n+\t\t\tfme->board_info.nums_of_retimer,\n+\t\t\tfme->board_info.ports_per_retimer,\n+\t\t\tfme->board_info.nums_of_fvl,\n+\t\t\tfme->board_info.ports_per_fvl);\n+\n+\treturn 0;\n+}\n+\n static int spi_self_checking(void)\n {\n \tu32 val;\n@@ -935,6 +1019,8 @@ static int fme_nios_spi_init(struct feature *feature)\n \t\tgoto release_dev;\n \t}\n \n+\tfme_get_board_interface(fme);\n+\n \tfme->max10_dev = max10;\n \n \t/* SPI self test */\n@@ -1027,6 +1113,45 @@ struct feature_ops fme_i2c_master_ops = {\n \t.uinit = fme_i2c_uninit,\n };\n \n+static int fme_eth_group_init(struct feature *feature)\n+{\n+\tstruct ifpga_fme_hw *fme = (struct ifpga_fme_hw *)feature->parent;\n+\tstruct eth_group_device *dev;\n+\n+\tdev = (struct eth_group_device *)eth_group_probe(feature->addr);\n+\tif (!dev)\n+\t\treturn -ENODEV;\n+\n+\tfme->eth_dev[dev->group_id] = dev;\n+\n+\tfme->eth_group_region[dev->group_id].addr =\n+\t\tfeature->addr;\n+\tfme->eth_group_region[dev->group_id].phys_addr =\n+\t\tfeature->phys_addr;\n+\tfme->eth_group_region[dev->group_id].len =\n+\t\tfeature->size;\n+\n+\tfme->nums_eth_dev++;\n+\n+\tdev_info(NULL, \"FME PHY Group %d Init.\\n\", dev->group_id);\n+\tdev_info(NULL, \"found %d eth group, addr %p phys_addr 0x%llx len %u\\n\",\n+\t\t\tdev->group_id, feature->addr,\n+\t\t\t(unsigned long long)feature->phys_addr,\n+\t\t\tfeature->size);\n+\n+\treturn 0;\n+}\n+\n+static void fme_eth_group_uinit(struct feature *feature)\n+{\n+\tUNUSED(feature);\n+}\n+\n+struct feature_ops fme_eth_group_ops = {\n+\t.init = fme_eth_group_init,\n+\t.uinit = fme_eth_group_uinit,\n+};\n+\n int fme_mgr_read_mac_rom(struct ifpga_fme_hw *fme, int offset,\n \t\tvoid *buf, int size)\n {\n@@ -1050,3 +1175,128 @@ int fme_mgr_write_mac_rom(struct ifpga_fme_hw *fme, int offset,\n \n \treturn at24_eeprom_write(dev, AT24512_SLAVE_ADDR, offset, buf, size);\n }\n+\n+static struct eth_group_device *get_eth_group_dev(struct ifpga_fme_hw *fme,\n+\t\tu8 group_id)\n+{\n+\tstruct eth_group_device *dev;\n+\n+\tif (group_id > (MAX_ETH_GROUP_DEVICES - 1))\n+\t\treturn NULL;\n+\n+\tdev = (struct eth_group_device *)fme->eth_dev[group_id];\n+\tif (!dev)\n+\t\treturn NULL;\n+\n+\tif (dev->status != ETH_GROUP_DEV_ATTACHED)\n+\t\treturn NULL;\n+\n+\treturn dev;\n+}\n+\n+int fme_mgr_get_eth_group_nums(struct ifpga_fme_hw *fme)\n+{\n+\treturn fme->nums_eth_dev;\n+}\n+\n+int fme_mgr_get_eth_group_info(struct ifpga_fme_hw *fme,\n+\t\tu8 group_id, struct opae_eth_group_info *info)\n+{\n+\tstruct eth_group_device *dev;\n+\n+\tdev = get_eth_group_dev(fme, group_id);\n+\tif (!dev)\n+\t\treturn -ENODEV;\n+\n+\tinfo->group_id = group_id;\n+\tinfo->speed = dev->speed;\n+\tinfo->nums_of_mac = dev->mac_num;\n+\tinfo->nums_of_phy = dev->phy_num;\n+\n+\treturn 0;\n+}\n+\n+int fme_mgr_eth_group_read_reg(struct ifpga_fme_hw *fme, u8 group_id,\n+\t\tu8 type, u8 index, u16 addr, u32 *data)\n+{\n+\tstruct eth_group_device *dev;\n+\n+\tdev = get_eth_group_dev(fme, group_id);\n+\tif (!dev)\n+\t\treturn -ENODEV;\n+\n+\treturn eth_group_read_reg(dev, type, index, addr, data);\n+}\n+\n+int fme_mgr_eth_group_write_reg(struct ifpga_fme_hw *fme, u8 group_id,\n+\t\tu8 type, u8 index, u16 addr, u32 data)\n+{\n+\tstruct eth_group_device *dev;\n+\n+\tdev = get_eth_group_dev(fme, group_id);\n+\tif (!dev)\n+\t\treturn -ENODEV;\n+\n+\treturn eth_group_write_reg(dev, type, index, addr, data);\n+}\n+\n+static int fme_get_eth_group_speed(struct ifpga_fme_hw *fme,\n+\t\tu8 group_id)\n+{\n+\tstruct eth_group_device *dev;\n+\n+\tdev = get_eth_group_dev(fme, group_id);\n+\tif (!dev)\n+\t\treturn -ENODEV;\n+\n+\treturn dev->speed;\n+}\n+\n+int fme_mgr_get_retimer_info(struct ifpga_fme_hw *fme,\n+\t\tstruct opae_retimer_info *info)\n+{\n+\tstruct intel_max10_device *dev;\n+\n+\tdev = (struct intel_max10_device *)fme->max10_dev;\n+\tif (!dev)\n+\t\treturn -ENODEV;\n+\n+\tinfo->nums_retimer = fme->board_info.nums_of_retimer;\n+\tinfo->ports_per_retimer = fme->board_info.ports_per_retimer;\n+\tinfo->nums_fvl = fme->board_info.nums_of_fvl;\n+\tinfo->ports_per_fvl = fme->board_info.ports_per_fvl;\n+\n+\t/* The speed of PKVL is identical the eth group's speed */\n+\tinfo->support_speed = fme_get_eth_group_speed(fme,\n+\t\t\tLINE_SIDE_GROUP_ID);\n+\n+\treturn 0;\n+}\n+\n+int fme_mgr_get_retimer_status(struct ifpga_fme_hw *fme,\n+\t\tstruct opae_retimer_status *status)\n+{\n+\tstruct intel_max10_device *dev;\n+\tunsigned int val;\n+\n+\tdev = (struct intel_max10_device *)fme->max10_dev;\n+\tif (!dev)\n+\t\treturn -ENODEV;\n+\n+\tif (max10_reg_read(PKVL_LINK_STATUS, &val)) {\n+\t\tdev_err(dev, \"%s: read pkvl status fail\\n\", __func__);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\t/* The speed of PKVL is identical the eth group's speed */\n+\tstatus->speed = fme_get_eth_group_speed(fme,\n+\t\t\tLINE_SIDE_GROUP_ID);\n+\n+\tstatus->line_link_bitmap = val;\n+\n+\tdev_debug(dev, \"get retimer status: speed:%d. line_link_bitmap:0x%x\\n\",\n+\t\t\tstatus->speed,\n+\t\t\tstatus->line_link_bitmap);\n+\n+\treturn 0;\n+}\ndiff --git a/drivers/raw/ifpga_rawdev/base/ifpga_hw.h b/drivers/raw/ifpga_rawdev/base/ifpga_hw.h\nindex e296dd2..a428d69 100644\n--- a/drivers/raw/ifpga_rawdev/base/ifpga_hw.h\n+++ b/drivers/raw/ifpga_rawdev/base/ifpga_hw.h\n@@ -7,6 +7,7 @@\n \n #include \"ifpga_defines.h\"\n #include \"opae_ifpga_hw_api.h\"\n+#include \"opae_eth_group.h\"\n \n /** List of private feateues */\n TAILQ_HEAD(ifpga_feature_list, feature);\n@@ -82,6 +83,12 @@ struct ifpga_fme_hw {\n \n \tvoid *max10_dev; /* MAX10 device */\n \tvoid *i2c_master; /* I2C Master device */\n+\tvoid *eth_dev[MAX_ETH_GROUP_DEVICES];\n+\tstruct opae_reg_region\n+\t\teth_group_region[MAX_ETH_GROUP_DEVICES];\n+\tstruct ifpga_fme_board_info board_info;\n+\tint nums_eth_dev;\n+\tunsigned int nums_acc_region;\n };\n \n enum ifpga_port_state {\ndiff --git a/drivers/raw/ifpga_rawdev/base/meson.build b/drivers/raw/ifpga_rawdev/base/meson.build\nindex 7655985..f1015bb 100644\n--- a/drivers/raw/ifpga_rawdev/base/meson.build\n+++ b/drivers/raw/ifpga_rawdev/base/meson.build\n@@ -20,6 +20,7 @@ sources = [\n \t'opae_intel_max10.c',\n \t'opae_i2c.c',\n \t'opae_at24_eeprom.c',\n+\t'opae_eth_group.c',\n ]\n \n error_cflags = ['-Wno-sign-compare', '-Wno-unused-value',\ndiff --git a/drivers/raw/ifpga_rawdev/base/opae_eth_group.c b/drivers/raw/ifpga_rawdev/base/opae_eth_group.c\nnew file mode 100644\nindex 0000000..8db6693\n--- /dev/null\n+++ b/drivers/raw/ifpga_rawdev/base/opae_eth_group.c\n@@ -0,0 +1,145 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2010-2019 Intel Corporation\n+ */\n+\n+#include \"opae_osdep.h\"\n+#include \"opae_eth_group.h\"\n+\n+#define DATA_VAL_INVL\t\t1 /* us */\n+#define DATA_VAL_POLL_TIMEOUT\t10 /* us */\n+\n+static const char *eth_type_to_string(u8 type)\n+{\n+\tswitch (type) {\n+\tcase ETH_GROUP_PHY:\n+\t\treturn \"phy\";\n+\tcase ETH_GROUP_MAC:\n+\t\treturn \"mac\";\n+\tcase ETH_GROUP_ETHER:\n+\t\treturn \"ethernet wrapper\";\n+\t}\n+\n+\treturn \"unknown\";\n+}\n+\n+static int eth_group_get_select(struct eth_group_device *dev,\n+\t\tu8 type, u8 index, u8 *select)\n+{\n+\t/*\n+\t * in different speed configuration, the index of\n+\t * PHY and MAC are different.\n+\t *\n+\t * 1 ethernet wrapper -> Device Select 0x0 - fixed value\n+\t * n PHYs             -> Device Select 0x2,4,6,8,A,C,E,10,...\n+\t * n MACs             -> Device Select 0x3,5,7,9,B,D,F,11,...\n+\t */\n+\n+\tif (type == ETH_GROUP_PHY && index < dev->phy_num)\n+\t\t*select = index * 2 + 2;\n+\telse if (type == ETH_GROUP_MAC && index < dev->mac_num)\n+\t\t*select = index * 2 + 3;\n+\telse if (type == ETH_GROUP_ETHER && index == 0)\n+\t\t*select = 0;\n+\telse\n+\t\treturn -EINVAL;\n+\n+\treturn 0;\n+}\n+\n+int eth_group_write_reg(struct eth_group_device *dev,\n+\t\tu8 type, u8 index, u16 addr, u32 data)\n+{\n+\tu8 dev_select = 0;\n+\tu64 v = 0;\n+\tint ret;\n+\n+\tdev_debug(dev, \"%s type %s index %u addr 0x%x\\n\",\n+\t\t\t__func__, eth_type_to_string(type), index, addr);\n+\n+\t/* find device select */\n+\tret = eth_group_get_select(dev, type, index, &dev_select);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tv = CMD_WR << CTRL_CMD_SHIT |\n+\t\t(u64)dev_select << CTRL_DS_SHIFT |\n+\t\t(u64)addr << CTRL_ADDR_SHIFT |\n+\t\t(data & CTRL_WR_DATA);\n+\n+\t/* only PHY has additional feature bit */\n+\tif (type == ETH_GROUP_PHY)\n+\t\tv |= CTRL_FEAT_SELECT;\n+\n+\topae_writeq(v, dev->base + ETH_GROUP_CTRL);\n+\n+\treturn 0;\n+}\n+\n+int eth_group_read_reg(struct eth_group_device *dev,\n+\t\tu8 type, u8 index, u16 addr, u32 *data)\n+{\n+\tu8 dev_select = 0;\n+\tu64 v = 0;\n+\tint ret;\n+\n+\tdev_debug(dev, \"%s type %s index %u addr 0x%x\\n\",\n+\t\t\t__func__, eth_type_to_string(type), index,\n+\t\t\taddr);\n+\n+\t/* find device select */\n+\tret = eth_group_get_select(dev, type, index, &dev_select);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tv = CMD_RD << CTRL_CMD_SHIT |\n+\t\t(u64)dev_select << CTRL_DS_SHIFT |\n+\t\t(u64)addr << CTRL_ADDR_SHIFT;\n+\n+\t/* only PHY has additional feature bit */\n+\tif (type == ETH_GROUP_PHY)\n+\t\tv |= CTRL_FEAT_SELECT;\n+\n+\topae_writeq(v, dev->base + ETH_GROUP_CTRL);\n+\n+\tif (opae_readq_poll_timeout(dev->base + ETH_GROUP_STAT,\n+\t\t\tv, v & STAT_DATA_VAL, DATA_VAL_INVL,\n+\t\t\tDATA_VAL_POLL_TIMEOUT))\n+\t\treturn -ETIMEDOUT;\n+\n+\t*data = (v & STAT_RD_DATA);\n+\n+\tdev_debug(dev, \"%s data 0x%x\\n\", __func__, *data);\n+\n+\treturn 0;\n+}\n+\n+struct eth_group_device *eth_group_probe(void *base)\n+{\n+\tstruct eth_group_device *dev;\n+\n+\tdev = opae_malloc(sizeof(*dev));\n+\tif (!dev)\n+\t\treturn NULL;\n+\n+\tdev->base = (u8 *)base;\n+\n+\tdev->info.info = opae_readq(dev->base + ETH_GROUP_INFO);\n+\tdev->group_id = dev->info.group_id;\n+\tdev->phy_num = dev->mac_num = dev->info.num_phys;\n+\tdev->speed = dev->info.speed;\n+\n+\tdev->status = ETH_GROUP_DEV_ATTACHED;\n+\n+\tdev_info(dev, \"eth group device %d probe done: phy_num=mac_num:%d, speed=%d\\n\",\n+\t\t\tdev->group_id, dev->phy_num, dev->speed);\n+\n+\treturn dev;\n+}\n+\n+void eth_group_release(struct eth_group_device *dev)\n+{\n+\tif (dev) {\n+\t\tdev->status = ETH_GROUP_DEV_NOUSED;\n+\t\topae_free(dev);\n+\t}\n+}\ndiff --git a/drivers/raw/ifpga_rawdev/base/opae_eth_group.h b/drivers/raw/ifpga_rawdev/base/opae_eth_group.h\nnew file mode 100644\nindex 0000000..8d695cc\n--- /dev/null\n+++ b/drivers/raw/ifpga_rawdev/base/opae_eth_group.h\n@@ -0,0 +1,96 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2010-2019 Intel Corporation\n+ */\n+\n+#ifndef _OPAE_PHY_MAC_H\n+#define _OPAE_PHY_MAC_H\n+\n+#include \"opae_osdep.h\"\n+\n+#define MAX_ETH_GROUP_DEVICES 2\n+\n+#define LINE_SIDE_GROUP_ID 0\n+#define HOST_SIDE_GROUP_ID 1\n+\n+#define ETH_GROUP_SELECT_FEAT 1\n+\n+#define ETH_GROUP_PHY 1\n+#define ETH_GROUP_MAC 2\n+#define ETH_GROUP_ETHER 3\n+\n+#define ETH_GROUP_INFO\t\t0x8\n+#define INFO_SPEED\t\tGENMASK_ULL(23, 16)\n+#define ETH_SPEED_10G\t\t10\n+#define ETH_SPEED_25G\t\t25\n+#define INFO_PHY_NUM\t\tGENMASK_ULL(15, 8)\n+#define INFO_GROUP_NUM\t\tGENMASK_ULL(7, 0)\n+\n+#define ETH_GROUP_CTRL\t\t0x10\n+#define CTRL_CMD\t\tGENMASK_ULL(63, 62)\n+#define CTRL_CMD_SHIT           62\n+#define CMD_NOP\t\t\t0ULL\n+#define CMD_RD\t\t\t1ULL\n+#define CMD_WR\t\t\t2ULL\n+#define CTRL_DEV_SELECT\t\tGENMASK_ULL(52, 49)\n+#define CTRL_DS_SHIFT   49\n+#define CTRL_FEAT_SELECT\tBIT_ULL(48)\n+#define SELECT_IP\t\t0\n+#define SELECT_FEAT\t\t1\n+#define CTRL_ADDR\t\tGENMASK_ULL(47, 32)\n+#define CTRL_ADDR_SHIFT         32\n+#define CTRL_WR_DATA\t\tGENMASK_ULL(31, 0)\n+\n+#define ETH_GROUP_STAT\t\t0x18\n+#define STAT_DATA_VAL\t\tBIT_ULL(32)\n+#define STAT_RD_DATA\t\tGENMASK_ULL(31, 0)\n+\n+struct opae_eth_group_info {\n+\tu8 group_id;\n+\tu8 speed;\n+\tu8 nums_of_phy;\n+\tu8 nums_of_mac;\n+};\n+\n+struct opae_eth_group_region_info {\n+\tu8 group_id;\n+\tu64 phys_addr;\n+\tu64 len;\n+\tu8 *addr;\n+\tu8 mem_idx;\n+};\n+\n+struct eth_group_info_reg {\n+\tunion {\n+\t\tu64 info;\n+\t\tstruct {\n+\t\t\tu8 group_id:8;\n+\t\t\tu8 num_phys:8;\n+\t\t\tu8 speed:8;\n+\t\t\tu8 direction:1;\n+\t\t\tu64 resvd:39;\n+\t\t};\n+\t};\n+};\n+\n+enum eth_group_status {\n+\tETH_GROUP_DEV_NOUSED = 0,\n+\tETH_GROUP_DEV_ATTACHED,\n+};\n+\n+struct eth_group_device {\n+\tu8 *base;\n+\tstruct eth_group_info_reg info;\n+\tenum eth_group_status status;\n+\tu8 speed;\n+\tu8 group_id;\n+\tu8 phy_num;\n+\tu8 mac_num;\n+};\n+\n+struct eth_group_device *eth_group_probe(void *base);\n+void eth_group_release(struct eth_group_device *dev);\n+int eth_group_read_reg(struct eth_group_device *dev,\n+\t\tu8 type, u8 index, u16 addr, u32 *data);\n+int eth_group_write_reg(struct eth_group_device *dev,\n+\t\tu8 type, u8 index, u16 addr, u32 data);\n+#endif\ndiff --git a/drivers/raw/ifpga_rawdev/base/opae_hw_api.c b/drivers/raw/ifpga_rawdev/base/opae_hw_api.c\nindex ec2b4c7..0e117d0 100644\n--- a/drivers/raw/ifpga_rawdev/base/opae_hw_api.c\n+++ b/drivers/raw/ifpga_rawdev/base/opae_hw_api.c\n@@ -426,3 +426,152 @@ int opae_manager_write_mac_rom(struct opae_manager *mgr, int port,\n \n \treturn -ENOENT;\n }\n+\n+/**\n+ * opae_manager_get_eth_group_nums - get eth group numbers\n+ * @mgr: opae_manager for eth group\n+ *\n+ * Return: the numbers of eth group\n+ */\n+int opae_manager_get_eth_group_nums(struct opae_manager *mgr)\n+{\n+\tif (!mgr || !mgr->network_ops)\n+\t\treturn -EINVAL;\n+\n+\tif (mgr->network_ops->get_retimer_info)\n+\t\treturn mgr->network_ops->get_eth_group_nums(mgr);\n+\n+\treturn -ENOENT;\n+}\n+\n+/**\n+ * opae_manager_get_eth_group_info - get eth group info\n+ * @mgr: opae_manager for eth group\n+ * @group_id: id for eth group\n+ * @info: info return to caller\n+ *\n+ * Return: 0 on success, otherwise error code\n+ */\n+int opae_manager_get_eth_group_info(struct opae_manager *mgr,\n+\t       u8 group_id, struct opae_eth_group_info *info)\n+{\n+\tif (!mgr || !mgr->network_ops)\n+\t\treturn -EINVAL;\n+\n+\tif (mgr->network_ops->get_retimer_info)\n+\t\treturn mgr->network_ops->get_eth_group_info(mgr,\n+\t\t\tgroup_id, info);\n+\n+\treturn -ENOENT;\n+}\n+\n+/**\n+ * opae_manager_get_eth_group_region_info\n+ * @mgr: opae_manager for flash.\n+ * @info: the memory region info for eth group\n+ *\n+ * Return: 0 on success, otherwise error code.\n+ */\n+int opae_manager_get_eth_group_region_info(struct opae_manager *mgr,\n+\t\tu8 group_id, struct opae_eth_group_region_info *info)\n+{\n+\tif (!mgr)\n+\t\treturn -EINVAL;\n+\n+\tif (group_id >= MAX_ETH_GROUP_DEVICES)\n+\t\treturn -EINVAL;\n+\n+\tinfo->group_id = group_id;\n+\n+\tif (mgr && mgr->ops && mgr->ops->get_eth_group_region_info)\n+\t\treturn mgr->ops->get_eth_group_region_info(mgr, info);\n+\n+\treturn -ENOENT;\n+}\n+\n+/**\n+ * opae_manager_eth_group_read_reg - read ETH group register\n+ * @mgr: opae_manager for ETH Group\n+ * @group_id: ETH group id\n+ * @type: eth type\n+ * @index: port index in eth group device\n+ * @addr: register address of ETH Group\n+ * @data: read buffer\n+ *\n+ * Return: 0 on success, otherwise error code\n+ */\n+int opae_manager_eth_group_read_reg(struct opae_manager *mgr, u8 group_id,\n+\t\tu8 type, u8 index, u16 addr, u32 *data)\n+{\n+\tif (!mgr || !mgr->network_ops)\n+\t\treturn -EINVAL;\n+\n+\tif (mgr->network_ops->eth_group_reg_read)\n+\t\treturn mgr->network_ops->eth_group_reg_read(mgr, group_id,\n+\t\t\t\ttype, index, addr, data);\n+\n+\treturn -ENOENT;\n+}\n+\n+/**\n+ * opae_manager_eth_group_write_reg - write ETH group register\n+ * @mgr: opae_manager for ETH Group\n+ * @group_id: ETH group id\n+ * @type: eth type\n+ * @index: port index in eth group device\n+ * @addr: register address of ETH Group\n+ * @data: data will write to register\n+ *\n+ * Return: 0 on success, otherwise error code\n+ */\n+int opae_manager_eth_group_write_reg(struct opae_manager *mgr, u8 group_id,\n+\t\tu8 type, u8 index, u16 addr, u32 data)\n+{\n+\tif (!mgr || !mgr->network_ops)\n+\t\treturn -EINVAL;\n+\n+\tif (mgr->network_ops->eth_group_reg_write)\n+\t\treturn mgr->network_ops->eth_group_reg_write(mgr, group_id,\n+\t\t\t\ttype, index, addr, data);\n+\n+\treturn -ENOENT;\n+}\n+\n+/**\n+ * opae_manager_get_retimer_info - get retimer info like PKVL chip\n+ * @mgr: opae_manager for retimer\n+ * @info: info return to caller\n+ *\n+ * Return: 0 on success, otherwise error code\n+ */\n+int opae_manager_get_retimer_info(struct opae_manager *mgr,\n+\t       struct opae_retimer_info *info)\n+{\n+\tif (!mgr || !mgr->network_ops)\n+\t\treturn -EINVAL;\n+\n+\tif (mgr->network_ops->get_retimer_info)\n+\t\treturn mgr->network_ops->get_retimer_info(mgr, info);\n+\n+\treturn -ENOENT;\n+}\n+\n+/**\n+ * opae_manager_get_retimer_status - get retimer status\n+ * @mgr: opae_manager of retimer\n+ * @status: status of retimer\n+ *\n+ * Return: 0 on success, otherwise error code\n+ */\n+int opae_manager_get_retimer_status(struct opae_manager *mgr,\n+\t\tstruct opae_retimer_status *status)\n+{\n+\tif (!mgr || !mgr->network_ops)\n+\t\treturn -EINVAL;\n+\n+\tif (mgr->network_ops->get_retimer_status)\n+\t\treturn mgr->network_ops->get_retimer_status(mgr,\n+\t\t\t\tstatus);\n+\n+\treturn -ENOENT;\n+}\ndiff --git a/drivers/raw/ifpga_rawdev/base/opae_hw_api.h b/drivers/raw/ifpga_rawdev/base/opae_hw_api.h\nindex 826da37..383e751 100644\n--- a/drivers/raw/ifpga_rawdev/base/opae_hw_api.h\n+++ b/drivers/raw/ifpga_rawdev/base/opae_hw_api.h\n@@ -12,6 +12,7 @@\n \n #include \"opae_osdep.h\"\n #include \"opae_intel_max10.h\"\n+#include \"opae_eth_group.h\"\n \n #ifndef PCI_MAX_RESOURCE\n #define PCI_MAX_RESOURCE 6\n@@ -45,6 +46,8 @@ struct opae_manager {\n struct opae_manager_ops {\n \tint (*flash)(struct opae_manager *mgr, int id, void *buffer,\n \t\t     u32 size, u64 *status);\n+\tint (*get_eth_group_region_info)(struct opae_manager *mgr,\n+\t\t\tstruct opae_eth_group_region_info *info);\n };\n \n /* networking management ops in FME */\n@@ -53,6 +56,17 @@ struct opae_manager_networking_ops {\n \t\t\tint size);\n \tint (*write_mac_rom)(struct opae_manager *mgr, int offset, void *buf,\n \t\t\tint size);\n+\tint (*get_eth_group_nums)(struct opae_manager *mgr);\n+\tint (*get_eth_group_info)(struct opae_manager *mgr,\n+\t\t\tu8 group_id, struct opae_eth_group_info *info);\n+\tint (*eth_group_reg_read)(struct opae_manager *mgr, u8 group_id,\n+\t\t\tu8 type, u8 index, u16 addr, u32 *data);\n+\tint (*eth_group_reg_write)(struct opae_manager *mgr, u8 group_id,\n+\t\t\tu8 type, u8 index, u16 addr, u32 data);\n+\tint (*get_retimer_info)(struct opae_manager *mgr,\n+\t\t\tstruct opae_retimer_info *info);\n+\tint (*get_retimer_status)(struct opae_manager *mgr,\n+\t\t\tstruct opae_retimer_status *status);\n };\n \n /* OPAE Manager APIs */\n@@ -62,6 +76,8 @@ struct opae_manager *\n #define opae_manager_free(mgr) opae_free(mgr)\n int opae_manager_flash(struct opae_manager *mgr, int acc_id, void *buf,\n \t\t       u32 size, u64 *status);\n+int opae_manager_get_eth_group_region_info(struct opae_manager *mgr,\n+\t\tu8 group_id, struct opae_eth_group_region_info *info);\n \n /* OPAE Bridge Data Structure */\n struct opae_bridge_ops;\n@@ -276,4 +292,15 @@ int opae_manager_read_mac_rom(struct opae_manager *mgr, int port,\n \t\tstruct opae_ether_addr *addr);\n int opae_manager_write_mac_rom(struct opae_manager *mgr, int port,\n \t\tstruct opae_ether_addr *addr);\n+int opae_manager_get_retimer_info(struct opae_manager *mgr,\n+\t\tstruct opae_retimer_info *info);\n+int opae_manager_get_retimer_status(struct opae_manager *mgr,\n+\t\tstruct opae_retimer_status *status);\n+int opae_manager_get_eth_group_nums(struct opae_manager *mgr);\n+int opae_manager_get_eth_group_info(struct opae_manager *mgr,\n+\t\tu8 group_id, struct opae_eth_group_info *info);\n+int opae_manager_eth_group_write_reg(struct opae_manager *mgr, u8 group_id,\n+\t\tu8 type, u8 index, u16 addr, u32 data);\n+int opae_manager_eth_group_read_reg(struct opae_manager *mgr, u8 group_id,\n+\t\tu8 type, u8 index, u16 addr, u32 *data);\n #endif /* _OPAE_HW_API_H_*/\ndiff --git a/drivers/raw/ifpga_rawdev/base/opae_intel_max10.h b/drivers/raw/ifpga_rawdev/base/opae_intel_max10.h\nindex 91a188d..08b387e 100644\n--- a/drivers/raw/ifpga_rawdev/base/opae_intel_max10.h\n+++ b/drivers/raw/ifpga_rawdev/base/opae_intel_max10.h\n@@ -8,9 +8,6 @@\n #include \"opae_osdep.h\"\n #include \"opae_spi.h\"\n \n-#define INTEL_MAX10_MAX_MDIO_DEVS 2\n-#define PKVL_NUMBER_PORTS  4\n-\n /* max10 capability flags */\n #define MAX10_FLAGS_NO_I2C2\t\tBIT(0)\n #define MAX10_FLAGS_NO_BMCIMG_FLASH\tBIT(1)\n@@ -25,6 +22,45 @@ struct intel_max10_device {\n \tstruct spi_transaction_dev *spi_tran_dev;\n };\n \n+/* retimer speed */\n+enum retimer_speed {\n+\tMXD_1GB = 1,\n+\tMXD_2_5GB = 2,\n+\tMXD_5GB = 5,\n+\tMXD_10GB = 10,\n+\tMXD_25GB = 25,\n+\tMXD_40GB = 40,\n+\tMXD_100GB = 100,\n+\tMXD_SPEED_UNKNOWN,\n+};\n+\n+/* retimer info */\n+struct opae_retimer_info {\n+\tunsigned int nums_retimer;\n+\tunsigned int ports_per_retimer;\n+\tunsigned int nums_fvl;\n+\tunsigned int ports_per_fvl;\n+\tenum retimer_speed support_speed;\n+};\n+\n+/* retimer status*/\n+struct opae_retimer_status {\n+\tenum retimer_speed speed;\n+\t/*\n+\t * retimer line link status bitmap:\n+\t * bit 0: Retimer0 Port0 link status\n+\t * bit 1: Retimer0 Port1 link status\n+\t * bit 2: Retimer0 Port2 link status\n+\t * bit 3: Retimer0 Port3 link status\n+\t *\n+\t * bit 4: Retimer1 Port0 link status\n+\t * bit 5: Retimer1 Port1 link status\n+\t * bit 6: Retimer1 Port2 link status\n+\t * bit 7: Retimer1 Port3 link status\n+\t */\n+\tunsigned int line_link_bitmap;\n+};\n+\n #define FLASH_BASE 0x10000000\n #define FLASH_OPTION_BITS 0x10000\n \ndiff --git a/drivers/raw/ifpga_rawdev/base/opae_osdep.h b/drivers/raw/ifpga_rawdev/base/opae_osdep.h\nindex d710ec0..1596adc 100644\n--- a/drivers/raw/ifpga_rawdev/base/opae_osdep.h\n+++ b/drivers/raw/ifpga_rawdev/base/opae_osdep.h\n@@ -53,12 +53,7 @@ struct uuid {\n #define dev_err(x, args...) dev_printf(ERR, args)\n #define dev_info(x, args...) dev_printf(INFO, args)\n #define dev_warn(x, args...) dev_printf(WARNING, args)\n-\n-#ifdef OPAE_DEBUG\n #define dev_debug(x, args...) dev_printf(DEBUG, args)\n-#else\n-#define dev_debug(x, args...) do { } while (0)\n-#endif\n \n #define pr_err(y, args...) dev_err(0, y, ##args)\n #define pr_warn(y, args...) dev_warn(0, y, ##args)\n@@ -81,4 +76,15 @@ struct uuid {\n #define time_before(a, b)\ttime_after(b, a)\n #define opae_memset(a, b, c)    memset((a), (b), (c))\n \n+#define opae_readq_poll_timeout(addr, val, cond, invl, timeout)\\\n+({\t\t\t\t\t\t\t\t\t     \\\n+\tint wait = 0;\t\t\t\t\t\t\t     \\\n+\tfor (; wait <= timeout; wait += invl) {\t\t\t     \\\n+\t\t(val) = opae_readq(addr);\t\t\t\t     \\\n+\t\tif (cond)                  \\\n+\t\t\tbreak;\t\t\t\t\t\t     \\\n+\t\tudelay(invl);\t\t\t\t\t\t     \\\n+\t}\t\t\t\t\t\t\t\t     \\\n+\t(cond) ? 0 : -ETIMEDOUT;\t  \\\n+})\n #endif\n",
    "prefixes": [
        "v7",
        "11/14"
    ]
}