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GET /api/patches/52498/?format=api
{ "id": 52498, "url": "http://patches.dpdk.org/api/patches/52498/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20190409190630.31975-4-vivkong@ca.ibm.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20190409190630.31975-4-vivkong@ca.ibm.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20190409190630.31975-4-vivkong@ca.ibm.com", "date": "2019-04-09T19:06:21", "name": "[RFC,03/12] acl: add support for s390x architecture", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": true, "hash": "ef5b93af1662a37ba609cf0c0e828690a2d4b963", "submitter": { "id": 1273, "url": "http://patches.dpdk.org/api/people/1273/?format=api", "name": "Vivian Kong", "email": "vivkong@gmail.com" }, "delegate": { "id": 1, "url": "http://patches.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20190409190630.31975-4-vivkong@ca.ibm.com/mbox/", "series": [ { "id": 4211, "url": "http://patches.dpdk.org/api/series/4211/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=4211", "date": "2019-04-09T19:06:18", "name": "introduce s390x architecture", "version": 1, "mbox": "http://patches.dpdk.org/series/4211/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/52498/comments/", "check": "warning", "checks": "http://patches.dpdk.org/api/patches/52498/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 4E48858CB;\n\tTue, 9 Apr 2019 21:06:46 +0200 (CEST)", "from mail-qt1-f194.google.com (mail-qt1-f194.google.com\n\t[209.85.160.194]) by dpdk.org (Postfix) with ESMTP id 896B154AE\n\tfor <dev@dpdk.org>; Tue, 9 Apr 2019 21:06:37 +0200 (CEST)", "by mail-qt1-f194.google.com with SMTP id x12so21153707qts.7\n\tfor <dev@dpdk.org>; Tue, 09 Apr 2019 12:06:37 -0700 (PDT)", "from csz25116.canlab.ibm.com ([199.246.40.57])\n\tby smtp.gmail.com with ESMTPSA id\n\tq23sm17934789qkc.16.2019.04.09.12.06.35 for <dev@dpdk.org>\n\t(version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128);\n\tTue, 09 Apr 2019 12:06:35 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025;\n\th=from:to:subject:date:message-id:in-reply-to:references:reply-to;\n\tbh=nbi8ciZYHZiEavNR0hFcg7X/0A/LAumdrTKr6hSQXNc=;\n\tb=UalmOM7yPaxfxS7KEblIbqPKmWWP76Q5hVd2cXUYYiCP1JmxUpGzGEhyAHuNjnNUmD\n\tt5W3GSfc0KTK5hNiLhc8Nips/Q+yCtKGcSe7+e99rlw/liTN7D4yvDCPD9iz6XX01YmT\n\tLrXWLhhFAODJT3wR8KCZc8Y0Nfddf6ecZqB60KFvVPFJ5Isuy8QUEYudEvHVXeaj9Mg+\n\tMXugLpAmJDYZYGmUT41hR56S1GgSGWa0CbH+hJcE+sR5EPQgpJ2dz7iyn5fDauiGYtJh\n\tVruK4R8djqd0XprcNcUB6d4M2Auvd9DIiWCb4hHuydrloZtFTX/ZLkDLBtsMKrAEy5xr\n\t5uTA==", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:from:to:subject:date:message-id:in-reply-to\n\t:references:reply-to;\n\tbh=nbi8ciZYHZiEavNR0hFcg7X/0A/LAumdrTKr6hSQXNc=;\n\tb=F0DV10y9QAVWtMESEIkxrz+pqRV3k8BVr+DIPOXGsH/uFnMLudRQRuy6+DX3KbAfdJ\n\tJPf4H0bJEsKvRgLrzJZ01jPjFYW+Pk0wGoty1pmqFo1uQVN/exJbdxOpoT31tw2IUyVP\n\tO3lA+ECI0cWCcX5eAA3g3iiYbbUv9XyvISMo97diXy0UcgZWCwQo5O0haVMPyDnjcpxx\n\tNJtRxPNTVRjPVAgAdMVudhOFujBvJI7O6M653BxPH1DoKo5yti5FnkOj4CCA6xRaveA4\n\tgYptOrHpFRBRdJHdkCzlUyp9sSmmj9mkHKIm/Wfax1CaawxS4zbPFcO7MHQwTDCa1mVj\n\tAr7A==", "X-Gm-Message-State": "APjAAAWNNNoq2XJAXuFGnAxJdZ4upYaoWMCMoTNBC5hgSRgLAR76MOqV\n\tpQSBpuVG/jospGVB7bSYmqvt94hbspI=", "X-Google-Smtp-Source": "APXvYqz4VugK7Re35n0MlYtcHzk3gkcMtltfTk8j9rFfRkZwPNh6i29xlQ7Eqk0+EEMdz9gOXdf68w==", "X-Received": "by 2002:ac8:2c72:: with SMTP id\n\te47mr31711658qta.189.1554836796500; \n\tTue, 09 Apr 2019 12:06:36 -0700 (PDT)", "From": "Vivian Kong <vivkong@gmail.com>", "X-Google-Original-From": "Vivian Kong <vivkong@ca.ibm.com>", "To": "dev@dpdk.org", "Date": "Tue, 9 Apr 2019 15:06:21 -0400", "Message-Id": "<20190409190630.31975-4-vivkong@ca.ibm.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20190409190630.31975-1-vivkong@ca.ibm.com>", "References": "<20190409190630.31975-1-vivkong@ca.ibm.com>", "Subject": "[dpdk-dev] [RFC 03/12] acl: add support for s390x architecture", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "Reply-To": "vivkong@ca.ibm.com", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Add big endian support for s390x architecture.\n\nSigned-off-by: Vivian Kong <vivkong@ca.ibm.com>\n---\n app/test-acl/main.c | 4 ++\n lib/librte_acl/Makefile | 2 +\n lib/librte_acl/acl_bld.c | 69 +++++++++++++++++++++++++++------\n lib/librte_acl/acl_gen.c | 9 +++++\n lib/librte_acl/acl_run_scalar.c | 8 ++++\n lib/librte_acl/rte_acl.c | 4 ++\n lib/librte_acl/rte_acl.h | 1 +\n 7 files changed, 85 insertions(+), 12 deletions(-)", "diff": "diff --git a/app/test-acl/main.c b/app/test-acl/main.c\nindex b80179417..b6c5c9abd 100644\n--- a/app/test-acl/main.c\n+++ b/app/test-acl/main.c\n@@ -81,6 +81,10 @@ static const struct acl_alg acl_alg[] = {\n \t\t.name = \"altivec\",\n \t\t.alg = RTE_ACL_CLASSIFY_ALTIVEC,\n \t},\n+\t{\n+\t\t.name = \"s390x\",\n+\t\t.alg = RTE_ACL_CLASSIFY_S390X,\n+\t},\n };\n \n static struct {\ndiff --git a/lib/librte_acl/Makefile b/lib/librte_acl/Makefile\nindex ea5edf00a..f87693d1e 100644\n--- a/lib/librte_acl/Makefile\n+++ b/lib/librte_acl/Makefile\n@@ -30,6 +30,8 @@ CFLAGS_acl_run_neon.o += -Wno-maybe-uninitialized\n endif\n else ifeq ($(CONFIG_RTE_ARCH_PPC_64),y)\n SRCS-$(CONFIG_RTE_LIBRTE_ACL) += acl_run_altivec.c\n+else ifeq ($(CONFIG_RTE_ARCH_S390X),y)\n+SRCS-$(CONFIG_RTE_LIBRTE_ACL) +=\n else\n SRCS-$(CONFIG_RTE_LIBRTE_ACL) += acl_run_sse.c\n endif\ndiff --git a/lib/librte_acl/acl_bld.c b/lib/librte_acl/acl_bld.c\nindex b82191f42..16bf09304 100644\n--- a/lib/librte_acl/acl_bld.c\n+++ b/lib/librte_acl/acl_bld.c\n@@ -777,6 +777,16 @@ acl_build_reset(struct rte_acl_ctx *ctx)\n \t\tsizeof(*ctx) - offsetof(struct rte_acl_ctx, num_categories));\n }\n \n+static uint32_t get_le_byte_index(uint32_t index, int size)\n+{\n+#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__\n+\t(void) size;\n+\treturn index;\n+#else\n+\treturn size - 1 - index;\n+#endif\n+}\n+\n static void\n acl_gen_range(struct acl_build_context *context,\n \tconst uint8_t *hi, const uint8_t *lo, int size, int level,\n@@ -786,12 +796,19 @@ acl_gen_range(struct acl_build_context *context,\n \tuint32_t n;\n \n \tprev = root;\n+\n+\t/* On big endian min and max point to highest byte.\n+\t * Therefore iterate in opposite direction as on\n+\t * little endian with helper function.\n+\t */\n \tfor (n = size - 1; n > 0; n--) {\n+\t\tuint32_t le_idx = get_le_byte_index(n, size);\n \t\tnode = acl_alloc_node(context, level++);\n-\t\tacl_add_ptr_range(context, prev, node, lo[n], hi[n]);\n+\t\tacl_add_ptr_range(context, prev, node, lo[le_idx], hi[le_idx]);\n \t\tprev = node;\n \t}\n-\tacl_add_ptr_range(context, prev, end, lo[0], hi[0]);\n+\tconst uint32_t first_idx = get_le_byte_index(0, size);\n+\tacl_add_ptr_range(context, prev, end, lo[first_idx], hi[first_idx]);\n }\n \n static struct rte_acl_node *\n@@ -804,10 +821,16 @@ acl_gen_range_trie(struct acl_build_context *context,\n \tconst uint8_t *lo = min;\n \tconst uint8_t *hi = max;\n \n+\t/* On big endian min and max point to highest byte.\n+\t * Therefore iterate in opposite direction as on\n+\t * little endian.\n+\t */\n+\tconst int byte_index = get_le_byte_index(size-1, size);\n+\n \t*pend = acl_alloc_node(context, level+size);\n \troot = acl_alloc_node(context, level++);\n \n-\tif (lo[size - 1] == hi[size - 1]) {\n+\tif (lo[byte_index] == hi[byte_index]) {\n \t\tacl_gen_range(context, hi, lo, size, level, root, *pend);\n \t} else {\n \t\tuint8_t limit_lo[64];\n@@ -819,27 +842,29 @@ acl_gen_range_trie(struct acl_build_context *context,\n \t\tmemset(limit_hi, UINT8_MAX, RTE_DIM(limit_hi));\n \n \t\tfor (n = size - 2; n >= 0; n--) {\n-\t\t\thi_ff = (uint8_t)(hi_ff & hi[n]);\n-\t\t\tlo_00 = (uint8_t)(lo_00 | lo[n]);\n+\t\t\tconst uint32_t le_idx = get_le_byte_index(n, size);\n+\t\t\thi_ff = (uint8_t)(hi_ff & hi[le_idx]);\n+\t\t\tlo_00 = (uint8_t)(lo_00 | lo[le_idx]);\n \t\t}\n \n \t\tif (hi_ff != UINT8_MAX) {\n-\t\t\tlimit_lo[size - 1] = hi[size - 1];\n+\t\t\tlimit_lo[byte_index] = hi[byte_index];\n \t\t\tacl_gen_range(context, hi, limit_lo, size, level,\n \t\t\t\troot, *pend);\n \t\t}\n \n \t\tif (lo_00 != 0) {\n-\t\t\tlimit_hi[size - 1] = lo[size - 1];\n+\t\t\tlimit_hi[byte_index] = lo[byte_index];\n \t\t\tacl_gen_range(context, limit_hi, lo, size, level,\n \t\t\t\troot, *pend);\n \t\t}\n \n-\t\tif (hi[size - 1] - lo[size - 1] > 1 ||\n+\t\tif (hi[byte_index] - lo[byte_index] > 1 ||\n \t\t\t\tlo_00 == 0 ||\n \t\t\t\thi_ff == UINT8_MAX) {\n-\t\t\tlimit_lo[size-1] = (uint8_t)(lo[size-1] + (lo_00 != 0));\n-\t\t\tlimit_hi[size-1] = (uint8_t)(hi[size-1] -\n+\t\t\tlimit_lo[byte_index] = (uint8_t)(lo[byte_index] +\n+\t\t\t\t(lo_00 != 0));\n+\t\t\tlimit_hi[byte_index] = (uint8_t)(hi[byte_index] -\n \t\t\t\t(hi_ff != UINT8_MAX));\n \t\t\tacl_gen_range(context, limit_hi, limit_lo, size,\n \t\t\t\tlevel, root, *pend);\n@@ -863,13 +888,17 @@ acl_gen_mask_trie(struct acl_build_context *context,\n \troot = acl_alloc_node(context, level++);\n \tprev = root;\n \n+\t/* On big endian val and msk point to highest byte.\n+\t * Therefore iterate in opposite direction as on\n+\t * little endian with helper function\n+\t */\n \tfor (n = size - 1; n >= 0; n--) {\n+\t\tuint32_t le_idx = get_le_byte_index(n, size);\n \t\tnode = acl_alloc_node(context, level++);\n-\t\tacl_gen_mask(&bits, val[n] & msk[n], msk[n]);\n+\t\tacl_gen_mask(&bits, val[le_idx] & msk[le_idx], msk[le_idx]);\n \t\tacl_add_ptr(context, prev, node, &bits);\n \t\tprev = node;\n \t}\n-\n \t*pend = prev;\n \treturn root;\n }\n@@ -927,6 +956,14 @@ build_trie(struct acl_build_context *context, struct rte_acl_build_rule *head,\n \t\t\t\t\tfld->mask_range.u32,\n \t\t\t\t\trule->config->defs[n].size);\n \n+\t\t\t\t/* Fields are aligned highest to lowest bit.\n+\t\t\t\t * Masked needs to be shifted to follow same\n+\t\t\t\t * convention\n+\t\t\t\t */\n+#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__\n+\t\t\t\tmask = mask << 32;\n+#endif\n+\n \t\t\t\t/* gen a mini-trie for this field */\n \t\t\t\tmerge = acl_gen_mask_trie(context,\n \t\t\t\t\t&fld->value,\n@@ -1017,6 +1054,14 @@ acl_calc_wildness(struct rte_acl_build_rule *head,\n \t\t\tuint32_t bit_len = CHAR_BIT * config->defs[n].size;\n \t\t\tuint64_t msk_val = RTE_LEN2MASK(bit_len,\n \t\t\t\ttypeof(msk_val));\n+\n+\t\t\t/* Fields are aligned highest to lowest bit.\n+\t\t\t * Masked needs to be shifted to follow same\n+\t\t\t * convention\n+\t\t\t */\n+\t\t\tif (__BYTE_ORDER__ == __ORDER_BIG_ENDIAN__)\n+\t\t\t\tmsk_val <<= 32;\n+\n \t\t\tdouble size = bit_len;\n \t\t\tint field_index = config->defs[n].field_index;\n \t\t\tconst struct rte_acl_field *fld = rule->f->field +\ndiff --git a/lib/librte_acl/acl_gen.c b/lib/librte_acl/acl_gen.c\nindex 35a0140b4..b4e8df0ce 100644\n--- a/lib/librte_acl/acl_gen.c\n+++ b/lib/librte_acl/acl_gen.c\n@@ -360,7 +360,16 @@ acl_gen_node(struct rte_acl_node *node, uint64_t *node_array,\n \t\tarray_ptr = &node_array[index->quad_index];\n \t\tacl_add_ptrs(node, array_ptr, no_match, 0);\n \t\tqtrp = (uint32_t *)node->transitions;\n+\n+\t\t/* Swap qtrp on big endian that transitions[0]\n+\t\t * is at least signifcant byte.\n+\t\t */\n+#if __BYTE_ORDER == __ORDER_BIG_ENDIAN__\n+\t\tnode->node_index = __bswap_32(qtrp[0]);\n+#else\n \t\tnode->node_index = qtrp[0];\n+#endif\n+\n \t\tnode->node_index <<= sizeof(index->quad_index) * CHAR_BIT;\n \t\tnode->node_index |= index->quad_index | node->node_type;\n \t\tindex->quad_index += node->fanout;\ndiff --git a/lib/librte_acl/acl_run_scalar.c b/lib/librte_acl/acl_run_scalar.c\nindex 3d61e7940..9f01ef8d8 100644\n--- a/lib/librte_acl/acl_run_scalar.c\n+++ b/lib/librte_acl/acl_run_scalar.c\n@@ -141,6 +141,14 @@ rte_acl_classify_scalar(const struct rte_acl_ctx *ctx, const uint8_t **data,\n \t\tinput0 = GET_NEXT_4BYTES(parms, 0);\n \t\tinput1 = GET_NEXT_4BYTES(parms, 1);\n \n+\t\t/* input needs to be swapped because the rules get\n+\t\t * swapped while building the trie.\n+\t\t */\n+#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__\n+\t\tinput0 = __bswap_32(input0);\n+\t\tinput1 = __bswap_32(input1);\n+#endif\n+\n \t\tfor (n = 0; n < 4; n++) {\n \n \t\t\ttransition0 = scalar_transition(flows.trans,\ndiff --git a/lib/librte_acl/rte_acl.c b/lib/librte_acl/rte_acl.c\nindex c436a9bfd..6d4d3f239 100644\n--- a/lib/librte_acl/rte_acl.c\n+++ b/lib/librte_acl/rte_acl.c\n@@ -64,6 +64,8 @@ static const rte_acl_classify_t classify_fns[] = {\n \t[RTE_ACL_CLASSIFY_AVX2] = rte_acl_classify_avx2,\n \t[RTE_ACL_CLASSIFY_NEON] = rte_acl_classify_neon,\n \t[RTE_ACL_CLASSIFY_ALTIVEC] = rte_acl_classify_altivec,\n+\t/* use scalar for s390x for now */\n+\t[RTE_ACL_CLASSIFY_S390X] = rte_acl_classify_scalar,\n };\n \n /* by default, use always available scalar code path. */\n@@ -103,6 +105,8 @@ RTE_INIT(rte_acl_init)\n \t\talg = RTE_ACL_CLASSIFY_NEON;\n #elif defined(RTE_ARCH_PPC_64)\n \talg = RTE_ACL_CLASSIFY_ALTIVEC;\n+#elif defined(RTE_ARCH_S390X)\n+\talg = RTE_ACL_CLASSIFY_S390X;\n #else\n #ifdef CC_AVX2_SUPPORT\n \tif (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2))\ndiff --git a/lib/librte_acl/rte_acl.h b/lib/librte_acl/rte_acl.h\nindex aa22e70c6..9537196db 100644\n--- a/lib/librte_acl/rte_acl.h\n+++ b/lib/librte_acl/rte_acl.h\n@@ -241,6 +241,7 @@ enum rte_acl_classify_alg {\n \tRTE_ACL_CLASSIFY_AVX2 = 3, /**< requires AVX2 support. */\n \tRTE_ACL_CLASSIFY_NEON = 4, /**< requires NEON support. */\n \tRTE_ACL_CLASSIFY_ALTIVEC = 5, /**< requires ALTIVEC support. */\n+\tRTE_ACL_CLASSIFY_S390X = 6, /**< requires s390x z13 support. */\n \tRTE_ACL_CLASSIFY_NUM /* should always be the last one. */\n };\n \n", "prefixes": [ "RFC", "03/12" ] }