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GET /api/patches/52232/?format=api
{ "id": 52232, "url": "http://patches.dpdk.org/api/patches/52232/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20190403200916.16349-7-gage.eads@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20190403200916.16349-7-gage.eads@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20190403200916.16349-7-gage.eads@intel.com", "date": "2019-04-03T20:09:14", "name": "[v7,6/8] stack: add C11 atomic implementation", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "d1df436ec248ecc47d3f716c047e7fb41c6c0080", "submitter": { "id": 586, "url": "http://patches.dpdk.org/api/people/586/?format=api", "name": "Eads, Gage", "email": "gage.eads@intel.com" }, "delegate": null, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20190403200916.16349-7-gage.eads@intel.com/mbox/", "series": [ { "id": 4101, "url": "http://patches.dpdk.org/api/series/4101/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=4101", "date": "2019-04-03T20:09:08", "name": "Add stack library and new mempool handler", "version": 7, "mbox": "http://patches.dpdk.org/series/4101/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/52232/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/52232/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 77FB61B44D;\n\tWed, 3 Apr 2019 22:10:26 +0200 (CEST)", "from mga01.intel.com (mga01.intel.com [192.55.52.88])\n\tby dpdk.org (Postfix) with ESMTP id 21D131B150\n\tfor <dev@dpdk.org>; Wed, 3 Apr 2019 22:10:04 +0200 (CEST)", "from orsmga007.jf.intel.com ([10.7.209.58])\n\tby fmsmga101.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t03 Apr 2019 13:10:04 -0700", "from txasoft-yocto.an.intel.com ([10.123.72.192])\n\tby orsmga007.jf.intel.com with ESMTP; 03 Apr 2019 13:10:03 -0700" ], "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.60,306,1549958400\"; d=\"scan'208\";a=\"128403737\"", "From": "Gage Eads <gage.eads@intel.com>", "To": "dev@dpdk.org", "Cc": "olivier.matz@6wind.com, arybchenko@solarflare.com,\n\tbruce.richardson@intel.com, konstantin.ananyev@intel.com,\n\tgavin.hu@arm.com, \n\tHonnappa.Nagarahalli@arm.com, nd@arm.com, thomas@monjalon.net", "Date": "Wed, 3 Apr 2019 15:09:14 -0500", "Message-Id": "<20190403200916.16349-7-gage.eads@intel.com>", "X-Mailer": "git-send-email 2.13.6", "In-Reply-To": "<20190403200916.16349-1-gage.eads@intel.com>", "References": "<20190401211429.20282-1-gage.eads@intel.com>\n\t<20190403200916.16349-1-gage.eads@intel.com>", "Subject": "[dpdk-dev] [PATCH v7 6/8] stack: add C11 atomic implementation", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "This commit adds an implementation of the lock-free stack push, pop, and\nlength functions that use __atomic builtins, for systems that benefit from\nthe finer-grained memory ordering control.\n\nSigned-off-by: Gage Eads <gage.eads@intel.com>\nReviewed-by: Olivier Matz <olivier.matz@6wind.com>\nReviewed-by: Honnappa Nagarahalli <honnappa.nagarahalli@arm.com>\n---\n lib/librte_stack/Makefile | 3 +-\n lib/librte_stack/meson.build | 3 +-\n lib/librte_stack/rte_stack_lf.h | 4 +\n lib/librte_stack/rte_stack_lf_c11.h | 175 ++++++++++++++++++++++++++++++++++++\n 4 files changed, 183 insertions(+), 2 deletions(-)\n create mode 100644 lib/librte_stack/rte_stack_lf_c11.h", "diff": "diff --git a/lib/librte_stack/Makefile b/lib/librte_stack/Makefile\nindex 311edd997..8d18ce520 100644\n--- a/lib/librte_stack/Makefile\n+++ b/lib/librte_stack/Makefile\n@@ -23,6 +23,7 @@ SRCS-$(CONFIG_RTE_LIBRTE_STACK) := rte_stack.c \\\n SYMLINK-$(CONFIG_RTE_LIBRTE_STACK)-include := rte_stack.h \\\n \t\t\t\t\t rte_stack_std.h \\\n \t\t\t\t\t rte_stack_lf.h \\\n-\t\t\t\t\t rte_stack_lf_generic.h\n+\t\t\t\t\t rte_stack_lf_generic.h \\\n+\t\t\t\t\t rte_stack_lf_c11.h\n \n include $(RTE_SDK)/mk/rte.lib.mk\ndiff --git a/lib/librte_stack/meson.build b/lib/librte_stack/meson.build\nindex 7a09a5d66..46fce0c20 100644\n--- a/lib/librte_stack/meson.build\n+++ b/lib/librte_stack/meson.build\n@@ -8,4 +8,5 @@ sources = files('rte_stack.c', 'rte_stack_std.c', 'rte_stack_lf.c')\n headers = files('rte_stack.h',\n \t\t'rte_stack_std.h',\n \t\t'rte_stack_lf.h',\n-\t\t'rte_stack_lf_generic.h')\n+\t\t'rte_stack_lf_generic.h',\n+\t\t'rte_stack_lf_c11.h')\ndiff --git a/lib/librte_stack/rte_stack_lf.h b/lib/librte_stack/rte_stack_lf.h\nindex bfd680133..518889a05 100644\n--- a/lib/librte_stack/rte_stack_lf.h\n+++ b/lib/librte_stack/rte_stack_lf.h\n@@ -5,7 +5,11 @@\n #ifndef _RTE_STACK_LF_H_\n #define _RTE_STACK_LF_H_\n \n+#ifdef RTE_USE_C11_MEM_MODEL\n+#include \"rte_stack_lf_c11.h\"\n+#else\n #include \"rte_stack_lf_generic.h\"\n+#endif\n \n /**\n * @internal Push several objects on the lock-free stack (MT-safe).\ndiff --git a/lib/librte_stack/rte_stack_lf_c11.h b/lib/librte_stack/rte_stack_lf_c11.h\nnew file mode 100644\nindex 000000000..a316e9af5\n--- /dev/null\n+++ b/lib/librte_stack/rte_stack_lf_c11.h\n@@ -0,0 +1,175 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2019 Intel Corporation\n+ */\n+\n+#ifndef _RTE_STACK_LF_C11_H_\n+#define _RTE_STACK_LF_C11_H_\n+\n+#include <rte_branch_prediction.h>\n+#include <rte_prefetch.h>\n+\n+static __rte_always_inline unsigned int\n+__rte_stack_lf_count(struct rte_stack *s)\n+{\n+\t/* stack_lf_push() and stack_lf_pop() do not update the list's contents\n+\t * and stack_lf->len atomically, which can cause the list to appear\n+\t * shorter than it actually is if this function is called while other\n+\t * threads are modifying the list.\n+\t *\n+\t * However, given the inherently approximate nature of the get_count\n+\t * callback -- even if the list and its size were updated atomically,\n+\t * the size could change between when get_count executes and when the\n+\t * value is returned to the caller -- this is acceptable.\n+\t *\n+\t * The stack_lf->len updates are placed such that the list may appear to\n+\t * have fewer elements than it does, but will never appear to have more\n+\t * elements. If the mempool is near-empty to the point that this is a\n+\t * concern, the user should consider increasing the mempool size.\n+\t */\n+\treturn (unsigned int)__atomic_load_n(&s->stack_lf.used.len.cnt,\n+\t\t\t\t\t __ATOMIC_RELAXED);\n+}\n+\n+static __rte_always_inline void\n+__rte_stack_lf_push_elems(struct rte_stack_lf_list *list,\n+\t\t\t struct rte_stack_lf_elem *first,\n+\t\t\t struct rte_stack_lf_elem *last,\n+\t\t\t unsigned int num)\n+{\n+#ifndef RTE_ARCH_X86_64\n+\tRTE_SET_USED(first);\n+\tRTE_SET_USED(last);\n+\tRTE_SET_USED(list);\n+\tRTE_SET_USED(num);\n+#else\n+\tstruct rte_stack_lf_head old_head;\n+\tint success;\n+\n+\told_head = list->head;\n+\n+\tdo {\n+\t\tstruct rte_stack_lf_head new_head;\n+\n+\t\t/* Use an acquire fence to establish a synchronized-with\n+\t\t * relationship between the list->head load and store-release\n+\t\t * operations (as part of the rte_atomic128_cmp_exchange()).\n+\t\t */\n+\t\t__atomic_thread_fence(__ATOMIC_ACQUIRE);\n+\n+\t\t/* Swing the top pointer to the first element in the list and\n+\t\t * make the last element point to the old top.\n+\t\t */\n+\t\tnew_head.top = first;\n+\t\tnew_head.cnt = old_head.cnt + 1;\n+\n+\t\tlast->next = old_head.top;\n+\n+\t\t/* Use the release memmodel to ensure the writes to the LF LIFO\n+\t\t * elements are visible before the head pointer write.\n+\t\t */\n+\t\tsuccess = rte_atomic128_cmp_exchange(\n+\t\t\t\t(rte_int128_t *)&list->head,\n+\t\t\t\t(rte_int128_t *)&old_head,\n+\t\t\t\t(rte_int128_t *)&new_head,\n+\t\t\t\t1, __ATOMIC_RELEASE,\n+\t\t\t\t__ATOMIC_RELAXED);\n+\t} while (success == 0);\n+\n+\t/* Ensure the stack modifications are not reordered with respect\n+\t * to the LIFO len update.\n+\t */\n+\t__atomic_add_fetch(&list->len.cnt, num, __ATOMIC_RELEASE);\n+#endif\n+}\n+\n+static __rte_always_inline struct rte_stack_lf_elem *\n+__rte_stack_lf_pop_elems(struct rte_stack_lf_list *list,\n+\t\t\t unsigned int num,\n+\t\t\t void **obj_table,\n+\t\t\t struct rte_stack_lf_elem **last)\n+{\n+#ifndef RTE_ARCH_X86_64\n+\tRTE_SET_USED(obj_table);\n+\tRTE_SET_USED(last);\n+\tRTE_SET_USED(list);\n+\tRTE_SET_USED(num);\n+\n+\treturn NULL;\n+#else\n+\tstruct rte_stack_lf_head old_head;\n+\tuint64_t len;\n+\tint success;\n+\n+\t/* Reserve num elements, if available */\n+\tlen = __atomic_load_n(&list->len.cnt, __ATOMIC_ACQUIRE);\n+\n+\twhile (1) {\n+\t\t/* Does the list contain enough elements? */\n+\t\tif (unlikely(len < num))\n+\t\t\treturn NULL;\n+\n+\t\t/* len is updated on failure */\n+\t\tif (__atomic_compare_exchange_n(&list->len.cnt,\n+\t\t\t\t\t\t&len, len - num,\n+\t\t\t\t\t\t0, __ATOMIC_ACQUIRE,\n+\t\t\t\t\t\t__ATOMIC_ACQUIRE))\n+\t\t\tbreak;\n+\t}\n+\n+\t/* If a torn read occurs, the CAS will fail and set old_head to the\n+\t * correct/latest value.\n+\t */\n+\told_head = list->head;\n+\n+\t/* Pop num elements */\n+\tdo {\n+\t\tstruct rte_stack_lf_head new_head;\n+\t\tstruct rte_stack_lf_elem *tmp;\n+\t\tunsigned int i;\n+\n+\t\t/* Use the acquire memmodel to ensure the reads to the LF LIFO\n+\t\t * elements are properly ordered with respect to the head\n+\t\t * pointer read.\n+\t\t */\n+\t\t__atomic_thread_fence(__ATOMIC_ACQUIRE);\n+\n+\t\trte_prefetch0(old_head.top);\n+\n+\t\ttmp = old_head.top;\n+\n+\t\t/* Traverse the list to find the new head. A next pointer will\n+\t\t * either point to another element or NULL; if a thread\n+\t\t * encounters a pointer that has already been popped, the CAS\n+\t\t * will fail.\n+\t\t */\n+\t\tfor (i = 0; i < num && tmp != NULL; i++) {\n+\t\t\trte_prefetch0(tmp->next);\n+\t\t\tif (obj_table)\n+\t\t\t\tobj_table[i] = tmp->data;\n+\t\t\tif (last)\n+\t\t\t\t*last = tmp;\n+\t\t\ttmp = tmp->next;\n+\t\t}\n+\n+\t\t/* If NULL was encountered, the list was modified while\n+\t\t * traversing it. Retry.\n+\t\t */\n+\t\tif (i != num)\n+\t\t\tcontinue;\n+\n+\t\tnew_head.top = tmp;\n+\t\tnew_head.cnt = old_head.cnt + 1;\n+\n+\t\tsuccess = rte_atomic128_cmp_exchange(\n+\t\t\t\t(rte_int128_t *)&list->head,\n+\t\t\t\t(rte_int128_t *)&old_head,\n+\t\t\t\t(rte_int128_t *)&new_head,\n+\t\t\t\t1, __ATOMIC_RELEASE,\n+\t\t\t\t__ATOMIC_RELAXED);\n+\t} while (success == 0);\n+\n+\treturn old_head.top;\n+#endif\n+}\n+\n+#endif /* _RTE_STACK_LF_C11_H_ */\n", "prefixes": [ "v7", "6/8" ] }