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GET /api/patches/52222/?format=api
{ "id": 52222, "url": "http://patches.dpdk.org/api/patches/52222/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20190403173438.23691-2-gage.eads@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20190403173438.23691-2-gage.eads@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20190403173438.23691-2-gage.eads@intel.com", "date": "2019-04-03T17:34:38", "name": "[v4,1/1] eal: add 128-bit compare exchange (x86-64 only)", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "fbc1c20f0b5d8c2ba04b7d7cac23ea43748c5fd8", "submitter": { "id": 586, "url": "http://patches.dpdk.org/api/people/586/?format=api", "name": "Eads, Gage", "email": "gage.eads@intel.com" }, "delegate": { "id": 1, "url": "http://patches.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20190403173438.23691-2-gage.eads@intel.com/mbox/", "series": [ { "id": 4097, "url": "http://patches.dpdk.org/api/series/4097/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=4097", "date": "2019-04-03T17:34:37", "name": "Add 128-bit compare and set", "version": 4, "mbox": "http://patches.dpdk.org/series/4097/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/52222/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/52222/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id AD9911B53A;\n\tWed, 3 Apr 2019 19:35:35 +0200 (CEST)", "from mga12.intel.com (mga12.intel.com [192.55.52.136])\n\tby dpdk.org (Postfix) with ESMTP id D05681B4E5\n\tfor <dev@dpdk.org>; Wed, 3 Apr 2019 19:35:31 +0200 (CEST)", "from fmsmga005.fm.intel.com ([10.253.24.32])\n\tby fmsmga106.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t03 Apr 2019 10:35:31 -0700", "from txasoft-yocto.an.intel.com ([10.123.72.192])\n\tby fmsmga005.fm.intel.com with ESMTP; 03 Apr 2019 10:35:30 -0700" ], "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.60,305,1549958400\"; d=\"scan'208\";a=\"334697334\"", "From": "Gage Eads <gage.eads@intel.com>", "To": "dev@dpdk.org", "Cc": "olivier.matz@6wind.com, arybchenko@solarflare.com,\n\tbruce.richardson@intel.com, konstantin.ananyev@intel.com,\n\tgavin.hu@arm.com, \n\tHonnappa.Nagarahalli@arm.com, nd@arm.com, chaozhu@linux.vnet.ibm.com, \n\tjerinj@marvell.com, hemant.agrawal@nxp.com, thomas@monjalon.net", "Date": "Wed, 3 Apr 2019 12:34:38 -0500", "Message-Id": "<20190403173438.23691-2-gage.eads@intel.com>", "X-Mailer": "git-send-email 2.13.6", "In-Reply-To": "<20190403173438.23691-1-gage.eads@intel.com>", "References": "<20190304205133.2248-1-gage.eads@intel.com>\n\t<20190403173438.23691-1-gage.eads@intel.com>", "Subject": "[dpdk-dev] [PATCH v4 1/1] eal: add 128-bit compare exchange (x86-64\n\tonly)", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "This operation can be used for non-blocking algorithms, such as a\nnon-blocking stack or ring.\n\nSigned-off-by: Gage Eads <gage.eads@intel.com>\nReviewed-by: Honnappa Nagarahalli <honnappa.nagarahalli@arm.com>\n---\n .../common/include/arch/x86/rte_atomic_64.h | 81 ++++++++++++++++++++++\n 1 file changed, 81 insertions(+)", "diff": "diff --git a/lib/librte_eal/common/include/arch/x86/rte_atomic_64.h b/lib/librte_eal/common/include/arch/x86/rte_atomic_64.h\nindex fd2ec9c53..49bce32c7 100644\n--- a/lib/librte_eal/common/include/arch/x86/rte_atomic_64.h\n+++ b/lib/librte_eal/common/include/arch/x86/rte_atomic_64.h\n@@ -34,6 +34,7 @@\n /*\n * Inspired from FreeBSD src/sys/amd64/include/atomic.h\n * Copyright (c) 1998 Doug Rabson\n+ * Copyright (c) 2019 Intel Corporation\n * All rights reserved.\n */\n \n@@ -46,6 +47,7 @@\n \n #include <stdint.h>\n #include <rte_common.h>\n+#include <rte_compat.h>\n #include <rte_atomic.h>\n \n /*------------------------- 64 bit atomic operations -------------------------*/\n@@ -208,4 +210,83 @@ static inline void rte_atomic64_clear(rte_atomic64_t *v)\n }\n #endif\n \n+/*------------------------ 128 bit atomic operations -------------------------*/\n+\n+/**\n+ * 128-bit integer structure.\n+ */\n+RTE_STD_C11\n+typedef struct {\n+\tRTE_STD_C11\n+\tunion {\n+\t\tuint64_t val[2];\n+\t\t__int128 int128;\n+\t};\n+} __rte_aligned(16) rte_int128_t;\n+\n+/**\n+ * An atomic compare and set function used by the mutex functions.\n+ * (Atomically) Equivalent to:\n+ * if (*dst == *exp)\n+ * *dst = *src\n+ * else\n+ * *exp = *dst\n+ *\n+ * @note The success and failure arguments must be one of the __ATOMIC_* values\n+ * defined in the C++11 standard. For details on their behavior, refer to the\n+ * standard.\n+ *\n+ * @param dst\n+ * The destination into which the value will be written.\n+ * @param exp\n+ * Pointer to the expected value. If the operation fails, this memory is\n+ * updated with the actual value.\n+ * @param src\n+ * Pointer to the new value.\n+ * @param weak\n+ * A value of true allows the comparison to spuriously fail and allows the\n+ * 'exp' update to occur non-atomically (i.e. a torn read may occur).\n+ * Implementations may ignore this argument and only implement the strong\n+ * variant.\n+ * @param success\n+ * If successful, the operation's memory behavior conforms to this (or a\n+ * stronger) model.\n+ * @param failure\n+ * If unsuccessful, the operation's memory behavior conforms to this (or a\n+ * stronger) model. This argument cannot be __ATOMIC_RELEASE,\n+ * __ATOMIC_ACQ_REL, or a stronger model than success.\n+ * @return\n+ * Non-zero on success; 0 on failure.\n+ */\n+static inline int __rte_experimental\n+rte_atomic128_cmp_exchange(rte_int128_t *dst,\n+\t\t\t rte_int128_t *exp,\n+\t\t\t const rte_int128_t *src,\n+\t\t\t unsigned int weak,\n+\t\t\t int success,\n+\t\t\t int failure)\n+{\n+\tRTE_SET_USED(weak);\n+\tRTE_SET_USED(success);\n+\tRTE_SET_USED(failure);\n+\tuint8_t res;\n+\n+\tasm volatile (\n+\t\t MPLOCKED\n+\t\t \"cmpxchg16b %[dst];\"\n+\t\t \" sete %[res]\"\n+\t\t : [dst] \"=m\" (dst->val[0]),\n+\t\t\t\"=a\" (exp->val[0]),\n+\t\t\t\"=d\" (exp->val[1]),\n+\t\t\t[res] \"=r\" (res)\n+\t\t : \"b\" (src->val[0]),\n+\t\t\t\"c\" (src->val[1]),\n+\t\t\t\"a\" (exp->val[0]),\n+\t\t\t\"d\" (exp->val[1]),\n+\t\t\t\"m\" (dst->val[0])\n+\t\t : \"memory\");\n+\n+\treturn res;\n+}\n+\n #endif /* _RTE_ATOMIC_X86_64_H_ */\n", "prefixes": [ "v4", "1/1" ] }