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GET /api/patches/52185/?format=api
{ "id": 52185, "url": "http://patches.dpdk.org/api/patches/52185/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1554292065-186702-15-git-send-email-rosen.xu@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1554292065-186702-15-git-send-email-rosen.xu@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1554292065-186702-15-git-send-email-rosen.xu@intel.com", "date": "2019-04-03T11:47:45", "name": "[v5,14/14] drivers/raw/ifpga_rawdev: add IPN3KE support for IFPGA Rawdev", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": true, "hash": "3cf81bae5123ffdb91ea5e1ed950abd8bfeaa912", "submitter": { "id": 946, "url": "http://patches.dpdk.org/api/people/946/?format=api", "name": "Xu, Rosen", "email": "rosen.xu@intel.com" }, "delegate": { "id": 319, "url": "http://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1554292065-186702-15-git-send-email-rosen.xu@intel.com/mbox/", "series": [ { "id": 4084, "url": "http://patches.dpdk.org/api/series/4084/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=4084", "date": "2019-04-03T11:47:31", "name": "Add patch set for IPN3KE", "version": 5, "mbox": "http://patches.dpdk.org/series/4084/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/52185/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/52185/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 4AA781B45D;\n\tWed, 3 Apr 2019 13:47:34 +0200 (CEST)", "from mga11.intel.com (mga11.intel.com [192.55.52.93])\n\tby dpdk.org (Postfix) with ESMTP id 000501B44A\n\tfor <dev@dpdk.org>; Wed, 3 Apr 2019 13:47:26 +0200 (CEST)", "from fmsmga005.fm.intel.com ([10.253.24.32])\n\tby fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t03 Apr 2019 04:47:26 -0700", "from dpdkx8602.sh.intel.com ([10.67.110.200])\n\tby fmsmga005.fm.intel.com with ESMTP; 03 Apr 2019 04:47:24 -0700" ], "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.60,304,1549958400\"; d=\"scan'208\";a=\"334606385\"", "From": "Rosen Xu <rosen.xu@intel.com>", "To": "dev@dpdk.org", "Cc": "ferruh.yigit@intel.com, tianfei.zhang@intel.com, dan.wei@intel.com,\n\trosen.xu@intel.com, andy.pei@intel.com, qiming.yang@intel.com,\n\thaiyue.wang@intel.com, santos.chen@intel.com, zhang.zhang@intel.com, \n\tdavid.lomartire@intel.com", "Date": "Wed, 3 Apr 2019 19:47:45 +0800", "Message-Id": "<1554292065-186702-15-git-send-email-rosen.xu@intel.com>", "X-Mailer": "git-send-email 1.8.3.1", "In-Reply-To": "<1554292065-186702-1-git-send-email-rosen.xu@intel.com>", "References": "<1551338000-120348-1-git-send-email-rosen.xu@intel.com>\n\t<1554292065-186702-1-git-send-email-rosen.xu@intel.com>", "Subject": "[dpdk-dev] [PATCH v5 14/14] drivers/raw/ifpga_rawdev: add IPN3KE\n\tsupport for IFPGA Rawdev", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Add Intel FPGA Acceleration NIC IPN3KE support for IFPGA Rawdev.\n\nSigned-off-by: Rosen Xu <rosen.xu@intel.com>\nSigned-off-by: Tianfei Zhang <tianfei.zhang@intel.com>\nSigned-off-by: Andy Pei <andy.pei@intel.com>\n---\n drivers/raw/ifpga_rawdev/Makefile | 1 +\n drivers/raw/ifpga_rawdev/ifpga_rawdev.c | 248 +++++++++++++++++++++++++++++++-\n drivers/raw/ifpga_rawdev/ifpga_rawdev.h | 14 +-\n drivers/raw/ifpga_rawdev/meson.build | 6 +-\n 4 files changed, 264 insertions(+), 5 deletions(-)", "diff": "diff --git a/drivers/raw/ifpga_rawdev/Makefile b/drivers/raw/ifpga_rawdev/Makefile\nindex f3b9d5e..f60b547 100644\n--- a/drivers/raw/ifpga_rawdev/Makefile\n+++ b/drivers/raw/ifpga_rawdev/Makefile\n@@ -13,6 +13,7 @@ CFLAGS += -O3\n CFLAGS += $(WERROR_FLAGS)\n CFLAGS += -I$(RTE_SDK)/drivers/bus/ifpga\n CFLAGS += -I$(RTE_SDK)/drivers/raw/ifpga_rawdev\n+CFLAGS += -I$(RTE_SDK)/drivers/net/ipn3ke\n LDLIBS += -lrte_eal\n LDLIBS += -lrte_rawdev\n LDLIBS += -lrte_bus_vdev\ndiff --git a/drivers/raw/ifpga_rawdev/ifpga_rawdev.c b/drivers/raw/ifpga_rawdev/ifpga_rawdev.c\nindex da772d0..9042fe9 100644\n--- a/drivers/raw/ifpga_rawdev/ifpga_rawdev.c\n+++ b/drivers/raw/ifpga_rawdev/ifpga_rawdev.c\n@@ -34,6 +34,7 @@\n #include \"ifpga_common.h\"\n #include \"ifpga_logs.h\"\n #include \"ifpga_rawdev.h\"\n+#include \"ipn3ke_rawdev_api.h\"\n \n int ifpga_rawdev_logtype;\n \n@@ -42,10 +43,12 @@\n #define PCIE_DEVICE_ID_PF_INT_5_X 0xBCBD\n #define PCIE_DEVICE_ID_PF_INT_6_X 0xBCC0\n #define PCIE_DEVICE_ID_PF_DSC_1_X 0x09C4\n+#define PCIE_DEVICE_ID_PAC_N3000 0x0B30\n /* VF Device */\n #define PCIE_DEVICE_ID_VF_INT_5_X 0xBCBF\n #define PCIE_DEVICE_ID_VF_INT_6_X 0xBCC1\n #define PCIE_DEVICE_ID_VF_DSC_1_X 0x09C5\n+#define PCIE_DEVICE_ID_VF_PAC_N3000 0x0B31\n #define RTE_MAX_RAW_DEVICE 10\n \n static const struct rte_pci_id pci_ifpga_map[] = {\n@@ -55,6 +58,8 @@\n \t{ RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_VF_INT_6_X) },\n \t{ RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_PF_DSC_1_X) },\n \t{ RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_VF_DSC_1_X) },\n+\t{ RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_PAC_N3000),},\n+\t{ RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_VF_PAC_N3000),},\n \t{ .vendor_id = 0, /* sentinel */ },\n };\n \n@@ -103,6 +108,10 @@\n \tstruct opae_adapter *adapter;\n \tstruct opae_accelerator *acc;\n \tstruct rte_afu_device *afu_dev;\n+\tstruct opae_manager *mgr = NULL;\n+\tstruct opae_eth_group_region_info opae_lside_eth_info;\n+\tstruct opae_eth_group_region_info opae_nside_eth_info;\n+\tint lside_bar_idx, nside_bar_idx;\n \n \tIFPGA_RAWDEV_PMD_FUNC_TRACE();\n \n@@ -128,6 +137,45 @@\n \t\t\treturn;\n \t\t}\n \t}\n+\n+\t/* get opae_manager to rawdev */\n+\tmgr = opae_adapter_get_mgr(adapter);\n+\tif (mgr) {\n+\t\t//get LineSide BAR Index\n+\t\tif (opae_manager_get_eth_group_region_info(mgr, 0,\n+\t\t\t&opae_lside_eth_info)) {\n+\t\t\treturn;\n+\t\t}\n+\t\tlside_bar_idx = opae_lside_eth_info.mem_idx;\n+\n+\t\t//get NICSide BAR Index\n+\t\tif (opae_manager_get_eth_group_region_info(mgr, 1,\n+\t\t\t&opae_nside_eth_info)) {\n+\t\t\treturn;\n+\t\t}\n+\t\tnside_bar_idx = opae_nside_eth_info.mem_idx;\n+\n+\t\tif (lside_bar_idx >= PCI_MAX_RESOURCE ||\n+\t\t\tnside_bar_idx >= PCI_MAX_RESOURCE ||\n+\t\t\tlside_bar_idx == nside_bar_idx)\n+\t\t\treturn;\n+\n+\t\t//fill LineSide BAR Index\n+\t\tafu_dev->mem_resource[lside_bar_idx].phys_addr =\n+\t\t\topae_lside_eth_info.phys_addr;\n+\t\tafu_dev->mem_resource[lside_bar_idx].len =\n+\t\t\topae_lside_eth_info.len;\n+\t\tafu_dev->mem_resource[lside_bar_idx].addr =\n+\t\t\topae_lside_eth_info.addr;\n+\n+\t\t//fill NICSide BAR Index\n+\t\tafu_dev->mem_resource[nside_bar_idx].phys_addr =\n+\t\t\topae_nside_eth_info.phys_addr;\n+\t\tafu_dev->mem_resource[nside_bar_idx].len =\n+\t\t\topae_nside_eth_info.len;\n+\t\tafu_dev->mem_resource[nside_bar_idx].addr =\n+\t\t\topae_nside_eth_info.addr;\n+\t}\n }\n \n static int\n@@ -327,6 +375,201 @@\n \treturn 0;\n }\n \n+static int\n+ifpga_rawdev_get_attr(struct rte_rawdev *dev,\n+\tconst char *attr_name, uint64_t *attr_value)\n+{\n+\tstruct opae_adapter *adapter;\n+\tstruct opae_manager *mgr;\n+\tstruct opae_retimer_info opae_rtm_info;\n+\tstruct opae_retimer_status opae_rtm_status;\n+\tstruct opae_eth_group_info opae_eth_grp_info;\n+\tstruct opae_eth_group_region_info opae_eth_grp_reg_info;\n+\tint eth_group_num = 0;\n+\tuint64_t port_link_bitmap = 0, port_link_bit;\n+\tuint32_t i, j, p, q;\n+\n+#define MAX_PORT_PER_RETIMER 4\n+\n+\tIFPGA_RAWDEV_PMD_FUNC_TRACE();\n+\n+\tif (!dev || !attr_name || !attr_value) {\n+\t\tIFPGA_RAWDEV_PMD_ERR(\"Invalid arguments for getting attributes\");\n+\t\treturn -1;\n+\t}\n+\n+\tadapter = ifpga_rawdev_get_priv(dev);\n+\tif (!adapter) {\n+\t\tIFPGA_RAWDEV_PMD_ERR(\"Adapter of dev %s is NULL\", dev->name);\n+\t\treturn -1;\n+\t}\n+\n+\tmgr = opae_adapter_get_mgr(adapter);\n+\tif (!mgr) {\n+\t\tIFPGA_RAWDEV_PMD_ERR(\"opae_manager of opae_adapter is NULL\");\n+\t\treturn -1;\n+\t}\n+\n+\t/* currently, eth_group_num is always 2 */\n+\teth_group_num = opae_manager_get_eth_group_nums(mgr);\n+\tif (eth_group_num < 0)\n+\t\treturn -1;\n+\n+\tif (!strcmp(attr_name, \"LineSideBaseMAC\")) {\n+\t\t/* Currently FPGA not implement, so just set all zeros*/\n+\t\t*attr_value = (uint64_t)0;\n+\t\treturn 0;\n+\t}\n+\tif (!strcmp(attr_name, \"LineSideMACType\")) {\n+\t\t/* eth_group 0 on FPGA connect to LineSide */\n+\t\tif (opae_manager_get_eth_group_info(mgr, 0,\n+\t\t\t&opae_eth_grp_info))\n+\t\t\treturn -1;\n+\t\tswitch (opae_eth_grp_info.speed) {\n+\t\tcase ETH_SPEED_10G:\n+\t\t\t*attr_value =\n+\t\t\t(uint64_t)(IFPGA_RAWDEV_RETIMER_MAC_TYPE_10GE_XFI);\n+\t\t\tbreak;\n+\t\tcase ETH_SPEED_25G:\n+\t\t\t*attr_value =\n+\t\t\t(uint64_t)(IFPGA_RAWDEV_RETIMER_MAC_TYPE_25GE_25GAUI);\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\t*attr_value =\n+\t\t\t(uint64_t)(IFPGA_RAWDEV_RETIMER_MAC_TYPE_UNKNOWN);\n+\t\t\tbreak;\n+\t\t}\n+\t\treturn 0;\n+\t}\n+\tif (!strcmp(attr_name, \"LineSideLinkSpeed\")) {\n+\t\tif (opae_manager_get_retimer_status(mgr, &opae_rtm_status))\n+\t\t\treturn -1;\n+\t\tswitch (opae_rtm_status.speed) {\n+\t\tcase MXD_1GB:\n+\t\t\t*attr_value =\n+\t\t\t\t(uint64_t)(IFPGA_RAWDEV_LINK_SPEED_UNKNOWN);\n+\t\t\tbreak;\n+\t\tcase MXD_2_5GB:\n+\t\t\t*attr_value =\n+\t\t\t\t(uint64_t)(IFPGA_RAWDEV_LINK_SPEED_UNKNOWN);\n+\t\t\tbreak;\n+\t\tcase MXD_5GB:\n+\t\t\t*attr_value =\n+\t\t\t\t(uint64_t)(IFPGA_RAWDEV_LINK_SPEED_UNKNOWN);\n+\t\t\tbreak;\n+\t\tcase MXD_10GB:\n+\t\t\t*attr_value =\n+\t\t\t\t(uint64_t)(IFPGA_RAWDEV_LINK_SPEED_10GB);\n+\t\t\tbreak;\n+\t\tcase MXD_25GB:\n+\t\t\t*attr_value =\n+\t\t\t\t(uint64_t)(IFPGA_RAWDEV_LINK_SPEED_25GB);\n+\t\t\tbreak;\n+\t\tcase MXD_40GB:\n+\t\t\t*attr_value =\n+\t\t\t\t(uint64_t)(IFPGA_RAWDEV_LINK_SPEED_40GB);\n+\t\t\tbreak;\n+\t\tcase MXD_100GB:\n+\t\t\t*attr_value =\n+\t\t\t\t(uint64_t)(IFPGA_RAWDEV_LINK_SPEED_UNKNOWN);\n+\t\t\tbreak;\n+\t\tcase MXD_SPEED_UNKNOWN:\n+\t\t\t*attr_value =\n+\t\t\t\t(uint64_t)(IFPGA_RAWDEV_LINK_SPEED_UNKNOWN);\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\t*attr_value =\n+\t\t\t\t(uint64_t)(IFPGA_RAWDEV_LINK_SPEED_UNKNOWN);\n+\t\t\tbreak;\n+\t\t}\n+\t\treturn 0;\n+\t}\n+\tif (!strcmp(attr_name, \"LineSideLinkRetimerNum\")) {\n+\t\tif (opae_manager_get_retimer_info(mgr, &opae_rtm_info))\n+\t\t\treturn -1;\n+\t\t*attr_value = (uint64_t)(opae_rtm_info.nums_retimer);\n+\t\treturn 0;\n+\t}\n+\tif (!strcmp(attr_name, \"LineSideLinkPortNum\")) {\n+\t\tif (opae_manager_get_retimer_info(mgr, &opae_rtm_info))\n+\t\t\treturn -1;\n+\t\tuint64_t tmp = opae_rtm_info.ports_per_retimer *\n+\t\t\topae_rtm_info.nums_retimer;\n+\t\t*attr_value = tmp;\n+\t\treturn 0;\n+\t}\n+\tif (!strcmp(attr_name, \"LineSideLinkStatus\")) {\n+\t\tif (opae_manager_get_retimer_info(mgr, &opae_rtm_info))\n+\t\t\treturn -1;\n+\t\tif (opae_manager_get_retimer_status(mgr, &opae_rtm_status))\n+\t\t\treturn -1;\n+\t\t(*attr_value) = 0;\n+\t\tq = 0;\n+\t\tport_link_bitmap = (uint64_t)(opae_rtm_status.line_link_bitmap);\n+\t\tfor (i = 0; i < opae_rtm_info.nums_retimer; i++) {\n+\t\t\tp = i * MAX_PORT_PER_RETIMER;\n+\t\t\tfor (j = 0; j < opae_rtm_info.ports_per_retimer; j++) {\n+\t\t\t\tport_link_bit = 0;\n+\t\t\t\tIFPGA_BIT_SET(port_link_bit, (p+j));\n+\t\t\t\tport_link_bit &= port_link_bitmap;\n+\t\t\t\tif (port_link_bit)\n+\t\t\t\t\tIFPGA_BIT_SET((*attr_value), q);\n+\t\t\t\tq++;\n+\t\t\t}\n+\t\t}\n+\t\treturn 0;\n+\t}\n+\tif (!strcmp(attr_name, \"LineSideBARIndex\")) {\n+\t\t/* eth_group 0 on FPGA connect to LineSide */\n+\t\tif (opae_manager_get_eth_group_region_info(mgr, 0,\n+\t\t\t&opae_eth_grp_reg_info))\n+\t\t\treturn -1;\n+\t\t*attr_value = (uint64_t)opae_eth_grp_reg_info.mem_idx;\n+\t\treturn 0;\n+\t}\n+\tif (!strcmp(attr_name, \"NICSideMACType\")) {\n+\t\t/* eth_group 1 on FPGA connect to NicSide */\n+\t\tif (opae_manager_get_eth_group_info(mgr, 1,\n+\t\t\t&opae_eth_grp_info))\n+\t\t\treturn -1;\n+\t\t*attr_value = (uint64_t)(opae_eth_grp_info.speed);\n+\t\treturn 0;\n+\t}\n+\tif (!strcmp(attr_name, \"NICSideLinkSpeed\")) {\n+\t\t/* eth_group 1 on FPGA connect to NicSide */\n+\t\tif (opae_manager_get_eth_group_info(mgr, 1,\n+\t\t\t&opae_eth_grp_info))\n+\t\t\treturn -1;\n+\t\t*attr_value = (uint64_t)(opae_eth_grp_info.speed);\n+\t\treturn 0;\n+\t}\n+\tif (!strcmp(attr_name, \"NICSideLinkPortNum\")) {\n+\t\tif (opae_manager_get_retimer_info(mgr, &opae_rtm_info))\n+\t\t\treturn -1;\n+\t\tuint64_t tmp = opae_rtm_info.nums_fvl *\n+\t\t\t\t\topae_rtm_info.ports_per_fvl;\n+\t\t*attr_value = tmp;\n+\t\treturn 0;\n+\t}\n+\tif (!strcmp(attr_name, \"NICSideLinkStatus\")) {\n+\t\t/*\n+\t\t *\n+\t\t */\n+\t\treturn 0;\n+\t}\n+\tif (!strcmp(attr_name, \"NICSideBARIndex\")) {\n+\t\t/* eth_group 1 on FPGA connect to NicSide */\n+\t\tif (opae_manager_get_eth_group_region_info(mgr, 1,\n+\t\t\t&opae_eth_grp_reg_info))\n+\t\t\treturn -1;\n+\t\t*attr_value = (uint64_t)opae_eth_grp_reg_info.mem_idx;\n+\t\treturn 0;\n+\t}\n+\n+\tIFPGA_RAWDEV_PMD_ERR(\"attr_name not support\");\n+\treturn -1;\n+}\n+\n static const struct rte_rawdev_ops ifpga_rawdev_ops = {\n \t.dev_info_get = ifpga_rawdev_info_get,\n \t.dev_configure = ifpga_rawdev_configure,\n@@ -339,7 +582,7 @@\n \t.queue_setup = NULL,\n \t.queue_release = NULL,\n \n-\t.attr_get = NULL,\n+\t.attr_get = ifpga_rawdev_get_attr,\n \t.attr_set = NULL,\n \n \t.enqueue_bufs = NULL,\n@@ -419,7 +662,7 @@\n \n \trawdev->dev_ops = &ifpga_rawdev_ops;\n \trawdev->device = &pci_dev->device;\n-\trawdev->driver_name = pci_dev->device.driver->name;\n+\trawdev->driver_name = pci_dev->driver->driver.name;\n \n \t/* must enumerate the adapter before use it */\n \tret = opae_adapter_enumerate(adapter);\n@@ -491,7 +734,6 @@\n ifpga_rawdev_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,\n \tstruct rte_pci_device *pci_dev)\n {\n-\n \tIFPGA_RAWDEV_PMD_FUNC_TRACE();\n \treturn ifpga_rawdev_create(pci_dev, rte_socket_id());\n }\ndiff --git a/drivers/raw/ifpga_rawdev/ifpga_rawdev.h b/drivers/raw/ifpga_rawdev/ifpga_rawdev.h\nindex c7759b8..fcb1a96 100644\n--- a/drivers/raw/ifpga_rawdev/ifpga_rawdev.h\n+++ b/drivers/raw/ifpga_rawdev/ifpga_rawdev.h\n@@ -8,7 +8,7 @@\n extern int ifpga_rawdev_logtype;\n \n #define IFPGA_RAWDEV_PMD_LOG(level, fmt, args...) \\\n-\trte_log(RTE_LOG_ ## level, ifpga_rawdev_logtype, \"ifgpa: \" fmt, \\\n+\trte_log(RTE_LOG_ ## level, ifpga_rawdev_logtype, \"ifpga_rawdev: \" fmt, \\\n \t\t##args)\n \n #define IFPGA_RAWDEV_PMD_FUNC_TRACE() IFPGA_RAWDEV_PMD_LOG(DEBUG, \">>\")\n@@ -28,6 +28,18 @@ enum ifpga_rawdev_device_state {\n \tIFPGA_ERROR\n };\n \n+/** Set a bit in the uint64 variable */\n+#define IFPGA_BIT_SET(var, pos) \\\n+\t((var) |= ((uint64_t)1 << ((pos))))\n+\n+/** Reset the bit in the variable */\n+#define IFPGA_BIT_RESET(var, pos) \\\n+\t((var) &= ~((uint64_t)1 << ((pos))))\n+\n+/** Check the bit is set in the variable */\n+#define IFPGA_BIT_ISSET(var, pos) \\\n+\t(((var) & ((uint64_t)1 << ((pos)))) ? 1 : 0)\n+\n static inline struct opae_adapter *\n ifpga_rawdev_get_priv(const struct rte_rawdev *rawdev)\n {\ndiff --git a/drivers/raw/ifpga_rawdev/meson.build b/drivers/raw/ifpga_rawdev/meson.build\nindex 6725687..132b777 100644\n--- a/drivers/raw/ifpga_rawdev/meson.build\n+++ b/drivers/raw/ifpga_rawdev/meson.build\n@@ -6,8 +6,12 @@ version = 1\n subdir('base')\n objs = [base_objs]\n \n+dep = dependency('libfdt', required: false)\n+if not dep.found()\n+\tbuild = false\n+endif\n deps += ['rawdev', 'pci', 'bus_pci', 'kvargs',\n-\t'bus_vdev', 'bus_ifpga']\n+\t'bus_vdev', 'bus_ifpga', 'net']\n sources = files('ifpga_rawdev.c')\n \n includes += include_directories('base')\n", "prefixes": [ "v5", "14/14" ] }