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GET /api/patches/52150/?format=api
{ "id": 52150, "url": "http://patches.dpdk.org/api/patches/52150/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1554281204-19196-4-git-send-email-rosen.xu@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1554281204-19196-4-git-send-email-rosen.xu@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1554281204-19196-4-git-send-email-rosen.xu@intel.com", "date": "2019-04-03T08:46:33", "name": "[v4,03/14] drivers/net/ipn3ke: add IPN3KE ethdev PMD driver", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "b6c6066890ac53c95d9cf419ff4a031d334a508c", "submitter": { "id": 946, "url": "http://patches.dpdk.org/api/people/946/?format=api", "name": "Xu, Rosen", "email": "rosen.xu@intel.com" }, "delegate": { "id": 319, "url": "http://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1554281204-19196-4-git-send-email-rosen.xu@intel.com/mbox/", "series": [ { "id": 4077, "url": "http://patches.dpdk.org/api/series/4077/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=4077", "date": "2019-04-03T08:46:30", "name": "Add patch set for IPN3KE", "version": 4, "mbox": "http://patches.dpdk.org/series/4077/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/52150/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/52150/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 89D401B10C;\n\tWed, 3 Apr 2019 10:45:56 +0200 (CEST)", "from mga09.intel.com (mga09.intel.com [134.134.136.24])\n\tby dpdk.org (Postfix) with ESMTP id 1A2921B104\n\tfor <dev@dpdk.org>; Wed, 3 Apr 2019 10:45:53 +0200 (CEST)", "from orsmga001.jf.intel.com ([10.7.209.18])\n\tby orsmga102.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t03 Apr 2019 01:45:53 -0700", "from dpdkx8602.sh.intel.com ([10.67.110.200])\n\tby orsmga001.jf.intel.com with ESMTP; 03 Apr 2019 01:45:50 -0700" ], "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.60,304,1549958400\"; d=\"scan'208\";a=\"220102451\"", "From": "Rosen Xu <rosen.xu@intel.com>", "To": "dev@dpdk.org", "Cc": "ferruh.yigit@intel.com, tianfei.zhang@intel.com, dan.wei@intel.com,\n\trosen.xu@intel.com, andy.pei@intel.com, qiming.yang@intel.com,\n\thaiyue.wang@intel.com, santos.chen@intel.com, zhang.zhang@intel.com", "Date": "Wed, 3 Apr 2019 16:46:33 +0800", "Message-Id": "<1554281204-19196-4-git-send-email-rosen.xu@intel.com>", "X-Mailer": "git-send-email 1.8.3.1", "In-Reply-To": "<1554281204-19196-1-git-send-email-rosen.xu@intel.com>", "References": "<1551338000-120348-1-git-send-email-rosen.xu@intel.com>\n\t<1554281204-19196-1-git-send-email-rosen.xu@intel.com>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=y", "Content-Transfer-Encoding": "8bit", "Subject": "[dpdk-dev] [PATCH v4 03/14] drivers/net/ipn3ke: add IPN3KE ethdev\n\tPMD driver", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Add Intel FPGA Acceleration NIC IPN3KE ethdev PMD driver.\n\nSigned-off-by: Rosen Xu <rosen.xu@intel.com>\nSigned-off-by: Andy Pei <andy.pei@intel.com>\nSigned-off-by: Dan Wei <dan.wei@intel.com>\n---\n MAINTAINERS | 7 +\n config/common_base | 4 +\n doc/guides/nics/features/ipn3ke.ini | 55 ++\n doc/guides/nics/index.rst | 1 +\n doc/guides/nics/ipn3ke.rst | 98 +++\n drivers/net/Makefile | 1 +\n drivers/net/ipn3ke/Makefile | 36 ++\n drivers/net/ipn3ke/ipn3ke_ethdev.c | 707 ++++++++++++++++++++\n drivers/net/ipn3ke/ipn3ke_ethdev.h | 891 ++++++++++++++++++++++++++\n drivers/net/ipn3ke/ipn3ke_logs.h | 30 +\n drivers/net/ipn3ke/ipn3ke_rawdev_api.h | 62 ++\n drivers/net/ipn3ke/meson.build | 6 +\n drivers/net/ipn3ke/rte_pmd_ipn3ke_version.map | 4 +\n drivers/net/meson.build | 1 +\n mk/rte.app.mk | 1 +\n usertools/dpdk-devbind.py | 4 +-\n 16 files changed, 1907 insertions(+), 1 deletion(-)\n create mode 100644 doc/guides/nics/features/ipn3ke.ini\n create mode 100644 doc/guides/nics/ipn3ke.rst\n create mode 100644 drivers/net/ipn3ke/Makefile\n create mode 100644 drivers/net/ipn3ke/ipn3ke_ethdev.c\n create mode 100644 drivers/net/ipn3ke/ipn3ke_ethdev.h\n create mode 100644 drivers/net/ipn3ke/ipn3ke_logs.h\n create mode 100644 drivers/net/ipn3ke/ipn3ke_rawdev_api.h\n create mode 100644 drivers/net/ipn3ke/meson.build\n create mode 100644 drivers/net/ipn3ke/rte_pmd_ipn3ke_version.map", "diff": "diff --git a/MAINTAINERS b/MAINTAINERS\nindex e9ff2b4..92c1912 100644\n--- a/MAINTAINERS\n+++ b/MAINTAINERS\n@@ -608,6 +608,13 @@ F: drivers/net/ice/\n F: doc/guides/nics/ice.rst\n F: doc/guides/nics/features/ice.ini\n \n+Intel ipn3ke\n+M: Rosen Xu <rosen.xu@intel.com>\n+T: git://dpdk.org/next/dpdk-next-net-intel\n+F: drivers/net/ipn3ke/\n+F: doc/guides/nics/ipn3ke.rst\n+F: doc/guides/nics/features/ipn3ke.ini\n+\n Marvell mvpp2\n M: Tomasz Duszynski <tdu@semihalf.com>\n M: Liron Himi <lironh@marvell.com>\ndiff --git a/config/common_base b/config/common_base\nindex 6292bc4..ee148a1 100644\n--- a/config/common_base\n+++ b/config/common_base\n@@ -328,6 +328,10 @@ CONFIG_RTE_LIBRTE_IAVF_DEBUG_TX=n\n CONFIG_RTE_LIBRTE_IAVF_DEBUG_TX_FREE=n\n CONFIG_RTE_LIBRTE_IAVF_DEBUG_RX=n\n CONFIG_RTE_LIBRTE_IAVF_16BYTE_RX_DESC=n\n+#\n+# Compile burst-oriented IPN3KE PMD driver\n+#\n+CONFIG_RTE_LIBRTE_IPN3KE_PMD=y\n \n #\n # Compile burst-oriented Mellanox ConnectX-3 (MLX4) PMD\ndiff --git a/doc/guides/nics/features/ipn3ke.ini b/doc/guides/nics/features/ipn3ke.ini\nnew file mode 100644\nindex 0000000..a194e35\n--- /dev/null\n+++ b/doc/guides/nics/features/ipn3ke.ini\n@@ -0,0 +1,55 @@\n+;\n+; Supported features of the 'ipn3ke' network poll mode driver.\n+;\n+; Refer to default.ini for the full list of available PMD features.\n+;\n+[Features]\n+Speed capabilities = Y\n+Link status = Y\n+Link status event = Y\n+Rx interrupt = Y\n+Queue start/stop = Y\n+Runtime Rx queue setup = Y\n+Runtime Tx queue setup = Y\n+Jumbo frame = Y\n+Scattered Rx = Y\n+TSO = Y\n+Promiscuous mode = Y\n+Allmulticast mode = Y\n+Unicast MAC filter = Y\n+Multicast MAC filter = Y\n+RSS hash = Y\n+RSS key update = Y\n+RSS reta update = Y\n+VMDq = Y\n+SR-IOV = Y\n+DCB = Y\n+VLAN filter = Y\n+Ethertype filter = Y\n+Tunnel filter = Y\n+Hash filter = Y\n+Flow director = Y\n+Flow control = Y\n+Flow API = Y\n+Traffic mirroring = Y\n+CRC offload = Y\n+VLAN offload = Y\n+QinQ offload = Y\n+L3 checksum offload = Y\n+L4 checksum offload = Y\n+Inner L3 checksum = Y\n+Inner L4 checksum = Y\n+Packet type parsing = Y\n+Timesync = Y\n+Rx descriptor status = Y\n+Tx descriptor status = Y\n+Basic stats = Y\n+Extended stats = Y\n+FW version = Y\n+Module EEPROM dump = Y\n+Multiprocess aware = Y\n+BSD nic_uio = Y\n+Linux UIO = Y\n+Linux VFIO = Y\n+x86-32 = Y\n+x86-64 = Y\ndiff --git a/doc/guides/nics/index.rst b/doc/guides/nics/index.rst\nindex 5c80e3b..611ffb8 100644\n--- a/doc/guides/nics/index.rst\n+++ b/doc/guides/nics/index.rst\n@@ -30,6 +30,7 @@ Network Interface Controller Drivers\n ice\n ifc\n igb\n+ ipn3ke\n ixgbe\n intel_vf\n kni\ndiff --git a/doc/guides/nics/ipn3ke.rst b/doc/guides/nics/ipn3ke.rst\nnew file mode 100644\nindex 0000000..9fec75e\n--- /dev/null\n+++ b/doc/guides/nics/ipn3ke.rst\n@@ -0,0 +1,98 @@\n+.. SPDX-License-Identifier: BSD-3-Clause\n+ Copyright(c) 2019 Intel Corporation.\n+\n+IPN3KE Poll Mode Driver\n+=======================\n+\n+The ipn3ke PMD (librte_pmd_ipn3ke) provides poll mode driver support\n+for Intel® FPGA PAC(Programmable Acceleration Card) N3000 based on\n+the Intel Ethernet Controller X710/XXV710 and Intel Arria 10 FPGA.\n+\n+In this card, FPGA is an acceleration bridge between network interface\n+and the Intel Ethernet Controller. Although both FPGA and Ethernet\n+Controllers are connected to CPU with PCIe Gen3x16 Switch, all the\n+packet RX/TX is handled by Intel Ethernet Controller. So from application\n+point of view the data path is still the legacy Intel Ethernet Controller\n+X710/XXV710 PMD. Besides this, users can enable more acceleration\n+features by FPGA IP.\n+\n+Prerequisites\n+-------------\n+\n+- Identifying your adapter using `Intel Support\n+ <http://www.intel.com/support>`_ and get the latest NVM/FW images.\n+\n+- Follow the DPDK :ref:`Getting Started Guide for Linux <linux_gsg>` to setup the basic DPDK environment.\n+\n+- To get better performance on Intel platforms, please follow the \"How to get best performance with NICs on Intel platforms\"\n+ section of the :ref:`Getting Started Guide for Linux <linux_gsg>`.\n+\n+\n+Pre-Installation Configuration\n+------------------------------\n+\n+Config File Options\n+~~~~~~~~~~~~~~~~~~~\n+\n+The following options can be modified in the ``config`` file.\n+Please note that enabling debugging options may affect system performance.\n+\n+- ``CONFIG_RTE_LIBRTE_IPN3KE_PMD`` (default ``n``)\n+\n+ Toggle compilation of the ``librte_pmd_ipn3ke`` driver.\n+\n+Runtime Config Options\n+~~~~~~~~~~~~~~~~~~~~~~\n+\n+- ``AFU name``\n+\n+ AFU name identifies which AFU is used by IPN3KE.\n+\n+- ``FPGA Acceleration list``\n+\n+ For IPN3KE FPGA can provide different bitstream, different bitstream includes different\n+ Acceleration, so users need to identify which Acceleration is used.\n+\n+- ``I40e PF name list``\n+\n+ Users need to bind FPGA LineSidePort to FVL PF. So I40e PF name list should be involved in\n+ startup command.\n+\n+Driver compilation and testing\n+------------------------------\n+\n+Refer to the document :ref:`compiling and testing a PMD for a NIC <pmd_build_and_test>`\n+for details.\n+\n+Sample Application Notes\n+------------------------\n+\n+Packet TX/RX with FPGA Pass-through image\n+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n+\n+FPGA Pass-through bitstream is original FPGA Image.\n+\n+To start ``testpmd``, and add I40e PF to FPGA network port:\n+\n+.. code-block:: console\n+\n+ ./app/testpmd -l 0-15 -n 4 --vdev 'ifpga_rawdev_cfg0,ifpga=b3:00.0,port=0' --vdev 'ipn3ke_cfg0,afu=0|b3:00.0,i40e_pf={0000:b1:00.0|0000:b1:00.1|0000:b1:00.2|0000:b1:00.3|0000:b5:00.0|0000:b5:00.1|0000:b5:00.2|0000:b5:00.3}' -- -i --no-numa --port-topology=loop\n+\n+HQoS and flow acceleration\n+~~~~~~~~~~~~~~~~~~~~~~~~~~\n+\n+HQoS and flow acceleration bitstream is used to offloading HQoS and flow classifier.\n+\n+To start ``testpmd``, and add I40e PF to FPGA network port, enable FPGA HQoS and Flow Acceleration:\n+\n+.. code-block:: console\n+\n+ ./app/testpmd -l 0-15 -n 4 --vdev 'ifpga_rawdev_cfg0,ifpga=b3:00.0,port=0' --vdev 'ipn3ke_cfg0,afu=0|b3:00.0,fpga_acc={tm|flow},i40e_pf={0000:b1:00.0|0000:b1:00.1|0000:b1:00.2|0000:b1:00.3|0000:b5:00.0|0000:b5:00.1|0000:b5:00.2|0000:b5:00.3}' -- -i --no-numa --forward-mode=macswap\n+\n+Limitations or Known issues\n+---------------------------\n+\n+19.05 limitation\n+~~~~~~~~~~~~~~~~\n+\n+Ipn3ke code released in 19.05 is for evaluation only.\ndiff --git a/drivers/net/Makefile b/drivers/net/Makefile\nindex 502869a..f78a6bc 100644\n--- a/drivers/net/Makefile\n+++ b/drivers/net/Makefile\n@@ -31,6 +31,7 @@ DIRS-$(CONFIG_RTE_LIBRTE_FM10K_PMD) += fm10k\n DIRS-$(CONFIG_RTE_LIBRTE_I40E_PMD) += i40e\n DIRS-$(CONFIG_RTE_LIBRTE_IAVF_PMD) += iavf\n DIRS-$(CONFIG_RTE_LIBRTE_ICE_PMD) += ice\n+DIRS-$(CONFIG_RTE_LIBRTE_IPN3KE_PMD) += ipn3ke\n DIRS-$(CONFIG_RTE_LIBRTE_IXGBE_PMD) += ixgbe\n DIRS-$(CONFIG_RTE_LIBRTE_LIO_PMD) += liquidio\n DIRS-$(CONFIG_RTE_LIBRTE_MLX4_PMD) += mlx4\ndiff --git a/drivers/net/ipn3ke/Makefile b/drivers/net/ipn3ke/Makefile\nnew file mode 100644\nindex 0000000..d7aa79b\n--- /dev/null\n+++ b/drivers/net/ipn3ke/Makefile\n@@ -0,0 +1,36 @@\n+# SPDX-License-Identifier: BSD-3-Clause\n+# Copyright(c) 2019 Intel Corporation\n+\n+include $(RTE_SDK)/mk/rte.vars.mk\n+\n+#\n+# library name\n+#\n+LIB = librte_pmd_ipn3ke.a\n+\n+#\n+# Add the experimenatal APIs called from this PMD\n+# rte_eth_switch_domain_alloc()\n+# rte_eth_dev_create()\n+# rte_eth_dev_destroy()\n+# rte_eth_switch_domain_free()\n+#\n+CFLAGS += -DALLOW_EXPERIMENTAL_API\n+CFLAGS += -O3\n+CFLAGS += $(WERROR_FLAGS)\n+CFLAGS += -I$(RTE_SDK)/drivers/bus/ifpga\n+LDLIBS += -lrte_eal -lrte_mbuf -lrte_mempool -lrte_ring\n+LDLIBS += -lrte_ethdev -lrte_net -lrte_kvargs\n+LDLIBS += -lrte_bus_ifpga\n+LDLIBS += -lrte_bus_vdev\n+\n+EXPORT_MAP := rte_pmd_ipn3ke_version.map\n+\n+LIBABIVER := 1\n+\n+#\n+# all source are stored in SRCS-y\n+#\n+SRCS-$(CONFIG_RTE_LIBRTE_IPN3KE_PMD) += ipn3ke_ethdev.c\n+\n+include $(RTE_SDK)/mk/rte.lib.mk\ndiff --git a/drivers/net/ipn3ke/ipn3ke_ethdev.c b/drivers/net/ipn3ke/ipn3ke_ethdev.c\nnew file mode 100644\nindex 0000000..372ce80\n--- /dev/null\n+++ b/drivers/net/ipn3ke/ipn3ke_ethdev.c\n@@ -0,0 +1,707 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2019 Intel Corporation\n+ */\n+\n+#include <stdint.h>\n+\n+#include <rte_bus_pci.h>\n+#include <rte_ethdev.h>\n+#include <rte_pci.h>\n+#include <rte_malloc.h>\n+\n+#include <rte_mbuf.h>\n+#include <rte_sched.h>\n+#include <rte_ethdev_driver.h>\n+\n+#include <rte_io.h>\n+#include <rte_rawdev.h>\n+#include <rte_rawdev_pmd.h>\n+#include <rte_bus_ifpga.h>\n+#include <ifpga_common.h>\n+#include <ifpga_logs.h>\n+\n+#include \"ipn3ke_rawdev_api.h\"\n+#include \"ipn3ke_logs.h\"\n+#include \"ipn3ke_ethdev.h\"\n+\n+int ipn3ke_afu_logtype;\n+\n+static const struct rte_afu_uuid afu_uuid_ipn3ke_map[] = {\n+\t{ MAP_UUID_10G_LOW, MAP_UUID_10G_HIGH },\n+\t{ IPN3KE_UUID_10G_LOW, IPN3KE_UUID_10G_HIGH },\n+\t{ IPN3KE_UUID_VBNG_LOW, IPN3KE_UUID_VBNG_HIGH},\n+\t{ IPN3KE_UUID_25G_LOW, IPN3KE_UUID_25G_HIGH },\n+\t{ 0, 0 /* sentinel */ },\n+};\n+\n+static int ipn3ke_indirect_read(struct ipn3ke_hw *hw,\n+\t\t\t\t\t uint32_t *rd_data,\n+\t\t\t\t\t uint32_t addr,\n+\t\t\t\t\t uint32_t dev_sel,\n+\t\t\t\t\t uint32_t eth_group_sel)\n+{\n+\tuint32_t i, try_cnt;\n+\tuint64_t indirect_value;\n+\tvolatile void *indirect_addrs;\n+\tuint64_t target_addr;\n+\tuint64_t read_data = 0;\n+\n+\tif (eth_group_sel != 0 && eth_group_sel != 1)\n+\t\treturn -1;\n+\n+\taddr &= 0x3FF;\n+\ttarget_addr = addr | dev_sel << 17;\n+\n+\tindirect_value = RCMD | target_addr << 32;\n+\tindirect_addrs = (volatile void *)(hw->eth_group_bar[eth_group_sel] +\n+\t\t0x10);\n+\n+\trte_delay_us(10);\n+\n+\trte_write64((rte_cpu_to_le_64(indirect_value)), indirect_addrs);\n+\n+\ti = 0;\n+\ttry_cnt = 10;\n+\tindirect_addrs = (volatile void *)(hw->eth_group_bar[eth_group_sel] +\n+\t\t0x18);\n+\tdo {\n+\t\tread_data = rte_read64(indirect_addrs);\n+\t\tif ((read_data >> 32) == 1)\n+\t\t\tbreak;\n+\t\ti++;\n+\t} while (i <= try_cnt);\n+\tif (i > try_cnt)\n+\t\treturn -1;\n+\n+\t(*rd_data) = rte_le_to_cpu_32(read_data);\n+\treturn 0;\n+}\n+\n+static int ipn3ke_indirect_write(struct ipn3ke_hw *hw,\n+\t\t\t\t\t uint32_t wr_data,\n+\t\t\t\t\t uint32_t addr,\n+\t\t\t\t\t uint32_t dev_sel,\n+\t\t\t\t\t uint32_t eth_group_sel)\n+{\n+\tvolatile void *indirect_addrs;\n+\tuint64_t indirect_value;\n+\tuint64_t target_addr;\n+\n+\tif (eth_group_sel != 0 && eth_group_sel != 1)\n+\t\treturn -1;\n+\n+\taddr &= 0x3FF;\n+\ttarget_addr = addr | dev_sel << 17;\n+\n+\tindirect_value = WCMD | target_addr << 32 | wr_data;\n+\tindirect_addrs = (volatile void *)(hw->eth_group_bar[eth_group_sel] +\n+\t\t0x10);\n+\n+\trte_write64((rte_cpu_to_le_64(indirect_value)), indirect_addrs);\n+\treturn 0;\n+}\n+\n+static int ipn3ke_indirect_mac_read(struct ipn3ke_hw *hw,\n+\t\t\t\t\t\t uint32_t *rd_data,\n+\t\t\t\t\t\t uint32_t addr,\n+\t\t\t\t\t\t uint32_t mac_num,\n+\t\t\t\t\t\t uint32_t eth_group_sel)\n+{\n+\tuint32_t dev_sel;\n+\n+\tif (mac_num >= hw->port_num)\n+\t\treturn -1;\n+\n+\tmac_num &= 0x7;\n+\tdev_sel = mac_num * 2 + 3;\n+\n+\treturn ipn3ke_indirect_read(hw,\n+\t\t\t\trd_data,\n+\t\t\t\taddr,\n+\t\t\t\tdev_sel,\n+\t\t\t\teth_group_sel);\n+}\n+\n+static int ipn3ke_indirect_mac_write(struct ipn3ke_hw *hw,\n+\t\t\t\t\t\t uint32_t wr_data,\n+\t\t\t\t\t\t uint32_t addr,\n+\t\t\t\t\t\t uint32_t mac_num,\n+\t\t\t\t\t\t uint32_t eth_group_sel)\n+{\n+\tuint32_t dev_sel;\n+\n+\tif (mac_num >= hw->port_num)\n+\t\treturn -1;\n+\n+\tmac_num &= 0x7;\n+\tdev_sel = mac_num * 2 + 3;\n+\n+\treturn ipn3ke_indirect_write(hw,\n+\t\t\t\twr_data,\n+\t\t\t\taddr,\n+\t\t\t\tdev_sel,\n+\t\t\t\teth_group_sel);\n+}\n+\n+static int\n+ipn3ke_hw_cap_init(struct ipn3ke_hw *hw)\n+{\n+\thw->hw_cap.version_number = IPN3KE_MASK_READ_REG(hw,\n+\t\t\t(IPN3KE_HW_BASE + 0), 0, 0xFFFF);\n+\thw->hw_cap.capability_registers_block_offset = IPN3KE_MASK_READ_REG(hw,\n+\t\t\t(IPN3KE_HW_BASE + 0x8), 0, 0xFFFFFFFF);\n+\thw->hw_cap.status_registers_block_offset = IPN3KE_MASK_READ_REG(hw,\n+\t\t\t(IPN3KE_HW_BASE + 0x10), 0, 0xFFFFFFFF);\n+\thw->hw_cap.control_registers_block_offset = IPN3KE_MASK_READ_REG(hw,\n+\t\t\t(IPN3KE_HW_BASE + 0x18), 0, 0xFFFFFFFF);\n+\thw->hw_cap.classify_offset = IPN3KE_MASK_READ_REG(hw,\n+\t\t\t(IPN3KE_HW_BASE + 0x20), 0, 0xFFFFFFFF);\n+\thw->hw_cap.classy_size = IPN3KE_MASK_READ_REG(hw,\n+\t\t\t(IPN3KE_HW_BASE + 0x24), 0, 0xFFFF);\n+\thw->hw_cap.policer_offset = IPN3KE_MASK_READ_REG(hw,\n+\t\t\t(IPN3KE_HW_BASE + 0x28), 0, 0xFFFFFFFF);\n+\thw->hw_cap.policer_entry_size = IPN3KE_MASK_READ_REG(hw,\n+\t\t\t(IPN3KE_HW_BASE + 0x2C), 0, 0xFFFF);\n+\thw->hw_cap.rss_key_array_offset = IPN3KE_MASK_READ_REG(hw,\n+\t\t\t(IPN3KE_HW_BASE + 0x30), 0, 0xFFFFFFFF);\n+\thw->hw_cap.rss_key_entry_size = IPN3KE_MASK_READ_REG(hw,\n+\t\t\t(IPN3KE_HW_BASE + 0x34), 0, 0xFFFF);\n+\thw->hw_cap.rss_indirection_table_array_offset = IPN3KE_MASK_READ_REG(hw,\n+\t\t\t(IPN3KE_HW_BASE + 0x38), 0, 0xFFFFFFFF);\n+\thw->hw_cap.rss_indirection_table_entry_size = IPN3KE_MASK_READ_REG(hw,\n+\t\t\t(IPN3KE_HW_BASE + 0x3C), 0, 0xFFFF);\n+\thw->hw_cap.dmac_map_offset = IPN3KE_MASK_READ_REG(hw,\n+\t\t\t(IPN3KE_HW_BASE + 0x40), 0, 0xFFFFFFFF);\n+\thw->hw_cap.dmac_map_size = IPN3KE_MASK_READ_REG(hw,\n+\t\t\t(IPN3KE_HW_BASE + 0x44), 0, 0xFFFF);\n+\thw->hw_cap.qm_offset = IPN3KE_MASK_READ_REG(hw,\n+\t\t\t(IPN3KE_HW_BASE + 0x48), 0, 0xFFFFFFFF);\n+\thw->hw_cap.qm_size = IPN3KE_MASK_READ_REG(hw,\n+\t\t\t(IPN3KE_HW_BASE + 0x4C), 0, 0xFFFF);\n+\thw->hw_cap.ccb_offset = IPN3KE_MASK_READ_REG(hw,\n+\t\t\t(IPN3KE_HW_BASE + 0x50), 0, 0xFFFFFFFF);\n+\thw->hw_cap.ccb_entry_size = IPN3KE_MASK_READ_REG(hw,\n+\t\t\t(IPN3KE_HW_BASE + 0x54), 0, 0xFFFF);\n+\thw->hw_cap.qos_offset = IPN3KE_MASK_READ_REG(hw,\n+\t\t\t(IPN3KE_HW_BASE + 0x58), 0, 0xFFFFFFFF);\n+\thw->hw_cap.qos_size = IPN3KE_MASK_READ_REG(hw,\n+\t\t\t(IPN3KE_HW_BASE + 0x5C), 0, 0xFFFF);\n+\n+\thw->hw_cap.num_rx_flow = IPN3KE_MASK_READ_REG(hw,\n+\t\t\tIPN3KE_CAPABILITY_REGISTERS_BLOCK_OFFSET,\n+\t\t\t0, 0xFFFF);\n+\thw->hw_cap.num_rss_blocks = IPN3KE_MASK_READ_REG(hw,\n+\t\t\tIPN3KE_CAPABILITY_REGISTERS_BLOCK_OFFSET,\n+\t\t\t4, 0xFFFF);\n+\thw->hw_cap.num_dmac_map = IPN3KE_MASK_READ_REG(hw,\n+\t\t\tIPN3KE_CAPABILITY_REGISTERS_BLOCK_OFFSET,\n+\t\t\t8, 0xFFFF);\n+\thw->hw_cap.num_tx_flow = IPN3KE_MASK_READ_REG(hw,\n+\t\t\tIPN3KE_CAPABILITY_REGISTERS_BLOCK_OFFSET,\n+\t\t\t0xC, 0xFFFF);\n+\thw->hw_cap.num_smac_map = IPN3KE_MASK_READ_REG(hw,\n+\t\t\tIPN3KE_CAPABILITY_REGISTERS_BLOCK_OFFSET,\n+\t\t\t0x10, 0xFFFF);\n+\n+\thw->hw_cap.link_speed_mbps = IPN3KE_MASK_READ_REG(hw,\n+\t\t\tIPN3KE_STATUS_REGISTERS_BLOCK_OFFSET,\n+\t\t\t0, 0xFFFFF);\n+\n+\treturn 0;\n+}\n+\n+static int\n+ipn3ke_hw_init(struct rte_afu_device *afu_dev,\n+\tstruct ipn3ke_hw *hw)\n+{\n+\tstruct rte_rawdev *rawdev;\n+\tint ret;\n+\tint i;\n+\tuint32_t val;\n+\tuint64_t port_num, mac_type, index;\n+\n+\trawdev = afu_dev->rawdev;\n+\n+\thw->afu_id.uuid.uuid_low = afu_dev->id.uuid.uuid_low;\n+\thw->afu_id.uuid.uuid_high = afu_dev->id.uuid.uuid_high;\n+\thw->afu_id.port = afu_dev->id.port;\n+\thw->hw_addr = (uint8_t *)(afu_dev->mem_resource[0].addr);\n+\thw->f_mac_read = ipn3ke_indirect_mac_read;\n+\thw->f_mac_write = ipn3ke_indirect_mac_write;\n+\thw->rawdev = rawdev;\n+\trawdev->dev_ops->attr_get(rawdev,\n+\t\t\t\t\"LineSideBARIndex\", &index);\n+\thw->eth_group_bar[0] = (uint8_t *)(afu_dev->mem_resource[index].addr);\n+\trawdev->dev_ops->attr_get(rawdev,\n+\t\t\t\t\"NICSideBARIndex\", &index);\n+\thw->eth_group_bar[1] = (uint8_t *)(afu_dev->mem_resource[index].addr);\n+\trawdev->dev_ops->attr_get(rawdev,\n+\t\t\t\t\"LineSideLinkPortNum\", &port_num);\n+\thw->retimer.port_num = (int)port_num;\n+\thw->port_num = hw->retimer.port_num;\n+\trawdev->dev_ops->attr_get(rawdev,\n+\t\t\t\t\"LineSideMACType\", &mac_type);\n+\thw->retimer.mac_type = (int)mac_type;\n+\n+\tif (afu_dev->id.uuid.uuid_low == IPN3KE_UUID_VBNG_LOW &&\n+\t\tafu_dev->id.uuid.uuid_high == IPN3KE_UUID_VBNG_HIGH) {\n+\t\tipn3ke_hw_cap_init(hw);\n+\t\tIPN3KE_AFU_PMD_DEBUG(\"UPL_version is 0x%x\\n\",\n+\t\t\tIPN3KE_READ_REG(hw, 0));\n+\n+\t\t/* Reset FPGA IP */\n+\t\tIPN3KE_WRITE_REG(hw, IPN3KE_CTRL_RESET, 1);\n+\t\tIPN3KE_WRITE_REG(hw, IPN3KE_CTRL_RESET, 0);\n+\t}\n+\n+\tif (hw->retimer.mac_type == IFPGA_RAWDEV_RETIMER_MAC_TYPE_25GE_25GAUI) {\n+\t} else {\n+\t\t/* Enable inter connect channel */\n+\t\tfor (i = 0; i < hw->port_num; i++) {\n+\t\t\t/* Enable the TX path */\n+\t\t\tval = 0;\n+\t\t\tval &= IPN3KE_MAC_TX_PACKET_CONTROL_MASK;\n+\t\t\t(*hw->f_mac_write)(hw,\n+\t\t\t\t\tval,\n+\t\t\t\t\tIPN3KE_MAC_TX_PACKET_CONTROL,\n+\t\t\t\t\ti,\n+\t\t\t\t\t1);\n+\n+\t\t\t/* Disables source address override */\n+\t\t\tval = 0;\n+\t\t\tval &= IPN3KE_MAC_TX_SRC_ADDR_OVERRIDE_MASK;\n+\t\t\t(*hw->f_mac_write)(hw,\n+\t\t\t\t\tval,\n+\t\t\t\t\tIPN3KE_MAC_TX_SRC_ADDR_OVERRIDE,\n+\t\t\t\t\ti,\n+\t\t\t\t\t1);\n+\n+\t\t\t/* Enable the RX path */\n+\t\t\tval = 0;\n+\t\t\tval &= IPN3KE_MAC_RX_TRANSFER_CONTROL_MASK;\n+\t\t\t(*hw->f_mac_write)(hw,\n+\t\t\t\t\tval,\n+\t\t\t\t\tIPN3KE_MAC_RX_TRANSFER_CONTROL,\n+\t\t\t\t\ti,\n+\t\t\t\t\t1);\n+\n+\t\t\t/* Clear all TX statistics counters */\n+\t\t\tval = 1;\n+\t\t\tval &= IPN3KE_MAC_TX_STATS_CLR_CLEAR_MASK;\n+\t\t\t(*hw->f_mac_write)(hw,\n+\t\t\t\t\tval,\n+\t\t\t\t\tIPN3KE_MAC_TX_STATS_CLR,\n+\t\t\t\t\ti,\n+\t\t\t\t\t1);\n+\n+\t\t\t/* Clear all RX statistics counters */\n+\t\t\tval = 1;\n+\t\t\tval &= IPN3KE_MAC_RX_STATS_CLR_CLEAR_MASK;\n+\t\t\t(*hw->f_mac_write)(hw,\n+\t\t\t\t\tval,\n+\t\t\t\t\tIPN3KE_MAC_RX_STATS_CLR,\n+\t\t\t\t\ti,\n+\t\t\t\t\t1);\n+\t\t}\n+\t}\n+\n+\tret = rte_eth_switch_domain_alloc(&hw->switch_domain_id);\n+\tif (ret)\n+\t\tIPN3KE_AFU_PMD_WARN(\"failed to allocate switch domain for device %d\",\n+\t\tret);\n+\n+\thw->tm_hw_enable = 0;\n+\thw->flow_hw_enable = 0;\n+\tif (afu_dev->id.uuid.uuid_low == IPN3KE_UUID_VBNG_LOW &&\n+\t\tafu_dev->id.uuid.uuid_high == IPN3KE_UUID_VBNG_HIGH) {\n+\t\thw->tm_hw_enable = 1;\n+\t}\n+\n+\thw->acc_tm = 0;\n+\thw->acc_flow = 0;\n+\n+\treturn 0;\n+}\n+\n+static void\n+ipn3ke_hw_uninit(struct ipn3ke_hw *hw)\n+{\n+\tint i;\n+\tuint32_t val;\n+\n+\tif (hw->retimer.mac_type == IFPGA_RAWDEV_RETIMER_MAC_TYPE_25GE_25GAUI) {\n+\t} else {\n+\t\tfor (i = 0; i < hw->port_num; i++) {\n+\t\t\t/* Disable the TX path */\n+\t\t\tval = 1;\n+\t\t\tval &= IPN3KE_MAC_TX_PACKET_CONTROL_MASK;\n+\t\t\t(*hw->f_mac_write)(hw,\n+\t\t\t\t\tval,\n+\t\t\t\t\tIPN3KE_MAC_TX_PACKET_CONTROL,\n+\t\t\t\t\t0,\n+\t\t\t\t\t1);\n+\n+\t\t\t/* Disable the RX path */\n+\t\t\tval = 1;\n+\t\t\tval &= IPN3KE_MAC_RX_TRANSFER_CONTROL_MASK;\n+\t\t\t(*hw->f_mac_write)(hw,\n+\t\t\t\t\tval,\n+\t\t\t\t\tIPN3KE_MAC_RX_TRANSFER_CONTROL,\n+\t\t\t\t\t0,\n+\t\t\t\t\t1);\n+\n+\t\t\t/* Clear all TX statistics counters */\n+\t\t\tval = 1;\n+\t\t\tval &= IPN3KE_MAC_TX_STATS_CLR_CLEAR_MASK;\n+\t\t\t(*hw->f_mac_write)(hw,\n+\t\t\t\t\tval,\n+\t\t\t\t\tIPN3KE_MAC_TX_STATS_CLR,\n+\t\t\t\t\t0,\n+\t\t\t\t\t1);\n+\n+\t\t\t/* Clear all RX statistics counters */\n+\t\t\tval = 1;\n+\t\t\tval &= IPN3KE_MAC_RX_STATS_CLR_CLEAR_MASK;\n+\t\t\t(*hw->f_mac_write)(hw,\n+\t\t\t\t\tval,\n+\t\t\t\t\tIPN3KE_MAC_RX_STATS_CLR,\n+\t\t\t\t\t0,\n+\t\t\t\t\t1);\n+\t\t}\n+\t}\n+}\n+\n+static int ipn3ke_vswitch_probe(struct rte_afu_device *afu_dev)\n+{\n+\tchar name[RTE_ETH_NAME_MAX_LEN];\n+\tstruct ipn3ke_hw *hw;\n+\tint i, retval;\n+\n+\t/* check if the AFU device has been probed already */\n+\t/* allocate shared mcp_vswitch structure */\n+\tif (!afu_dev->shared.data) {\n+\t\tsnprintf(name, sizeof(name), \"net_%s_hw\",\n+\t\t\tafu_dev->device.name);\n+\t\thw = rte_zmalloc_socket(name,\n+\t\t\t\t\tsizeof(struct ipn3ke_hw),\n+\t\t\t\t\tRTE_CACHE_LINE_SIZE,\n+\t\t\t\t\tafu_dev->device.numa_node);\n+\t\tif (!hw) {\n+\t\t\tIPN3KE_AFU_PMD_ERR(\"failed to allocate hardwart data\");\n+\t\t\t\tretval = -ENOMEM;\n+\t\t\t\treturn -ENOMEM;\n+\t\t}\n+\t\tafu_dev->shared.data = hw;\n+\n+\t\trte_spinlock_init(&afu_dev->shared.lock);\n+\t} else {\n+\t\thw = (struct ipn3ke_hw *)afu_dev->shared.data;\n+\t}\n+\n+\tretval = ipn3ke_hw_init(afu_dev, hw);\n+\tif (retval)\n+\t\treturn retval;\n+\n+\t/* probe representor ports */\n+\tfor (i = 0; i < hw->port_num; i++) {\n+\t\t/* representor port net_bdf_port */\n+\t\tsnprintf(name, sizeof(name), \"net_%s_representor_%d\",\n+\t\t\tafu_dev->device.name, i);\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int ipn3ke_vswitch_remove(struct rte_afu_device *afu_dev)\n+{\n+\tchar name[RTE_ETH_NAME_MAX_LEN];\n+\tstruct ipn3ke_hw *hw;\n+\tstruct rte_eth_dev *ethdev;\n+\tint i, ret;\n+\n+\thw = (struct ipn3ke_hw *)afu_dev->shared.data;\n+\n+\t/* remove representor ports */\n+\tfor (i = 0; i < hw->port_num; i++) {\n+\t\t/* representor port net_bdf_port */\n+\t\tsnprintf(name, sizeof(name), \"net_%s_representor_%d\",\n+\t\t\tafu_dev->device.name, i);\n+\n+\t\tethdev = rte_eth_dev_allocated(afu_dev->device.name);\n+\t\tif (!ethdev)\n+\t\t\treturn -ENODEV;\n+\t}\n+\n+\tret = rte_eth_switch_domain_free(hw->switch_domain_id);\n+\tif (ret)\n+\t\tIPN3KE_AFU_PMD_WARN(\"failed to free switch domain: %d\", ret);\n+\n+\t/* hw uninit*/\n+\tipn3ke_hw_uninit(hw);\n+\n+\treturn 0;\n+}\n+\n+static struct rte_afu_driver afu_ipn3ke_driver = {\n+\t.id_table = afu_uuid_ipn3ke_map,\n+\t.probe = ipn3ke_vswitch_probe,\n+\t.remove = ipn3ke_vswitch_remove,\n+};\n+\n+RTE_PMD_REGISTER_AFU(net_ipn3ke_afu, afu_ipn3ke_driver);\n+\n+static const char * const valid_args[] = {\n+#define IPN3KE_AFU_NAME \"afu\"\n+\t\tIPN3KE_AFU_NAME,\n+#define IPN3KE_FPGA_ACCELERATION_LIST \"fpga_acc\"\n+\t\tIPN3KE_FPGA_ACCELERATION_LIST,\n+#define IPN3KE_I40E_PF_LIST \"i40e_pf\"\n+\t\tIPN3KE_I40E_PF_LIST,\n+\t\tNULL\n+};\n+static int\n+ipn3ke_cfg_parse_acc_list(const char *afu_name,\n+\tconst char *acc_list_name)\n+{\n+\tstruct rte_afu_device *afu_dev;\n+\tstruct ipn3ke_hw *hw;\n+\tconst char *p_source;\n+\tchar *p_start;\n+\tchar name[RTE_ETH_NAME_MAX_LEN];\n+\n+\tafu_dev = rte_ifpga_find_afu_by_name(afu_name);\n+\tif (!afu_dev)\n+\t\treturn -1;\n+\thw = (struct ipn3ke_hw *)afu_dev->shared.data;\n+\tif (!hw)\n+\t\treturn -1;\n+\n+\tp_source = acc_list_name;\n+\twhile (*p_source) {\n+\t\twhile ((*p_source == '{') || (*p_source == '|'))\n+\t\t\tp_source++;\n+\t\tp_start = name;\n+\t\twhile ((*p_source != '|') && (*p_source != '}'))\n+\t\t\t*p_start++ = *p_source++;\n+\t\t*p_start = 0;\n+\t\tif (!strcmp(name, \"tm\") && hw->tm_hw_enable)\n+\t\t\thw->acc_tm = 1;\n+\n+\t\tif (!strcmp(name, \"flow\") && hw->flow_hw_enable)\n+\t\t\thw->acc_flow = 1;\n+\n+\t\tif (*p_source == '}')\n+\t\t\treturn 0;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int\n+ipn3ke_cfg_parse_i40e_pf_ethdev(const char *afu_name,\n+const char *pf_name)\n+{\n+\tstruct rte_eth_dev *i40e_eth, *rpst_eth;\n+\tstruct rte_afu_device *afu_dev;\n+\tstruct ipn3ke_rpst *rpst;\n+\tstruct ipn3ke_hw *hw;\n+\tconst char *p_source;\n+\tchar *p_start;\n+\tchar name[RTE_ETH_NAME_MAX_LEN];\n+\tuint16_t port_id;\n+\tint i;\n+\tint ret = -1;\n+\n+\tafu_dev = rte_ifpga_find_afu_by_name(afu_name);\n+\tif (!afu_dev)\n+\t\treturn -1;\n+\thw = (struct ipn3ke_hw *)afu_dev->shared.data;\n+\tif (!hw)\n+\t\treturn -1;\n+\n+\tp_source = pf_name;\n+\tfor (i = 0; i < hw->port_num; i++) {\n+\t\tsnprintf(name, sizeof(name), \"net_%s_representor_%d\",\n+\t\t\tafu_name, i);\n+\t\tret = rte_eth_dev_get_port_by_name(name, &port_id);\n+\t\tif (ret)\n+\t\t\treturn -1;\n+\t\trpst_eth = &rte_eth_devices[port_id];\n+\t\trpst = IPN3KE_DEV_PRIVATE_TO_RPST(rpst_eth);\n+\n+\t\twhile ((*p_source == '{') || (*p_source == '|'))\n+\t\t\tp_source++;\n+\t\tp_start = name;\n+\t\twhile ((*p_source != '|') && (*p_source != '}'))\n+\t\t\t*p_start++ = *p_source++;\n+\t\t*p_start = 0;\n+\n+\t\tret = rte_eth_dev_get_port_by_name(name, &port_id);\n+\t\tif (ret)\n+\t\t\treturn -1;\n+\t\ti40e_eth = &rte_eth_devices[port_id];\n+\n+\t\trpst->i40e_pf_eth = i40e_eth;\n+\t\trpst->i40e_pf_eth_port_id = port_id;\n+\n+\t\tif ((*p_source == '}') || !(*p_source))\n+\t\t\tbreak;\n+\t}\n+\n+\treturn 0;\n+}\n+static int\n+ipn3ke_cfg_probe(struct rte_vdev_device *dev)\n+{\n+\tstruct rte_devargs *devargs;\n+\tstruct rte_kvargs *kvlist = NULL;\n+\tchar *afu_name = NULL;\n+\tchar *acc_name = NULL;\n+\tchar *pf_name = NULL;\n+\tint afu_name_en = 0;\n+\tint acc_list_en = 0;\n+\tint pf_list_en = 0;\n+\tint ret = -1;\n+\n+\tdevargs = dev->device.devargs;\n+\n+\tkvlist = rte_kvargs_parse(devargs->args, valid_args);\n+\tif (!kvlist) {\n+\t\tIPN3KE_AFU_PMD_ERR(\"error when parsing param\");\n+\t\tgoto end;\n+\t}\n+\n+\tif (rte_kvargs_count(kvlist, IPN3KE_AFU_NAME) == 1) {\n+\t\tif (rte_kvargs_process(kvlist, IPN3KE_AFU_NAME,\n+\t\t\t\t &rte_ifpga_get_string_arg,\n+\t\t\t\t &afu_name) < 0) {\n+\t\t\tIPN3KE_AFU_PMD_ERR(\"error to parse %s\",\n+\t\t\t\t IPN3KE_AFU_NAME);\n+\t\t\tgoto end;\n+\t\t} else {\n+\t\t\tafu_name_en = 1;\n+\t\t}\n+\t}\n+\n+\tif (rte_kvargs_count(kvlist, IPN3KE_FPGA_ACCELERATION_LIST) == 1) {\n+\t\tif (rte_kvargs_process(kvlist, IPN3KE_FPGA_ACCELERATION_LIST,\n+\t\t\t\t &rte_ifpga_get_string_arg,\n+\t\t\t\t &acc_name) < 0) {\n+\t\t\tIPN3KE_AFU_PMD_ERR(\"error to parse %s\",\n+\t\t\t\t IPN3KE_FPGA_ACCELERATION_LIST);\n+\t\t\tgoto end;\n+\t\t} else {\n+\t\t\tacc_list_en = 1;\n+\t\t}\n+\t}\n+\n+\tif (rte_kvargs_count(kvlist, IPN3KE_I40E_PF_LIST) == 1) {\n+\t\tif (rte_kvargs_process(kvlist, IPN3KE_I40E_PF_LIST,\n+\t\t\t\t &rte_ifpga_get_string_arg,\n+\t\t\t\t &pf_name) < 0) {\n+\t\t\tIPN3KE_AFU_PMD_ERR(\"error to parse %s\",\n+\t\t\t\t IPN3KE_I40E_PF_LIST);\n+\t\t\tgoto end;\n+\t\t} else {\n+\t\t\tpf_list_en = 1;\n+\t\t}\n+\t}\n+\n+\tif (!afu_name_en) {\n+\t\tIPN3KE_AFU_PMD_ERR(\"arg %s is mandatory for ipn3ke\",\n+\t\t\t IPN3KE_AFU_NAME);\n+\t\tgoto end;\n+\t}\n+\n+\tif (!pf_list_en) {\n+\t\tIPN3KE_AFU_PMD_ERR(\"arg %s is mandatory for ipn3ke\",\n+\t\t\t IPN3KE_I40E_PF_LIST);\n+\t\tgoto end;\n+\t}\n+\n+\tif (acc_list_en) {\n+\t\tret = ipn3ke_cfg_parse_acc_list(afu_name, acc_name);\n+\t\tif (ret) {\n+\t\t\tIPN3KE_AFU_PMD_ERR(\"arg %s parse error for ipn3ke\",\n+\t\t\t IPN3KE_FPGA_ACCELERATION_LIST);\n+\t\t\tgoto end;\n+\t\t}\n+\t} else {\n+\t\tIPN3KE_AFU_PMD_INFO(\"arg %s is optional for ipn3ke, using i40e acc\",\n+\t\t\t IPN3KE_FPGA_ACCELERATION_LIST);\n+\t}\n+\n+\tret = ipn3ke_cfg_parse_i40e_pf_ethdev(afu_name, pf_name);\n+\tif (ret)\n+\t\tgoto end;\n+end:\n+\tif (kvlist)\n+\t\trte_kvargs_free(kvlist);\n+\tif (afu_name)\n+\t\tfree(afu_name);\n+\tif (acc_name)\n+\t\tfree(acc_name);\n+\n+\treturn ret;\n+}\n+\n+static int\n+ipn3ke_cfg_remove(struct rte_vdev_device *dev)\n+{\n+\tstruct rte_devargs *devargs;\n+\tstruct rte_kvargs *kvlist = NULL;\n+\tchar *afu_name = NULL;\n+\tstruct rte_afu_device *afu_dev;\n+\tint ret = -1;\n+\n+\tdevargs = dev->device.devargs;\n+\n+\tkvlist = rte_kvargs_parse(devargs->args, valid_args);\n+\tif (!kvlist) {\n+\t\tIPN3KE_AFU_PMD_ERR(\"error when parsing param\");\n+\t\tgoto end;\n+\t}\n+\n+\tif (rte_kvargs_count(kvlist, IPN3KE_AFU_NAME) == 1) {\n+\t\tif (rte_kvargs_process(kvlist, IPN3KE_AFU_NAME,\n+\t\t\t\t &rte_ifpga_get_string_arg,\n+\t\t\t\t &afu_name) < 0) {\n+\t\t\tIPN3KE_AFU_PMD_ERR(\"error to parse %s\",\n+\t\t\t\t IPN3KE_AFU_NAME);\n+\t\t} else {\n+\t\t\tafu_dev = rte_ifpga_find_afu_by_name(afu_name);\n+\t\t\tif (!afu_dev)\n+\t\t\t\tgoto end;\n+\t\t\tret = ipn3ke_vswitch_remove(afu_dev);\n+\t\t}\n+\t} else {\n+\t\tIPN3KE_AFU_PMD_ERR(\"Remove ipn3ke_cfg %p error\", dev);\n+\t}\n+\n+end:\n+\tif (kvlist)\n+\t\trte_kvargs_free(kvlist);\n+\n+\treturn ret;\n+}\n+\n+static struct rte_vdev_driver ipn3ke_cfg_driver = {\n+\t.probe = ipn3ke_cfg_probe,\n+\t.remove = ipn3ke_cfg_remove,\n+};\n+\n+RTE_PMD_REGISTER_VDEV(ipn3ke_cfg, ipn3ke_cfg_driver);\n+RTE_PMD_REGISTER_ALIAS(ipn3ke_cfg, ipn3ke_cfg);\n+RTE_PMD_REGISTER_PARAM_STRING(ipn3ke_cfg,\n+\t\"afu=<string> \"\n+\t\"fpga_acc=<string>\"\n+\t\"i40e_pf=<string>\");\n+\n+RTE_INIT(ipn3ke_afu_init_log);\n+static void\n+ipn3ke_afu_init_log(void)\n+{\n+\tipn3ke_afu_logtype = rte_log_register(\"driver.afu.ipn3ke\");\n+\tif (ipn3ke_afu_logtype >= 0)\n+\t\trte_log_set_level(ipn3ke_afu_logtype, RTE_LOG_NOTICE);\n+}\ndiff --git a/drivers/net/ipn3ke/ipn3ke_ethdev.h b/drivers/net/ipn3ke/ipn3ke_ethdev.h\nnew file mode 100644\nindex 0000000..3baa9fe\n--- /dev/null\n+++ b/drivers/net/ipn3ke/ipn3ke_ethdev.h\n@@ -0,0 +1,891 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2019 Intel Corporation\n+ */\n+\n+#ifndef _IPN3KE_ETHDEV_H_\n+#define _IPN3KE_ETHDEV_H_\n+\n+#include <stdbool.h>\n+#include <stddef.h>\n+#include <stdint.h>\n+#include <limits.h>\n+#include <net/if.h>\n+#include <netinet/in.h>\n+#include <sys/queue.h>\n+\n+#include <rte_mbuf.h>\n+#include <rte_flow_driver.h>\n+#include <rte_ethdev_driver.h>\n+#include <rte_ethdev_vdev.h>\n+#include <rte_malloc.h>\n+#include <rte_memcpy.h>\n+#include <rte_bus_vdev.h>\n+#include <rte_kvargs.h>\n+#include <rte_spinlock.h>\n+\n+#include <rte_cycles.h>\n+#include <rte_bus_ifpga.h>\n+#include <rte_tm_driver.h>\n+\n+struct ipn3ke_rpst;\n+\n+#define IPN3KE_TM_SCRATCH_RW 0\n+\n+/* TM Levels */\n+enum ipn3ke_tm_node_level {\n+\tIPN3KE_TM_NODE_LEVEL_PORT,\n+\tIPN3KE_TM_NODE_LEVEL_VT,\n+\tIPN3KE_TM_NODE_LEVEL_COS,\n+\tIPN3KE_TM_NODE_LEVEL_MAX,\n+};\n+\n+/* TM Shaper Profile */\n+struct ipn3ke_tm_shaper_profile {\n+\tuint32_t valid;\n+\tuint32_t m;\n+\tuint32_t e;\n+\tuint64_t rate;\n+\tstruct rte_tm_shaper_params params;\n+};\n+\n+TAILQ_HEAD(ipn3ke_tm_shaper_profile_list, ipn3ke_tm_shaper_profile);\n+\n+\n+#define IPN3KE_TDROP_TH1_MASK 0x1ffffff\n+#define IPN3KE_TDROP_TH1_SHIFT (25)\n+#define IPN3KE_TDROP_TH2_MASK 0x1ffffff\n+\n+/* TM TDROP Profile */\n+struct ipn3ke_tm_tdrop_profile {\n+\tuint32_t tdrop_profile_id;\n+\tuint32_t th1;\n+\tuint32_t th2;\n+\tuint32_t n_users;\n+\tuint32_t valid;\n+\tstruct rte_tm_wred_params params;\n+};\n+\n+/* TM node priority */\n+enum ipn3ke_tm_node_state {\n+\tIPN3KE_TM_NODE_STATE_IDLE = 0,\n+\tIPN3KE_TM_NODE_STATE_CONFIGURED_ADD,\n+\tIPN3KE_TM_NODE_STATE_CONFIGURED_DEL,\n+\tIPN3KE_TM_NODE_STATE_COMMITTED,\n+\tIPN3KE_TM_NODE_STATE_MAX,\n+};\n+\n+TAILQ_HEAD(ipn3ke_tm_node_list, ipn3ke_tm_node);\n+\n+/* IPN3KE TM Node */\n+struct ipn3ke_tm_node {\n+\tTAILQ_ENTRY(ipn3ke_tm_node) node;\n+\tuint32_t node_index;\n+\tuint32_t level;\n+\tuint32_t tm_id;\n+\tenum ipn3ke_tm_node_state node_state;\n+\tuint32_t parent_node_id;\n+\tuint32_t priority;\n+\tuint32_t weight;\n+\tstruct ipn3ke_tm_node *parent_node;\n+\tstruct ipn3ke_tm_shaper_profile shaper_profile;\n+\tstruct ipn3ke_tm_tdrop_profile *tdrop_profile;\n+\tstruct rte_tm_node_params params;\n+\tstruct rte_tm_node_stats stats;\n+\tuint32_t n_children;\n+\tstruct ipn3ke_tm_node_list children_node_list;\n+};\n+\n+/* IPN3KE TM Hierarchy Specification */\n+struct ipn3ke_tm_hierarchy {\n+\tstruct ipn3ke_tm_node *port_node;\n+\t/*struct ipn3ke_tm_node_list vt_node_list;*/\n+\t/*struct ipn3ke_tm_node_list cos_node_list;*/\n+\n+\tuint32_t n_shaper_profiles;\n+\t/*uint32_t n_shared_shapers;*/\n+\tuint32_t n_tdrop_profiles;\n+\tuint32_t n_vt_nodes;\n+\tuint32_t n_cos_nodes;\n+\n+\tstruct ipn3ke_tm_node *port_commit_node;\n+\tstruct ipn3ke_tm_node_list vt_commit_node_list;\n+\tstruct ipn3ke_tm_node_list cos_commit_node_list;\n+\n+\t/*uint32_t n_tm_nodes[IPN3KE_TM_NODE_LEVEL_MAX];*/\n+};\n+\n+struct ipn3ke_tm_internals {\n+\t/** Hierarchy specification\n+\t *\n+\t * -Hierarchy is unfrozen at init and when port is stopped.\n+\t * -Hierarchy is frozen on successful hierarchy commit.\n+\t * -Run-time hierarchy changes are not allowed, therefore it makes\n+\t * sense to keep the hierarchy frozen after the port is started.\n+\t */\n+\tstruct ipn3ke_tm_hierarchy h;\n+\tint hierarchy_frozen;\n+\tint tm_started;\n+\tuint32_t tm_id;\n+};\n+\n+#define IPN3KE_TM_COS_NODE_NUM (64 * 1024)\n+#define IPN3KE_TM_VT_NODE_NUM (IPN3KE_TM_COS_NODE_NUM / 8)\n+#define IPN3KE_TM_10G_PORT_NODE_NUM (8)\n+#define IPN3KE_TM_25G_PORT_NODE_NUM (4)\n+\n+#define IPN3KE_TM_NODE_LEVEL_MOD (100000)\n+#define IPN3KE_TM_NODE_MOUNT_MAX (8)\n+\n+#define IPN3KE_TM_TDROP_PROFILE_NUM (2 * 1024)\n+\n+/* TM node priority */\n+enum ipn3ke_tm_node_priority {\n+\tIPN3KE_TM_NODE_PRIORITY_NORMAL0 = 0,\n+\tIPN3KE_TM_NODE_PRIORITY_LOW,\n+\tIPN3KE_TM_NODE_PRIORITY_NORMAL1,\n+\tIPN3KE_TM_NODE_PRIORITY_HIGHEST,\n+};\n+\n+#define IPN3KE_TM_NODE_WEIGHT_MAX UINT8_MAX\n+\n+/** Set a bit in the uint32 variable */\n+#define IPN3KE_BIT_SET(var, pos) \\\n+\t((var) |= ((uint32_t)1 << ((pos))))\n+\n+/** Reset the bit in the variable */\n+#define IPN3KE_BIT_RESET(var, pos) \\\n+\t((var) &= ~((uint32_t)1 << ((pos))))\n+\n+/** Check the bit is set in the variable */\n+#define IPN3KE_BIT_ISSET(var, pos) \\\n+\t(((var) & ((uint32_t)1 << ((pos)))) ? 1 : 0)\n+\n+struct ipn3ke_hw;\n+\n+#define IPN3KE_HW_BASE 0x4000000\n+\n+#define IPN3KE_CAPABILITY_REGISTERS_BLOCK_OFFSET \\\n+\t(IPN3KE_HW_BASE + hw->hw_cap.capability_registers_block_offset)\n+\n+#define IPN3KE_STATUS_REGISTERS_BLOCK_OFFSET \\\n+\t(IPN3KE_HW_BASE + hw->hw_cap.status_registers_block_offset)\n+\n+#define IPN3KE_CTRL_RESET \\\n+\t(IPN3KE_HW_BASE + hw->hw_cap.control_registers_block_offset)\n+\n+#define IPN3KE_CTRL_MTU \\\n+\t(IPN3KE_HW_BASE + hw->hw_cap.control_registers_block_offset + 4)\n+\n+#define IPN3KE_CLASSIFY_OFFSET \\\n+\t(IPN3KE_HW_BASE + hw->hw_cap.classify_offset)\n+\n+#define IPN3KE_POLICER_OFFSET \\\n+\t(IPN3KE_HW_BASE + hw->hw_cap.policer_offset)\n+\n+#define IPN3KE_RSS_KEY_ARRAY_OFFSET \\\n+\t(IPN3KE_HW_BASE + hw->hw_cap.rss_key_array_offset)\n+\n+#define IPN3KE_RSS_INDIRECTION_TABLE_ARRAY_OFFSET \\\n+\t(IPN3KE_HW_BASE + hw->hw_cap.rss_indirection_table_array_offset)\n+\n+#define IPN3KE_DMAC_MAP_OFFSET \\\n+\t(IPN3KE_HW_BASE + hw->hw_cap.dmac_map_offset)\n+\n+#define IPN3KE_QM_OFFSET \\\n+\t(IPN3KE_HW_BASE + hw->hw_cap.qm_offset)\n+\n+#define IPN3KE_CCB_OFFSET \\\n+\t(IPN3KE_HW_BASE + hw->hw_cap.ccb_offset)\n+\n+#define IPN3KE_QOS_OFFSET \\\n+\t(IPN3KE_HW_BASE + hw->hw_cap.qos_offset)\n+\n+struct ipn3ke_hw_cap {\n+\tuint32_t version_number;\n+\tuint32_t capability_registers_block_offset;\n+\tuint32_t status_registers_block_offset;\n+\tuint32_t control_registers_block_offset;\n+\tuint32_t classify_offset;\n+\tuint32_t classy_size;\n+\tuint32_t policer_offset;\n+\tuint32_t policer_entry_size;\n+\tuint32_t rss_key_array_offset;\n+\tuint32_t rss_key_entry_size;\n+\tuint32_t rss_indirection_table_array_offset;\n+\tuint32_t rss_indirection_table_entry_size;\n+\tuint32_t dmac_map_offset;\n+\tuint32_t dmac_map_size;\n+\tuint32_t qm_offset;\n+\tuint32_t qm_size;\n+\tuint32_t ccb_offset;\n+\tuint32_t ccb_entry_size;\n+\tuint32_t qos_offset;\n+\tuint32_t qos_size;\n+\n+\tuint32_t num_rx_flow; /* Default: 64K */\n+\tuint32_t num_rss_blocks; /* Default: 512 */\n+\tuint32_t num_dmac_map; /* Default: 1K */\n+\tuint32_t num_tx_flow; /* Default: 64K */\n+\tuint32_t num_smac_map; /* Default: 1K */\n+\n+\tuint32_t link_speed_mbps;\n+};\n+\n+/**\n+ * Strucute to store private data for each representor instance\n+ */\n+struct ipn3ke_rpst {\n+\tTAILQ_ENTRY(ipn3ke_rpst) next; /**< Next in device list. */\n+\tuint16_t switch_domain_id;\n+\t/**< Switch ID */\n+\tuint16_t port_id;\n+\tstruct rte_eth_dev *ethdev;\n+\t/**< Port ID */\n+\tstruct ipn3ke_hw *hw;\n+\tstruct rte_eth_dev *i40e_pf_eth;\n+\tuint16_t i40e_pf_eth_port_id;\n+\tstruct rte_eth_link ori_linfo;\n+\tstruct ipn3ke_tm_internals tm;\n+\t/**< Private data store of assocaiated physical function */\n+\tstruct ether_addr mac_addr;\n+};\n+\n+/* UUID IDs */\n+#define MAP_UUID_10G_LOW 0xffffffffffffffff\n+#define MAP_UUID_10G_HIGH 0xffffffffffffffff\n+#define IPN3KE_UUID_10G_LOW 0xc000c9660d824272\n+#define IPN3KE_UUID_10G_HIGH 0x9aeffe5f84570612\n+#define IPN3KE_UUID_VBNG_LOW\t\t0x8991165349d23ff9\n+#define IPN3KE_UUID_VBNG_HIGH\t\t0xb74cf419d15a481f\n+#define IPN3KE_UUID_25G_LOW 0xb7d9bac566bfbc80\n+#define IPN3KE_UUID_25G_HIGH 0xb07bac1aeef54d67\n+\n+#define IPN3KE_AFU_BUF_SIZE_MIN 1024\n+#define IPN3KE_AFU_FRAME_SIZE_MAX 9728\n+\n+#define IPN3KE_RAWDEV_ATTR_LEN_MAX (64)\n+\n+typedef int (*ipn3ke_indirect_mac_read_t)(struct ipn3ke_hw *hw,\n+\t\t\t\t uint32_t *rd_data,\n+\t\t\t\t uint32_t addr,\n+\t\t\t\t uint32_t mac_num,\n+\t\t\t\t uint32_t eth_wrapper_sel);\n+\n+typedef int (*ipn3ke_indirect_mac_write_t)(struct ipn3ke_hw *hw,\n+\t\t\t\t uint32_t wr_data,\n+\t\t\t\t uint32_t addr,\n+\t\t\t\t uint32_t mac_num,\n+\t\t\t\t uint32_t eth_wrapper_sel);\n+\n+struct ipn3ke_hw {\n+\tstruct rte_eth_dev *eth_dev;\n+\n+\t/* afu info */\n+\tstruct rte_afu_id afu_id;\n+\tstruct rte_rawdev *rawdev;\n+\n+\tstruct ipn3ke_hw_cap hw_cap;\n+\n+\tstruct ifpga_rawdevg_retimer_info retimer;\n+\n+\tuint16_t switch_domain_id;\n+\tuint16_t port_num;\n+\n+\tuint32_t tm_hw_enable;\n+\tuint32_t flow_hw_enable;\n+\n+\tuint32_t acc_tm;\n+\tuint32_t acc_flow;\n+\n+\tuint32_t flow_max_entries;\n+\tuint32_t flow_num_entries;\n+\n+\tstruct ipn3ke_tm_node *nodes;\n+\tstruct ipn3ke_tm_node *port_nodes;\n+\tstruct ipn3ke_tm_node *vt_nodes;\n+\tstruct ipn3ke_tm_node *cos_nodes;\n+\n+\tstruct ipn3ke_tm_tdrop_profile *tdrop_profile;\n+\tuint32_t tdrop_profile_num;\n+\n+\tuint32_t ccb_status;\n+\tuint32_t ccb_seg_free;\n+\tuint32_t ccb_seg_num;\n+\tuint32_t ccb_seg_k;\n+\n+\tuint8_t *eth_group_bar[2];\n+\t/**< MAC Register read */\n+\tipn3ke_indirect_mac_read_t f_mac_read;\n+\t/**< MAC Register write */\n+\tipn3ke_indirect_mac_write_t f_mac_write;\n+\n+\tuint8_t *hw_addr;\n+};\n+\n+/**\n+ * @internal\n+ * Helper macro for drivers that need to convert to struct rte_afu_device.\n+ */\n+#define RTE_DEV_TO_AFU(ptr) \\\n+\tcontainer_of(ptr, struct rte_afu_device, device)\n+\n+#define RTE_DEV_TO_AFU_CONST(ptr) \\\n+\tcontainer_of(ptr, const struct rte_afu_device, device)\n+\n+#define RTE_ETH_DEV_TO_AFU(eth_dev) \\\n+\tRTE_DEV_TO_AFU((eth_dev)->device)\n+\n+/**\n+ * PCIe MMIO Access\n+ */\n+\n+#define IPN3KE_PCI_REG(reg) rte_read32(reg)\n+#define IPN3KE_PCI_REG_ADDR(a, reg) \\\n+\t((volatile uint32_t *)((char *)(a)->hw_addr + (reg)))\n+static inline uint32_t ipn3ke_read_addr(volatile void *addr)\n+{\n+\treturn rte_le_to_cpu_32(IPN3KE_PCI_REG(addr));\n+}\n+\n+#define WCMD 0x8000000000000000\n+#define RCMD 0x4000000000000000\n+#define UPL_BASE 0x10000\n+static inline uint32_t _ipn3ke_indrct_read(struct ipn3ke_hw *hw,\n+\t\tuint32_t addr)\n+{\n+\tuint64_t word_offset = 0;\n+\tuint64_t read_data = 0;\n+\tuint64_t indirect_value = 0;\n+\tvolatile void *indirect_addrs = 0;\n+\n+\tword_offset = (addr & 0x1FFFFFF) >> 2;\n+\tindirect_value = RCMD | word_offset << 32;\n+\tindirect_addrs = (volatile void *)(hw->hw_addr +\n+\t\t\t\t\t\t(uint32_t)(UPL_BASE | 0x10));\n+\n+\trte_delay_us(10);\n+\n+\trte_write64((rte_cpu_to_le_64(indirect_value)), indirect_addrs);\n+\n+\tindirect_addrs = (volatile void *)(hw->hw_addr +\n+\t\t\t\t\t\t(uint32_t)(UPL_BASE | 0x18));\n+\twhile ((read_data >> 32) != 1)\n+\t\tread_data = rte_read64(indirect_addrs);\n+\n+\treturn rte_le_to_cpu_32(read_data);\n+}\n+\n+static inline void _ipn3ke_indrct_write(struct ipn3ke_hw *hw,\n+\t\tuint32_t addr, uint32_t value)\n+{\n+\tuint64_t word_offset = 0;\n+\tuint64_t indirect_value = 0;\n+\tvolatile void *indirect_addrs = 0;\n+\n+\tword_offset = (addr & 0x1FFFFFF) >> 2;\n+\tindirect_value = WCMD | word_offset << 32 | value;\n+\tindirect_addrs = (volatile void *)(hw->hw_addr +\n+\t\t\t\t\t\t(uint32_t)(UPL_BASE | 0x10));\n+\n+\trte_write64((rte_cpu_to_le_64(indirect_value)), indirect_addrs);\n+\trte_delay_us(10);\n+}\n+\n+#define IPN3KE_PCI_REG_WRITE(reg, value) \\\n+\trte_write32((rte_cpu_to_le_32(value)), reg)\n+\n+#define IPN3KE_PCI_REG_WRITE_RELAXED(reg, value) \\\n+\trte_write32_relaxed((rte_cpu_to_le_32(value)), reg)\n+\n+#define IPN3KE_READ_REG(hw, reg) \\\n+\t_ipn3ke_indrct_read((hw), (reg))\n+\n+#define IPN3KE_WRITE_REG(hw, reg, value) \\\n+\t_ipn3ke_indrct_write((hw), (reg), (value))\n+\n+#define IPN3KE_MASK_READ_REG(hw, reg, x, mask) \\\n+\t((mask) & IPN3KE_READ_REG((hw), ((reg) + (0x4 * (x)))))\n+\n+#define IPN3KE_MASK_WRITE_REG(hw, reg, x, value, mask) \\\n+\tIPN3KE_WRITE_REG((hw), ((reg) + (0x4 * (x))), ((mask) & (value)))\n+\n+#define IPN3KE_DEV_PRIVATE_TO_HW(dev) \\\n+\t(((struct ipn3ke_rpst *)(dev)->data->dev_private)->hw)\n+\n+#define IPN3KE_DEV_PRIVATE_TO_RPST(dev) \\\n+\t((struct ipn3ke_rpst *)(dev)->data->dev_private)\n+\n+#define IPN3KE_DEV_PRIVATE_TO_TM(dev) \\\n+\t(&(((struct ipn3ke_rpst *)(dev)->data->dev_private)->tm))\n+\n+/* Byte address of IPN3KE internal module */\n+#define IPN3KE_TM_VERSION (IPN3KE_QM_OFFSET + 0x0000)\n+#define IPN3KE_TM_SCRATCH (IPN3KE_QM_OFFSET + 0x0004)\n+#define IPN3KE_TM_STATUS (IPN3KE_QM_OFFSET + 0x0008)\n+#define IPN3KE_TM_MISC_STATUS (IPN3KE_QM_OFFSET + 0x0010)\n+#define IPN3KE_TM_MISC_WARNING_0 (IPN3KE_QM_OFFSET + 0x0040)\n+#define IPN3KE_TM_MISC_MON_0 (IPN3KE_QM_OFFSET + 0x0048)\n+#define IPN3KE_TM_MISC_FATAL_0 (IPN3KE_QM_OFFSET + 0x0050)\n+#define IPN3KE_TM_BW_MON_CTRL_1 (IPN3KE_QM_OFFSET + 0x0080)\n+#define IPN3KE_TM_BW_MON_CTRL_2 (IPN3KE_QM_OFFSET + 0x0084)\n+#define IPN3KE_TM_BW_MON_RATE (IPN3KE_QM_OFFSET + 0x0088)\n+#define IPN3KE_TM_STATS_CTRL (IPN3KE_QM_OFFSET + 0x0100)\n+#define IPN3KE_TM_STATS_DATA_0 (IPN3KE_QM_OFFSET + 0x0110)\n+#define IPN3KE_TM_STATS_DATA_1 (IPN3KE_QM_OFFSET + 0x0114)\n+#define IPN3KE_QM_UID_CONFIG_CTRL (IPN3KE_QM_OFFSET + 0x0200)\n+#define IPN3KE_QM_UID_CONFIG_DATA (IPN3KE_QM_OFFSET + 0x0204)\n+\n+#define IPN3KE_BM_VERSION (IPN3KE_QM_OFFSET + 0x4000)\n+#define IPN3KE_BM_STATUS (IPN3KE_QM_OFFSET + 0x4008)\n+#define IPN3KE_BM_STORE_CTRL (IPN3KE_QM_OFFSET + 0x4010)\n+#define IPN3KE_BM_STORE_STATUS (IPN3KE_QM_OFFSET + 0x4018)\n+#define IPN3KE_BM_STORE_MON (IPN3KE_QM_OFFSET + 0x4028)\n+#define IPN3KE_BM_WARNING_0 (IPN3KE_QM_OFFSET + 0x4040)\n+#define IPN3KE_BM_MON_0 (IPN3KE_QM_OFFSET + 0x4048)\n+#define IPN3KE_BM_FATAL_0 (IPN3KE_QM_OFFSET + 0x4050)\n+#define IPN3KE_BM_DRAM_ACCESS_CTRL (IPN3KE_QM_OFFSET + 0x4100)\n+#define IPN3KE_BM_DRAM_ACCESS_DATA_0 (IPN3KE_QM_OFFSET + 0x4120)\n+#define IPN3KE_BM_DRAM_ACCESS_DATA_1 (IPN3KE_QM_OFFSET + 0x4124)\n+#define IPN3KE_BM_DRAM_ACCESS_DATA_2 (IPN3KE_QM_OFFSET + 0x4128)\n+#define IPN3KE_BM_DRAM_ACCESS_DATA_3 (IPN3KE_QM_OFFSET + 0x412C)\n+#define IPN3KE_BM_DRAM_ACCESS_DATA_4 (IPN3KE_QM_OFFSET + 0x4130)\n+#define IPN3KE_BM_DRAM_ACCESS_DATA_5 (IPN3KE_QM_OFFSET + 0x4134)\n+#define IPN3KE_BM_DRAM_ACCESS_DATA_6 (IPN3KE_QM_OFFSET + 0x4138)\n+\n+#define IPN3KE_QM_VERSION (IPN3KE_QM_OFFSET + 0x8000)\n+#define IPN3KE_QM_STATUS (IPN3KE_QM_OFFSET + 0x8008)\n+#define IPN3KE_QM_LL_TABLE_MON (IPN3KE_QM_OFFSET + 0x8018)\n+#define IPN3KE_QM_WARNING_0 (IPN3KE_QM_OFFSET + 0x8040)\n+#define IPN3KE_QM_MON_0 (IPN3KE_QM_OFFSET + 0x8048)\n+#define IPN3KE_QM_FATAL_0 (IPN3KE_QM_OFFSET + 0x8050)\n+#define IPN3KE_QM_FATAL_1 (IPN3KE_QM_OFFSET + 0x8054)\n+#define IPN3KE_LL_TABLE_ACCESS_CTRL (IPN3KE_QM_OFFSET + 0x8100)\n+#define IPN3KE_LL_TABLE_ACCESS_DATA_0 (IPN3KE_QM_OFFSET + 0x8110)\n+#define IPN3KE_LL_TABLE_ACCESS_DATA_1 (IPN3KE_QM_OFFSET + 0x8114)\n+\n+#define IPN3KE_CCB_ERROR (IPN3KE_CCB_OFFSET + 0x0008)\n+#define IPN3KE_CCB_NSEGFREE (IPN3KE_CCB_OFFSET + 0x200000)\n+#define IPN3KE_CCB_NSEGFREE_MASK 0x3FFFFF\n+#define IPN3KE_CCB_PSEGMAX_COEF (IPN3KE_CCB_OFFSET + 0x200008)\n+#define IPN3KE_CCB_PSEGMAX_COEF_MASK 0xFFFFF\n+#define IPN3KE_CCB_NSEG_P (IPN3KE_CCB_OFFSET + 0x200080)\n+#define IPN3KE_CCB_NSEG_MASK 0x3FFFFF\n+#define IPN3KE_CCB_QPROFILE_Q (IPN3KE_CCB_OFFSET + 0x240000)\n+#define IPN3KE_CCB_QPROFILE_MASK 0x7FF\n+#define IPN3KE_CCB_PROFILE_P (IPN3KE_CCB_OFFSET + 0x280000)\n+#define IPN3KE_CCB_PROFILE_MASK 0x1FFFFFF\n+#define IPN3KE_CCB_PROFILE_MS (IPN3KE_CCB_OFFSET + 0xC)\n+#define IPN3KE_CCB_PROFILE_MS_MASK 0x1FFFFFF\n+#define IPN3KE_CCB_LR_LB_DBG_CTRL (IPN3KE_CCB_OFFSET + 0x2C0000)\n+#define IPN3KE_CCB_LR_LB_DBG_DONE (IPN3KE_CCB_OFFSET + 0x2C0004)\n+#define IPN3KE_CCB_LR_LB_DBG_RDATA (IPN3KE_CCB_OFFSET + 0x2C000C)\n+\n+#define IPN3KE_QOS_MAP_L1_X (IPN3KE_QOS_OFFSET + 0x000000)\n+#define IPN3KE_QOS_MAP_L1_MASK 0x1FFF\n+#define IPN3KE_QOS_MAP_L2_X (IPN3KE_QOS_OFFSET + 0x040000)\n+#define IPN3KE_QOS_MAP_L2_MASK 0x7\n+#define IPN3KE_QOS_TYPE_MASK 0x3\n+#define IPN3KE_QOS_TYPE_L1_X (IPN3KE_QOS_OFFSET + 0x200000)\n+#define IPN3KE_QOS_TYPE_L2_X (IPN3KE_QOS_OFFSET + 0x240000)\n+#define IPN3KE_QOS_TYPE_L3_X (IPN3KE_QOS_OFFSET + 0x280000)\n+#define IPN3KE_QOS_SCH_WT_MASK 0xFF\n+#define IPN3KE_QOS_SCH_WT_L1_X (IPN3KE_QOS_OFFSET + 0x400000)\n+#define IPN3KE_QOS_SCH_WT_L2_X (IPN3KE_QOS_OFFSET + 0x440000)\n+#define IPN3KE_QOS_SCH_WT_L3_X (IPN3KE_QOS_OFFSET + 0x480000)\n+#define IPN3KE_QOS_SHAP_WT_MASK 0x3FFF\n+#define IPN3KE_QOS_SHAP_WT_L1_X (IPN3KE_QOS_OFFSET + 0x600000)\n+#define IPN3KE_QOS_SHAP_WT_L2_X (IPN3KE_QOS_OFFSET + 0x640000)\n+#define IPN3KE_QOS_SHAP_WT_L3_X (IPN3KE_QOS_OFFSET + 0x680000)\n+\n+#define IPN3KE_CLF_BASE_DST_MAC_ADDR_HI (IPN3KE_CLASSIFY_OFFSET + 0x0000)\n+#define IPN3KE_CLF_BASE_DST_MAC_ADDR_LOW (IPN3KE_CLASSIFY_OFFSET + 0x0004)\n+#define IPN3KE_CLF_QINQ_STAG (IPN3KE_CLASSIFY_OFFSET + 0x0008)\n+#define IPN3KE_CLF_LKUP_ENABLE (IPN3KE_CLASSIFY_OFFSET + 0x000C)\n+#define IPN3KE_CLF_DFT_FLOW_ID (IPN3KE_CLASSIFY_OFFSET + 0x0040)\n+#define IPN3KE_CLF_RX_PARSE_CFG (IPN3KE_CLASSIFY_OFFSET + 0x0080)\n+#define IPN3KE_CLF_RX_STATS_CFG (IPN3KE_CLASSIFY_OFFSET + 0x00C0)\n+#define IPN3KE_CLF_RX_STATS_RPT (IPN3KE_CLASSIFY_OFFSET + 0x00C4)\n+#define IPN3KE_CLF_RX_TEST (IPN3KE_CLASSIFY_OFFSET + 0x0400)\n+\n+#define IPN3KE_CLF_EM_VERSION (IPN3KE_CLASSIFY_OFFSET + 0x40000 + 0x0000)\n+#define IPN3KE_CLF_EM_NUM (IPN3KE_CLASSIFY_OFFSET + 0x40000 + 0x0008)\n+#define IPN3KE_CLF_EM_KEY_WDTH (IPN3KE_CLASSIFY_OFFSET + 0x40000 + 0x000C)\n+#define IPN3KE_CLF_EM_RES_WDTH (IPN3KE_CLASSIFY_OFFSET + 0x40000 + 0x0010)\n+#define IPN3KE_CLF_EM_ALARMS (IPN3KE_CLASSIFY_OFFSET + 0x40000 + 0x0014)\n+#define IPN3KE_CLF_EM_DRC_RLAT (IPN3KE_CLASSIFY_OFFSET + 0x40000 + 0x0018)\n+\n+#define IPN3KE_CLF_MHL_VERSION (IPN3KE_CLASSIFY_OFFSET + 0x50000 + 0x0000)\n+#define IPN3KE_CLF_MHL_GEN_CTRL (IPN3KE_CLASSIFY_OFFSET + 0x50000 + 0x0018)\n+#define IPN3KE_CLF_MHL_MGMT_CTRL (IPN3KE_CLASSIFY_OFFSET + 0x50000 + 0x0020)\n+#define IPN3KE_CLF_MHL_MGMT_CTRL_BIT_BUSY 31\n+#define IPN3KE_CLF_MHL_MGMT_CTRL_FLUSH 0x0\n+#define IPN3KE_CLF_MHL_MGMT_CTRL_INSERT 0x1\n+#define IPN3KE_CLF_MHL_MGMT_CTRL_DELETE 0x2\n+#define IPN3KE_CLF_MHL_MGMT_CTRL_SEARCH 0x3\n+#define IPN3KE_CLF_MHL_FATAL_0 (IPN3KE_CLASSIFY_OFFSET + 0x50000 + 0x0050)\n+#define IPN3KE_CLF_MHL_MON_0 (IPN3KE_CLASSIFY_OFFSET + 0x50000 + 0x0060)\n+#define IPN3KE_CLF_MHL_TOTAL_ENTRIES (IPN3KE_CLASSIFY_OFFSET + \\\n+\t\t\t\t\t0x50000 + 0x0080)\n+#define IPN3KE_CLF_MHL_ONEHIT_BUCKETS (IPN3KE_CLASSIFY_OFFSET + \\\n+\t\t\t\t\t0x50000 + 0x0084)\n+#define IPN3KE_CLF_MHL_KEY_MASK 0xFFFFFFFF\n+#define IPN3KE_CLF_MHL_KEY_0 (IPN3KE_CLASSIFY_OFFSET + 0x50000 + 0x1000)\n+#define IPN3KE_CLF_MHL_KEY_1 (IPN3KE_CLASSIFY_OFFSET + 0x50000 + 0x1004)\n+#define IPN3KE_CLF_MHL_KEY_2 (IPN3KE_CLASSIFY_OFFSET + 0x50000 + 0x1008)\n+#define IPN3KE_CLF_MHL_KEY_3 (IPN3KE_CLASSIFY_OFFSET + 0x50000 + 0x100C)\n+#define IPN3KE_CLF_MHL_RES_MASK 0xFFFFFFFF\n+#define IPN3KE_CLF_MHL_RES (IPN3KE_CLASSIFY_OFFSET + 0x50000 + 0x2000)\n+\n+int\n+ipn3ke_rpst_dev_set_link_up(struct rte_eth_dev *dev);\n+int\n+ipn3ke_rpst_dev_set_link_down(struct rte_eth_dev *dev);\n+int\n+ipn3ke_rpst_link_update(struct rte_eth_dev *ethdev,\n+\t__rte_unused int wait_to_complete);\n+void\n+ipn3ke_rpst_promiscuous_enable(struct rte_eth_dev *ethdev);\n+void\n+ipn3ke_rpst_promiscuous_disable(struct rte_eth_dev *ethdev);\n+void\n+ipn3ke_rpst_allmulticast_enable(struct rte_eth_dev *ethdev);\n+void\n+ipn3ke_rpst_allmulticast_disable(struct rte_eth_dev *ethdev);\n+int\n+ipn3ke_rpst_mac_addr_set(struct rte_eth_dev *ethdev,\n+\t\tstruct ether_addr *mac_addr);\n+int\n+ipn3ke_rpst_mtu_set(struct rte_eth_dev *ethdev, uint16_t mtu);\n+\n+int\n+ipn3ke_rpst_init(struct rte_eth_dev *ethdev, void *init_params);\n+int\n+ipn3ke_rpst_uninit(struct rte_eth_dev *ethdev);\n+int\n+ipn3ke_hw_tm_init(struct ipn3ke_hw *hw);\n+\n+\n+/* IPN3KE_MASK is a macro used on 32 bit registers */\n+#define IPN3KE_MASK(mask, shift) ((mask) << (shift))\n+\n+#define IPN3KE_MAC_CTRL_BASE_0 0x00000000\n+#define IPN3KE_MAC_CTRL_BASE_1 0x00008000\n+\n+#define IPN3KE_MAC_STATS_MASK 0xFFFFFFFFF\n+\n+/* All the address are in 4Bytes*/\n+#define IPN3KE_MAC_PRIMARY_MAC_ADDR0 0x0010\n+#define IPN3KE_MAC_PRIMARY_MAC_ADDR1 0x0011\n+\n+#define IPN3KE_MAC_MAC_RESET_CONTROL 0x001F\n+#define IPN3KE_MAC_MAC_RESET_CONTROL_TX_SHIFT 0\n+#define IPN3KE_MAC_MAC_RESET_CONTROL_TX_MASK \\\n+\tIPN3KE_MASK(0x1, IPN3KE_MAC_MAC_RESET_CONTROL_TX_SHIFT)\n+\n+#define IPN3KE_MAC_MAC_RESET_CONTROL_RX_SHIFT 8\n+#define IPN3KE_MAC_MAC_RESET_CONTROL_RX_MASK \\\n+\tIPN3KE_MASK(0x1, IPN3KE_MAC_MAC_RESET_CONTROL_RX_SHIFT)\n+\n+#define IPN3KE_MAC_TX_PACKET_CONTROL 0x0020\n+#define IPN3KE_MAC_TX_PACKET_CONTROL_SHIFT 0\n+#define IPN3KE_MAC_TX_PACKET_CONTROL_MASK \\\n+\tIPN3KE_MASK(0x1, IPN3KE_MAC_TX_PACKET_CONTROL_SHIFT)\n+\n+#define IPN3KE_MAC_TX_SRC_ADDR_OVERRIDE 0x002A\n+#define IPN3KE_MAC_TX_SRC_ADDR_OVERRIDE_SHIFT 0\n+#define IPN3KE_MAC_TX_SRC_ADDR_OVERRIDE_MASK \\\n+\tIPN3KE_MASK(0x1, IPN3KE_MAC_TX_SRC_ADDR_OVERRIDE_SHIFT)\n+\n+#define IPN3KE_MAC_TX_FRAME_MAXLENGTH 0x002C\n+#define IPN3KE_MAC_TX_FRAME_MAXLENGTH_SHIFT 0\n+#define IPN3KE_MAC_TX_FRAME_MAXLENGTH_MASK \\\n+\tIPN3KE_MASK(0xFFFF, IPN3KE_MAC_TX_FRAME_MAXLENGTH_SHIFT)\n+\n+#define IPN3KE_MAC_TX_PAUSEFRAME_CONTROL 0x0040\n+#define IPN3KE_MAC_TX_PAUSEFRAME_CONTROL_SHIFT 0\n+#define IPN3KE_MAC_TX_PAUSEFRAME_CONTROL_MASK \\\n+\tIPN3KE_MASK(0x3, IPN3KE_MAC_TX_PAUSEFRAME_CONTROL_SHIFT)\n+\n+#define IPN3KE_MAC_TX_PAUSEFRAME_QUANTA 0x0042\n+#define IPN3KE_MAC_TX_PAUSEFRAME_QUANTA_SHIFT 0\n+#define IPN3KE_MAC_TX_PAUSEFRAME_QUANTA_MASK \\\n+\tIPN3KE_MASK(0xFFFF, IPN3KE_MAC_TX_PAUSEFRAME_QUANTA_SHIFT)\n+\n+#define IPN3KE_MAC_TX_PAUSEFRAME_HOLDOFF_QUANTA 0x0043\n+#define IPN3KE_MAC_TX_PAUSEFRAME_HOLDOFF_QUANTA_SHIFT 0\n+#define IPN3KE_MAC_TX_PAUSEFRAME_HOLDOFF_QUANTA_MASK \\\n+\tIPN3KE_MASK(0xFFFF, IPN3KE_MAC_TX_PAUSEFRAME_HOLDOFF_QUANTA_SHIFT)\n+\n+#define IPN3KE_MAC_TX_PAUSEFRAME_ENABLE 0x0044\n+#define IPN3KE_MAC_TX_PAUSEFRAME_ENABLE_CFG_SHIFT 0\n+#define IPN3KE_MAC_TX_PAUSEFRAME_ENABLE_CFG_MASK \\\n+\tIPN3KE_MASK(0x1, IPN3KE_MAC_TX_PAUSEFRAME_ENABLE_CFG_SHIFT)\n+\n+#define IPN3KE_MAC_TX_PAUSEFRAME_ENABLE_TYPE_SHIFT 1\n+#define IPN3KE_MAC_TX_PAUSEFRAME_ENABLE_TYPE_MASK \\\n+\tIPN3KE_MASK(0x3, IPN3KE_MAC_TX_PAUSEFRAME_ENABLE_TYPE_SHIFT)\n+\n+#define IPN3KE_MAC_RX_TRANSFER_CONTROL 0x00A0\n+#define IPN3KE_MAC_RX_TRANSFER_CONTROL_SHIFT 0x0\n+#define IPN3KE_MAC_RX_TRANSFER_CONTROL_MASK \\\n+\tIPN3KE_MASK(0x1, IPN3KE_MAC_RX_TRANSFER_CONTROL_SHIFT)\n+\n+#define IPN3KE_MAC_RX_FRAME_CONTROL 0x00AC\n+#define IPN3KE_MAC_RX_FRAME_CONTROL_EN_ALLUCAST_SHIFT 0x0\n+#define IPN3KE_MAC_RX_FRAME_CONTROL_EN_ALLUCAST_MASK \\\n+\tIPN3KE_MASK(0x1, IPN3KE_MAC_RX_FRAME_CONTROL_EN_ALLUCAST_SHIFT)\n+\n+#define IPN3KE_MAC_RX_FRAME_CONTROL_EN_ALLMCAST_SHIFT 0x1\n+#define IPN3KE_MAC_RX_FRAME_CONTROL_EN_ALLMCAST_MASK \\\n+\tIPN3KE_MASK(0x1, IPN3KE_MAC_RX_FRAME_CONTROL_EN_ALLMCAST_SHIFT)\n+\n+#define IPN3KE_VLAN_TAG_SIZE 4\n+/**\n+ * The overhead from MTU to max frame size.\n+ * Considering QinQ packet, the VLAN tag needs to be counted twice.\n+ */\n+#define IPN3KE_ETH_OVERHEAD \\\n+\t\t(ETHER_HDR_LEN + ETHER_CRC_LEN + IPN3KE_VLAN_TAG_SIZE * 2)\n+\n+#define IPN3KE_MAC_FRAME_SIZE_MAX 9728\n+#define IPN3KE_MAC_RX_FRAME_MAXLENGTH 0x00AE\n+#define IPN3KE_MAC_RX_FRAME_MAXLENGTH_SHIFT 0\n+#define IPN3KE_MAC_RX_FRAME_MAXLENGTH_MASK \\\n+\tIPN3KE_MASK(0xFFFF, IPN3KE_MAC_RX_FRAME_MAXLENGTH_SHIFT)\n+\n+#define IPN3KE_MAC_TX_STATS_CLR 0x0140\n+#define IPN3KE_MAC_TX_STATS_CLR_CLEAR_SHIFT 0\n+#define IPN3KE_MAC_TX_STATS_CLR_CLEAR_MASK \\\n+\tIPN3KE_MASK(0x1, IPN3KE_MAC_TX_STATS_CLR_CLEAR_SHIFT)\n+\n+#define IPN3KE_MAC_RX_STATS_CLR 0x01C0\n+#define IPN3KE_MAC_RX_STATS_CLR_CLEAR_SHIFT 0\n+#define IPN3KE_MAC_RX_STATS_CLR_CLEAR_MASK \\\n+\tIPN3KE_MASK(0x1, IPN3KE_MAC_RX_STATS_CLR_CLEAR_SHIFT)\n+\n+/*tx_stats_framesOK*/\n+#define IPN3KE_MAC_TX_STATS_FRAMESOK_HI 0x0142\n+#define IPN3KE_MAC_TX_STATS_FRAMESOK_LOW 0x0143\n+\n+/*rx_stats_framesOK*/\n+#define IPN3KE_MAC_RX_STATS_FRAMESOK_HI 0x01C2\n+#define IPN3KE_MAC_RX_STATS_FRAMESOK_LOW 0x01C3\n+\n+/*tx_stats_framesErr*/\n+#define IPN3KE_MAC_TX_STATS_FRAMESERR_HI 0x0144\n+#define IPN3KE_MAC_TX_STATS_FRAMESERR_LOW 0x0145\n+\n+/*rx_stats_framesErr*/\n+#define IPN3KE_MAC_RX_STATS_FRAMESERR_HI 0x01C4\n+#define IPN3KE_MAC_RX_STATS_FRAMESERR_LOW 0x01C5\n+\n+/*rx_stats_framesCRCErr*/\n+#define IPN3KE_MAC_RX_STATS_FRAMESCRCERR_HI 0x01C6\n+#define IPN3KE_MAC_RX_STATS_FRAMESCRCERR_LOW 0x01C7\n+\n+/*tx_stats_octetsOK 64b*/\n+#define IPN3KE_MAC_TX_STATS_OCTETSOK_HI 0x0148\n+#define IPN3KE_MAC_TX_STATS_OCTETSOK_LOW 0x0149\n+\n+/*rx_stats_octetsOK 64b*/\n+#define IPN3KE_MAC_RX_STATS_OCTETSOK_HI 0x01C8\n+#define IPN3KE_MAC_RX_STATS_OCTETSOK_LOW 0x01C9\n+\n+/*tx_stats_pauseMACCtrl_Frames*/\n+#define IPN3KE_MAC_TX_STATS_PAUSEMACCTRL_FRAMES_HI 0x014A\n+#define IPN3KE_MAC_TX_STATS_PAUSEMACCTRL_FRAMES_LOW 0x014B\n+\n+/*rx_stats_pauseMACCtrl_Frames*/\n+#define IPN3KE_MAC_RX_STATS_PAUSEMACCTRL_FRAMES_HI 0x01CA\n+#define IPN3KE_MAC_RX_STATS_PAUSEMACCTRL_FRAMES_LOW 0x01CB\n+\n+/*tx_stats_ifErrors*/\n+#define IPN3KE_MAC_TX_STATS_IFERRORS_HI 0x014C\n+#define IPN3KE_MAC_TX_STATS_IFERRORS_LOW 0x014D\n+\n+/*rx_stats_ifErrors*/\n+#define IPN3KE_MAC_RX_STATS_IFERRORS_HI 0x01CC\n+#define IPN3KE_MAC_RX_STATS_IFERRORS_LOW 0x01CD\n+\n+/*tx_stats_unicast_FramesOK*/\n+#define IPN3KE_MAC_TX_STATS_UNICAST_FRAMESOK_HI 0x014E\n+#define IPN3KE_MAC_TX_STATS_UNICAST_FRAMESOK_LOW 0x014F\n+\n+/*rx_stats_unicast_FramesOK*/\n+#define IPN3KE_MAC_RX_STATS_UNICAST_FRAMESOK_HI 0x01CE\n+#define IPN3KE_MAC_RX_STATS_UNICAST_FRAMESOK_LOW 0x01CF\n+\n+/*tx_stats_unicast_FramesErr*/\n+#define IPN3KE_MAC_TX_STATS_UNICAST_FRAMESERR_HI 0x0150\n+#define IPN3KE_MAC_TX_STATS_UNICAST_FRAMESERR_LOW 0x0151\n+\n+/*rx_stats_unicast_FramesErr*/\n+#define IPN3KE_MAC_RX_STATS_UNICAST_FRAMESERR_HI 0x01D0\n+#define IPN3KE_MAC_RX_STATS_UNICAST_FRAMESERR_LOW 0x01D1\n+\n+/*tx_stats_multicast_FramesOK*/\n+#define IPN3KE_MAC_TX_STATS_MULTICAST_FRAMESOK_HI 0x0152\n+#define IPN3KE_MAC_TX_STATS_MULTICAST_FRAMESOK_LOW 0x0153\n+\n+/*rx_stats_multicast_FramesOK*/\n+#define IPN3KE_MAC_RX_STATS_MULTICAST_FRAMESOK_HI 0x01D2\n+#define IPN3KE_MAC_RX_STATS_MULTICAST_FRAMESOK_LOW 0x01D3\n+\n+/*tx_stats_multicast_FramesErr*/\n+#define IPN3KE_MAC_TX_STATS_MULTICAST_FRAMESERR_HI 0x0154\n+#define IPN3KE_MAC_TX_STATS_MULTICAST_FRAMESERR_LOW 0x0155\n+\n+/*rx_stats_multicast_FramesErr*/\n+#define IPN3KE_MAC_RX_STATS_MULTICAST_FRAMESERR_HI 0x01D4\n+#define IPN3KE_MAC_RX_STATS_MULTICAST_FRAMESERR_LOW 0x01D5\n+\n+/*tx_stats_broadcast_FramesOK*/\n+#define IPN3KE_MAC_TX_STATS_BROADCAST_FRAMESOK_HI 0x0156\n+#define IPN3KE_MAC_TX_STATS_BROADCAST_FRAMESOK_LOW 0x0157\n+\n+/*rx_stats_broadcast_FramesOK*/\n+#define IPN3KE_MAC_RX_STATS_BROADCAST_FRAMESOK_HI 0x01D6\n+#define IPN3KE_MAC_RX_STATS_BROADCAST_FRAMESOK_LOW 0x01D7\n+\n+/*tx_stats_broadcast_FramesErr*/\n+#define IPN3KE_MAC_TX_STATS_BROADCAST_FRAMESERR_HI 0x0158\n+#define IPN3KE_MAC_TX_STATS_BROADCAST_FRAMESERR_LOW 0x0159\n+\n+/*rx_stats_broadcast_FramesErr*/\n+#define IPN3KE_MAC_RX_STATS_BROADCAST_FRAMESERR_HI 0x01D8\n+#define IPN3KE_MAC_RX_STATS_BROADCAST_FRAMESERR_LOW 0x01D9\n+\n+/*tx_stats_etherStatsOctets 64b*/\n+#define IPN3KE_MAC_TX_STATS_ETHERSTATSOCTETS_HI 0x015A\n+#define IPN3KE_MAC_TX_STATS_ETHERSTATSOCTETS_LOW 0x015B\n+\n+/*rx_stats_etherStatsOctets 64b*/\n+#define IPN3KE_MAC_RX_STATS_ETHERSTATSOCTETS_HI 0x01DA\n+#define IPN3KE_MAC_RX_STATS_ETHERSTATSOCTETS_LOW 0x01DB\n+\n+/*tx_stats_etherStatsPkts*/\n+#define IPN3KE_MAC_TX_STATS_ETHERSTATSPKTS_HI 0x015C\n+#define IPN3KE_MAC_TX_STATS_ETHERSTATSPKTS_LOW 0x015D\n+\n+/*rx_stats_etherStatsPkts*/\n+#define IPN3KE_MAC_RX_STATS_ETHERSTATSPKTS_HI 0x01DC\n+#define IPN3KE_MAC_RX_STATS_ETHERSTATSPKTS_LOW 0x01DD\n+\n+/*tx_stats_etherStatsUndersizePkts*/\n+#define IPN3KE_MAC_TX_STATS_ETHERSTATSUNDERSIZEPKTS_HI 0x015E\n+#define IPN3KE_MAC_TX_STATS_ETHERSTATSUNDERSIZEPKTS_LOW 0x015F\n+\n+/*rx_stats_etherStatsUndersizePkts*/\n+#define IPN3KE_MAC_RX_STATS_ETHERSTATSUNDERSIZEPKTS_HI 0x01DE\n+#define IPN3KE_MAC_RX_STATS_ETHERSTATSUNDERSIZEPKTS_LOW 0x01DF\n+\n+/*tx_stats_etherStatsOversizePkts*/\n+#define IPN3KE_MAC_TX_STATS_ETHERSTATSOVERSIZEPKTS_HI 0x0160\n+#define IPN3KE_MAC_TX_STATS_ETHERSTATSOVERSIZEPKTS_LOW 0x0161\n+\n+/*rx_stats_etherStatsOversizePkts*/\n+#define IPN3KE_MAC_RX_STATS_ETHERSTATSOVERSIZEPKTS_HI 0x01E0\n+#define IPN3KE_MAC_RX_STATS_ETHERSTATSOVERSIZEPKTS_LOW 0x01E1\n+\n+/*tx_stats_etherStatsPkts64Octets*/\n+#define IPN3KE_MAC_TX_STATS_ETHERSTATSPKTS64OCTETS_HI 0x0162\n+#define IPN3KE_MAC_TX_STATS_ETHERSTATSPKTS64OCTETS_LOW 0x0163\n+\n+/*rx_stats_etherStatsPkts64Octets*/\n+#define IPN3KE_MAC_RX_STATS_ETHERSTATSPKTS64OCTETS_HI 0x01E2\n+#define IPN3KE_MAC_RX_STATS_ETHERSTATSPKTS64OCTETS_LOW 0x01E3\n+\n+/*tx_stats_etherStatsPkts65to127Octets*/\n+#define IPN3KE_MAC_TX_STATS_ETHERSTATSPKTS65TO127OCTETS_HI 0x0164\n+#define IPN3KE_MAC_TX_STATS_ETHERSTATSPKTS65TO127OCTETS_LOW 0x0165\n+\n+/*rx_stats_etherStatsPkts65to127Octets*/\n+#define IPN3KE_MAC_RX_STATS_ETHERSTATSPKTS65TO127OCTETS_HI 0x01E4\n+#define IPN3KE_MAC_RX_STATS_ETHERSTATSPKTS65TO127OCTETS_LOW 0x01E5\n+\n+/*tx_stats_etherStatsPkts128to255Octets*/\n+#define IPN3KE_MAC_TX_STATS_ETHERSTATSPKTS128TO255OCTETS_HI 0x0166\n+#define IPN3KE_MAC_TX_STATS_ETHERSTATSPKTS128TO255OCTETS_LOW 0x0167\n+\n+/*rx_stats_etherStatsPkts128to255Octets*/\n+#define IPN3KE_MAC_RX_STATS_ETHERSTATSPKTS128TO255OCTETS_HI 0x01E6\n+#define IPN3KE_MAC_RX_STATS_ETHERSTATSPKTS128TO255OCTETS_LOW 0x01E7\n+\n+/*tx_stats_etherStatsPkts256to511Octet*/\n+#define IPN3KE_MAC_TX_STATS_ETHERSTATSPKTS256TO511OCTET_HI 0x0168\n+#define IPN3KE_MAC_TX_STATS_ETHERSTATSPKTS256TO511OCTET_LOW 0x0169\n+\n+/*rx_stats_etherStatsPkts256to511Octets*/\n+#define IPN3KE_MAC_RX_STATS_ETHERSTATSPKTS256TO511OCTETS_HI 0x01E8\n+#define IPN3KE_MAC_RX_STATS_ETHERSTATSPKTS256TO511OCTETS_LOW 0x01E9\n+\n+/*tx_stats_etherStatsPkts512to1023Octets*/\n+#define IPN3KE_MAC_TX_STATS_ETHERSTATSPKTS512TO1023OCTETS_HI 0x016A\n+#define IPN3KE_MAC_TX_STATS_ETHERSTATSPKTS512TO1023OCTETS_LOW 0x016B\n+\n+/*rx_stats_etherStatsPkts512to1023Octets*/\n+#define IPN3KE_MAC_RX_STATS_ETHERSTATSPKTS512TO1023OCTETS_HI 0x01EA\n+#define IPN3KE_MAC_RX_STATS_ETHERSTATSPKTS512TO1023OCTETS_LOW 0x01EB\n+\n+/*tx_stats_etherStatPkts1024to1518Octets*/\n+#define IPN3KE_MAC_TX_STATS_ETHERSTATPKTS1024TO1518OCTETS_HI 0x016C\n+#define IPN3KE_MAC_TX_STATS_ETHERSTATPKTS1024TO1518OCTETS_LOW 0x016D\n+\n+/*rx_stats_etherStatPkts1024to1518Octets*/\n+#define IPN3KE_MAC_RX_STATS_ETHERSTATPKTS1024TO1518OCTETS_HI 0x01EC\n+#define IPN3KE_MAC_RX_STATS_ETHERSTATPKTS1024TO1518OCTETS_LOW 0x01ED\n+\n+/*tx_stats_etherStatsPkts1519toXOctets*/\n+#define IPN3KE_MAC_TX_STATS_ETHERSTATSPKTS1519TOXOCTETS_HI 0x016E\n+#define IPN3KE_MAC_TX_STATS_ETHERSTATSPKTS1519TOXOCTETS_LOW 0x016F\n+\n+/*rx_stats_etherStatsPkts1519toXOctets*/\n+#define IPN3KE_MAC_RX_STATS_ETHERSTATSPKTS1519TOXOCTETS_HI 0x01EE\n+#define IPN3KE_MAC_RX_STATS_ETHERSTATSPKTS1519TOXOCTETS_LOW 0x01EF\n+\n+/*rx_stats_etherStatsFragments*/\n+#define IPN3KE_MAC_RX_STATS_ETHERSTATSFRAGMENTS_HI 0x01F0\n+#define IPN3KE_MAC_RX_STATS_ETHERSTATSFRAGMENTS_LOW 0x01F1\n+\n+/*rx_stats_etherStatsJabbers*/\n+#define IPN3KE_MAC_RX_STATS_ETHERSTATSJABBERS_HI 0x01F2\n+#define IPN3KE_MAC_RX_STATS_ETHERSTATSJABBERS_LOW 0x01F3\n+\n+/*rx_stats_etherStatsCRCErr*/\n+#define IPN3KE_MAC_RX_STATS_ETHERSTATSCRCERR_HI 0x01F4\n+#define IPN3KE_MAC_RX_STATS_ETHERSTATSCRCERR_LOW 0x01F5\n+\n+/*tx_stats_unicastMACCtrlFrames*/\n+#define IPN3KE_MAC_TX_STATS_UNICASTMACCTRLFRAMES_HI 0x0176\n+#define IPN3KE_MAC_TX_STATS_UNICASTMACCTRLFRAMES_LOW 0x0177\n+\n+/*rx_stats_unicastMACCtrlFrames*/\n+#define IPN3KE_MAC_RX_STATS_UNICASTMACCTRLFRAMES_HI 0x01F6\n+#define IPN3KE_MAC_RX_STATS_UNICASTMACCTRLFRAMES_LOW 0x01F7\n+\n+/*tx_stats_multicastMACCtrlFrames*/\n+#define IPN3KE_MAC_TX_STATS_MULTICASTMACCTRLFRAMES_HI 0x0178\n+#define IPN3KE_MAC_TX_STATS_MULTICASTMACCTRLFRAMES_LOW 0x0179\n+\n+/*rx_stats_multicastMACCtrlFrames*/\n+#define IPN3KE_MAC_RX_STATS_MULTICASTMACCTRLFRAMES_HI 0x01F8\n+#define IPN3KE_MAC_RX_STATS_MULTICASTMACCTRLFRAMES_LOW 0x01F9\n+\n+/*tx_stats_broadcastMACCtrlFrames*/\n+#define IPN3KE_MAC_TX_STATS_BROADCASTMACCTRLFRAMES_HI 0x017A\n+#define IPN3KE_MAC_TX_STATS_BROADCASTMACCTRLFRAMES_LOW 0x017B\n+\n+/*rx_stats_broadcastMACCtrlFrames*/\n+#define IPN3KE_MAC_RX_STATS_BROADCASTMACCTRLFRAMES_HI 0x01FA\n+#define IPN3KE_MAC_RX_STATS_BROADCASTMACCTRLFRAMES_LOW 0x01FB\n+\n+/*tx_stats_PFCMACCtrlFrames*/\n+#define IPN3KE_MAC_TX_STATS_PFCMACCTRLFRAMES_HI 0x017C\n+#define IPN3KE_MAC_TX_STATS_PFCMACCTRLFRAMES_LOW 0x017D\n+\n+/*rx_stats_PFCMACCtrlFrames*/\n+#define IPN3KE_MAC_RX_STATS_PFCMACCTRLFRAMES_HI 0x01FC\n+#define IPN3KE_MAC_RX_STATS_PFCMACCTRLFRAMES_LOW 0x01FD\n+\n+\n+#endif /* _IPN3KE_ETHDEV_H_ */\ndiff --git a/drivers/net/ipn3ke/ipn3ke_logs.h b/drivers/net/ipn3ke/ipn3ke_logs.h\nnew file mode 100644\nindex 0000000..dedaece\n--- /dev/null\n+++ b/drivers/net/ipn3ke/ipn3ke_logs.h\n@@ -0,0 +1,30 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2019 Intel Corporation\n+ */\n+\n+#ifndef _IPN3KE_LOGS_H_\n+#define _IPN3KE_LOGS_H_\n+\n+#include <rte_log.h>\n+\n+extern int ipn3ke_afu_logtype;\n+\n+#define IPN3KE_AFU_PMD_LOG(level, fmt, args...) \\\n+\trte_log(RTE_LOG_ ## level, ipn3ke_afu_logtype, \"ipn3ke_afu: \" fmt, \\\n+\t\t##args)\n+\n+#define IPN3KE_AFU_PMD_FUNC_TRACE() IPN3KE_AFU_PMD_LOG(DEBUG, \">>\")\n+\n+#define IPN3KE_AFU_PMD_DEBUG(fmt, args...) \\\n+\tIPN3KE_AFU_PMD_LOG(DEBUG, fmt, ## args)\n+\n+#define IPN3KE_AFU_PMD_INFO(fmt, args...) \\\n+\tIPN3KE_AFU_PMD_LOG(INFO, fmt, ## args)\n+\n+#define IPN3KE_AFU_PMD_ERR(fmt, args...) \\\n+\tIPN3KE_AFU_PMD_LOG(ERR, fmt, ## args)\n+\n+#define IPN3KE_AFU_PMD_WARN(fmt, args...) \\\n+\tIPN3KE_AFU_PMD_LOG(WARNING, fmt, ## args)\n+\n+#endif /* _IPN3KE_LOGS_H_ */\ndiff --git a/drivers/net/ipn3ke/ipn3ke_rawdev_api.h b/drivers/net/ipn3ke/ipn3ke_rawdev_api.h\nnew file mode 100644\nindex 0000000..671fae8\n--- /dev/null\n+++ b/drivers/net/ipn3ke/ipn3ke_rawdev_api.h\n@@ -0,0 +1,62 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2010-2018 Intel Corporation\n+ */\n+\n+#ifndef _IFPGA_RAWDEV_API_H_\n+#define _IFPGA_RAWDEV_API_H_\n+\n+#include <rte_ether.h>\n+\n+enum ifpga_rawdev_retimer_media_type {\n+\tIFPGA_RAWDEV_RETIMER_MEDIA_TYPE_UNKNOWN = 0,\n+\tIFPGA_RAWDEV_RETIMER_MEDIA_TYPE_100GBASE_LR4,\n+\tIFPGA_RAWDEV_RETIMER_MEDIA_TYPE_100GBASE_SR4,\n+\tIFPGA_RAWDEV_RETIMER_MEDIA_TYPE_100GBASE_CR4,\n+\tIFPGA_RAWDEV_RETIMER_MEDIA_TYPE_40GBASE_LR4,\n+\tIFPGA_RAWDEV_RETIMER_MEDIA_TYPE_400GBASE_SR4,\n+\tIFPGA_RAWDEV_RETIMER_MEDIA_TYPE_40GBASE_CR4,\n+\tIFPGA_RAWDEV_RETIMER_MEDIA_TYPE_25GBASE_SR,\n+\tIFPGA_RAWDEV_RETIMER_MEDIA_TYPE_25GBASE_CR,\n+\tIFPGA_RAWDEV_RETIMER_MEDIA_TYPE_10GBASE_LR,\n+\tIFPGA_RAWDEV_RETIMER_MEDIA_TYPE_10GBASE_SR,\n+\tIFPGA_RAWDEV_RETIMER_MEDIA_TYPE_10GBASE_DAC,\n+\tIFPGA_RAWDEV_RETIMER_MEDIA_TYPE_DEFAULT\n+};\n+\n+enum ifpga_rawdev_retimer_mac_type {\n+\tIFPGA_RAWDEV_RETIMER_MAC_TYPE_UNKNOWN = 0,\n+\tIFPGA_RAWDEV_RETIMER_MAC_TYPE_100GE_CAUI,\n+\tIFPGA_RAWDEVG_RETIMER_MAC_TYPE_40GE_XLAUI,\n+\tIFPGA_RAWDEV_RETIMER_MAC_TYPE_25GE_25GAUI,\n+\tIFPGA_RAWDEV_RETIMER_MAC_TYPE_10GE_XFI,\n+\tIFPGA_RAWDEV_RETIMER_MAC_TYPE_DEFAULT\n+};\n+\n+#define IFPGA_RAWDEV_LINK_SPEED_10GB_SHIFT 0x0\n+#define IFPGA_RAWDEV_LINK_SPEED_40GB_SHIFT 0x1\n+#define IFPGA_RAWDEV_LINK_SPEED_25GB_SHIFT 0x2\n+\n+enum ifpga_rawdev_link_speed {\n+\tIFPGA_RAWDEV_LINK_SPEED_UNKNOWN = 0,\n+\tIFPGA_RAWDEV_LINK_SPEED_10GB =\n+\t\t(1 << IFPGA_RAWDEV_LINK_SPEED_10GB_SHIFT),\n+\tIFPGA_RAWDEV_LINK_SPEED_40GB =\n+\t\t(1 << IFPGA_RAWDEV_LINK_SPEED_40GB_SHIFT),\n+\tIFPGA_RAWDEV_LINK_SPEED_25GB =\n+\t\t(1 << IFPGA_RAWDEV_LINK_SPEED_25GB_SHIFT),\n+};\n+\n+struct ifpga_rawdevg_retimer_info {\n+\tint retimer_num;\n+\tint port_num;\n+\tenum ifpga_rawdev_retimer_media_type media_type;\n+\tenum ifpga_rawdev_retimer_mac_type mac_type;\n+};\n+\n+struct ifpga_rawdevg_link_info {\n+\tint port;\n+\tint link_up;\n+\tenum ifpga_rawdev_link_speed link_speed;\n+};\n+\n+#endif /* _IFPGA_RAWDEV_H_ */\ndiff --git a/drivers/net/ipn3ke/meson.build b/drivers/net/ipn3ke/meson.build\nnew file mode 100644\nindex 0000000..e983bb3\n--- /dev/null\n+++ b/drivers/net/ipn3ke/meson.build\n@@ -0,0 +1,6 @@\n+# SPDX-License-Identifier: BSD-3-Clause\n+# Copyright(c) 2019 Intel Corporation\n+\n+allow_experimental_apis = true\n+sources += files('ipn3ke_ethdev.c')\n+deps += ['bus_ifpga', 'sched']\ndiff --git a/drivers/net/ipn3ke/rte_pmd_ipn3ke_version.map b/drivers/net/ipn3ke/rte_pmd_ipn3ke_version.map\nnew file mode 100644\nindex 0000000..fc8c95e\n--- /dev/null\n+++ b/drivers/net/ipn3ke/rte_pmd_ipn3ke_version.map\n@@ -0,0 +1,4 @@\n+DPDK_19.05 {\n+\n+\tlocal: *;\n+};\ndiff --git a/drivers/net/meson.build b/drivers/net/meson.build\nindex 3ecc78c..81a6c79 100644\n--- a/drivers/net/meson.build\n+++ b/drivers/net/meson.build\n@@ -19,6 +19,7 @@ drivers = ['af_packet',\n \t'iavf',\n \t'ice',\n \t'ifc',\n+\t'ipn3ke',\n \t'ixgbe',\n \t'kni',\n \t'liquidio',\ndiff --git a/mk/rte.app.mk b/mk/rte.app.mk\nindex 262132f..3bb0821 100644\n--- a/mk/rte.app.mk\n+++ b/mk/rte.app.mk\n@@ -295,6 +295,7 @@ endif # CONFIG_RTE_LIBRTE_FSLMC_BUS\n _LDLIBS-$(CONFIG_RTE_LIBRTE_IFPGA_BUS) += -lrte_bus_ifpga\n ifeq ($(CONFIG_RTE_LIBRTE_IFPGA_BUS),y)\n _LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_IFPGA_RAWDEV) += -lrte_pmd_ifpga_rawdev\n+_LDLIBS-$(CONFIG_RTE_LIBRTE_IPN3KE_PMD) += -lrte_pmd_ipn3ke\n endif # CONFIG_RTE_LIBRTE_IFPGA_BUS\n endif # CONFIG_RTE_LIBRTE_RAWDEV\n \ndiff --git a/usertools/dpdk-devbind.py b/usertools/dpdk-devbind.py\nindex 249b65a..3fb358e 100755\n--- a/usertools/dpdk-devbind.py\n+++ b/usertools/dpdk-devbind.py\n@@ -12,6 +12,8 @@\n # The PCI base class for all devices\n network_class = {'Class': '02', 'Vendor': None, 'Device': None,\n 'SVendor': None, 'SDevice': None}\n+ifpga_class = {'Class': '12', 'Vendor': '8086', 'Device': 'bcc0,09c4,0b30',\n+ 'SVendor': None, 'SDevice': None}\n encryption_class = {'Class': '10', 'Vendor': None, 'Device': None,\n 'SVendor': None, 'SDevice': None}\n intel_processor_class = {'Class': '0b', 'Vendor': '8086', 'Device': None,\n@@ -34,7 +36,7 @@\n octeontx2_npa = {'Class': '08', 'Vendor': '177d', 'Device': 'a0fb,a0fc',\n 'SVendor': None, 'SDevice': None}\n \n-network_devices = [network_class, cavium_pkx, avp_vnic]\n+network_devices = [network_class, cavium_pkx, avp_vnic, ifpga_class]\n crypto_devices = [encryption_class, intel_processor_class]\n eventdev_devices = [cavium_sso, cavium_tim, octeontx2_sso]\n mempool_devices = [cavium_fpa, octeontx2_npa]\n", "prefixes": [ "v4", "03/14" ] }