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GET /api/patches/51/?format=api
{ "id": 51, "url": "http://patches.dpdk.org/api/patches/51/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1405651521-14545-2-git-send-email-helin.zhang@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1405651521-14545-2-git-send-email-helin.zhang@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1405651521-14545-2-git-send-email-helin.zhang@intel.com", "date": "2014-07-18T02:45:19", "name": "[dpdk-dev,1/3] i40evf: add RSS support in VF", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "9bc507da8a3e633773cf550d5cf76ff472167995", "submitter": { "id": 14, "url": "http://patches.dpdk.org/api/people/14/?format=api", "name": "Zhang, Helin", "email": "helin.zhang@intel.com" }, "delegate": null, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1405651521-14545-2-git-send-email-helin.zhang@intel.com/mbox/", "series": [], "comments": "http://patches.dpdk.org/api/patches/51/comments/", "check": "pending", "checks": "http://patches.dpdk.org/api/patches/51/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<hzhan75@shecgisg004.sh.intel.com>", "Received": [ "from mga11.intel.com (mga11.intel.com [192.55.52.93])\n\tby dpdk.org (Postfix) with ESMTP id 32BAF959\n\tfor <dev@dpdk.org>; Fri, 18 Jul 2014 04:44:34 +0200 (CEST)", "from fmsmga001.fm.intel.com ([10.253.24.23])\n\tby fmsmga102.fm.intel.com with ESMTP; 17 Jul 2014 19:45:32 -0700", "from shvmail01.sh.intel.com ([10.239.29.42])\n\tby fmsmga001.fm.intel.com with ESMTP; 17 Jul 2014 19:45:30 -0700", "from shecgisg004.sh.intel.com (shecgisg004.sh.intel.com\n\t[10.239.29.89])\n\tby shvmail01.sh.intel.com with ESMTP id s6I2jSM1025162;\n\tFri, 18 Jul 2014 10:45:28 +0800", "from shecgisg004.sh.intel.com (localhost [127.0.0.1])\n\tby shecgisg004.sh.intel.com (8.13.6/8.13.6/SuSE Linux 0.8) with ESMTP\n\tid s6I2jPkV014661; Fri, 18 Jul 2014 10:45:27 +0800", "(from hzhan75@localhost)\n\tby shecgisg004.sh.intel.com (8.13.6/8.13.6/Submit) id s6I2jPt8014657; \n\tFri, 18 Jul 2014 10:45:25 +0800" ], "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.01,682,1400050800\"; d=\"scan'208\";a=\"563544553\"", "From": "Helin Zhang <helin.zhang@intel.com>", "To": "dev@dpdk.org", "Date": "Fri, 18 Jul 2014 10:45:19 +0800", "Message-Id": "<1405651521-14545-2-git-send-email-helin.zhang@intel.com>", "X-Mailer": "git-send-email 1.7.0.7", "In-Reply-To": "<1405651521-14545-1-git-send-email-helin.zhang@intel.com>", "References": "<1405651521-14545-1-git-send-email-helin.zhang@intel.com>", "Subject": "[dpdk-dev] [PATCH 1/3] i40evf: add RSS support in VF", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "patches and discussions about DPDK <dev.dpdk.org>", "List-Unsubscribe": "<http://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://dpdk.org/ml/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<http://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "X-List-Received-Date": "Fri, 18 Jul 2014 02:44:35 -0000" }, "content": "Add VF RSS support in Poll Mode Driver, as it is supported by hardware.\n\nSigned-off-by: Helin Zhang <helin.zhang@intel.com>\nAcked-by: Cunming Liang <cunming.liang@intel.com>\nAcked-by: Jijiang Liu <jijiang.liu@intel.com>\n---\n lib/librte_pmd_i40e/i40e_ethdev.c | 4 +-\n lib/librte_pmd_i40e/i40e_ethdev.h | 40 ++++++-\n lib/librte_pmd_i40e/i40e_ethdev_vf.c | 208 +++++++++++++++++++++++++++++++++++\n 3 files changed, 249 insertions(+), 3 deletions(-)", "diff": "diff --git a/lib/librte_pmd_i40e/i40e_ethdev.c b/lib/librte_pmd_i40e/i40e_ethdev.c\nindex 9ed31b5..85e8b18 100644\n--- a/lib/librte_pmd_i40e/i40e_ethdev.c\n+++ b/lib/librte_pmd_i40e/i40e_ethdev.c\n@@ -3747,7 +3747,7 @@ DONE:\n }\n \n /* Configure hash enable flags for RSS */\n-static uint64_t\n+uint64_t\n i40e_config_hena(uint64_t flags)\n {\n \tuint64_t hena = 0;\n@@ -3782,7 +3782,7 @@ i40e_config_hena(uint64_t flags)\n }\n \n /* Parse the hash enable flags */\n-static uint64_t\n+uint64_t\n i40e_parse_hena(uint64_t flags)\n {\n \tuint64_t rss_hf = 0;\ndiff --git a/lib/librte_pmd_i40e/i40e_ethdev.h b/lib/librte_pmd_i40e/i40e_ethdev.h\nindex 64deef2..1d42cd2 100644\n--- a/lib/librte_pmd_i40e/i40e_ethdev.h\n+++ b/lib/librte_pmd_i40e/i40e_ethdev.h\n@@ -68,6 +68,36 @@\n \t\t I40E_FLAG_HEADER_SPLIT_ENABLED | \\\n \t\t I40E_FLAG_FDIR)\n \n+#define I40E_RSS_OFFLOAD_ALL ( \\\n+\tETH_RSS_NONF_IPV4_UDP | \\\n+\tETH_RSS_NONF_IPV4_TCP | \\\n+\tETH_RSS_NONF_IPV4_SCTP | \\\n+\tETH_RSS_NONF_IPV4_OTHER | \\\n+\tETH_RSS_FRAG_IPV4 | \\\n+\tETH_RSS_NONF_IPV6_UDP | \\\n+\tETH_RSS_NONF_IPV6_TCP | \\\n+\tETH_RSS_NONF_IPV6_SCTP | \\\n+\tETH_RSS_NONF_IPV6_OTHER | \\\n+\tETH_RSS_FRAG_IPV6 | \\\n+\tETH_RSS_L2_PAYLOAD)\n+\n+/* All bits of RSS hash enable */\n+#define I40E_RSS_HENA_ALL ( \\\n+\t(1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP) | \\\n+\t(1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP) | \\\n+\t(1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP) | \\\n+\t(1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER) | \\\n+\t(1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4) | \\\n+\t(1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP) | \\\n+\t(1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP) | \\\n+\t(1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP) | \\\n+\t(1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER) | \\\n+\t(1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6) | \\\n+\t(1ULL << I40E_FILTER_PCTYPE_FCOE_OX) | \\\n+\t(1ULL << I40E_FILTER_PCTYPE_FCOE_RX) | \\\n+\t(1ULL << I40E_FILTER_PCTYPE_FCOE_OTHER) | \\\n+\t(1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))\n+\n struct i40e_adapter;\n \n TAILQ_HEAD(i40e_mac_filter_list, i40e_mac_filter);\n@@ -253,6 +283,8 @@ struct i40e_vf_tx_queues {\n * Structure to store private data specific for VF instance.\n */\n struct i40e_vf {\n+\tstruct i40e_adapter *adapter; /* The adapter this VF associate to */\n+\tstruct rte_eth_dev_data *dev_data; /* Pointer to the device data */\n \tuint16_t num_queue_pairs;\n \tuint16_t max_pkt_len; /* Maximum packet length */\n \tbool promisc_unicast_enabled;\n@@ -310,8 +342,10 @@ int i40e_dev_link_update(struct rte_eth_dev *dev,\n void i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi);\n void i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi);\n int i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,\n-\t\t\t\tstruct i40e_vsi_vlan_pvid_info *info);\n+\t\t\t struct i40e_vsi_vlan_pvid_info *info);\n int i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on);\n+uint64_t i40e_config_hena(uint64_t flags);\n+uint64_t i40e_parse_hena(uint64_t flags);\n \n /* I40E_DEV_PRIVATE_TO */\n #define I40E_DEV_PRIVATE_TO_PF(adapter) \\\n@@ -361,6 +395,10 @@ i40e_get_vsi_from_adapter(struct i40e_adapter *adapter)\n #define I40E_PF_TO_ADAPTER(pf) \\\n \t((struct i40e_adapter *)pf->adapter)\n \n+/* I40E_VF_TO */\n+#define I40E_VF_TO_HW(vf) \\\n+\t(&(((struct i40e_vf *)vf)->adapter->hw))\n+\n static inline void\n i40e_init_adminq_parameter(struct i40e_hw *hw)\n {\ndiff --git a/lib/librte_pmd_i40e/i40e_ethdev_vf.c b/lib/librte_pmd_i40e/i40e_ethdev_vf.c\nindex 2726bfb..bef34cb 100644\n--- a/lib/librte_pmd_i40e/i40e_ethdev_vf.c\n+++ b/lib/librte_pmd_i40e/i40e_ethdev_vf.c\n@@ -125,6 +125,19 @@ static void i40evf_dev_allmulticast_disable(struct rte_eth_dev *dev);\n static int i40evf_get_link_status(struct rte_eth_dev *dev,\n \t\t\t\t struct rte_eth_link *link);\n static int i40evf_init_vlan(struct rte_eth_dev *dev);\n+static int i40evf_config_rss(struct i40e_vf *vf);\n+static int i40evf_dev_rss_reta_update(struct rte_eth_dev *dev,\n+\t\t\t\t struct rte_eth_rss_reta *reta_conf);\n+static int i40evf_dev_rss_reta_query(struct rte_eth_dev *dev,\n+\t\t\t\t struct rte_eth_rss_reta *reta_conf);\n+static int i40evf_dev_rss_hash_update(struct rte_eth_dev *dev,\n+\t\t\t\t struct rte_eth_rss_conf *rss_conf);\n+static int i40evf_dev_rss_hash_conf_get(struct rte_eth_dev *dev,\n+\t\t\t\t\tstruct rte_eth_rss_conf *rss_conf);\n+\n+/* Default hash key buffer for RSS */\n+static uint32_t rss_key_default[I40E_VFQF_HKEY_MAX_INDEX + 1];\n+\n static struct eth_dev_ops i40evf_eth_dev_ops = {\n \t.dev_configure = i40evf_dev_configure,\n \t.dev_start = i40evf_dev_start,\n@@ -144,6 +157,10 @@ static struct eth_dev_ops i40evf_eth_dev_ops = {\n \t.rx_queue_release = i40e_dev_rx_queue_release,\n \t.tx_queue_setup = i40e_dev_tx_queue_setup,\n \t.tx_queue_release = i40e_dev_tx_queue_release,\n+\t.reta_update = i40evf_dev_rss_reta_update,\n+\t.reta_query = i40evf_dev_rss_reta_query,\n+\t.rss_hash_update = i40evf_dev_rss_hash_update,\n+\t.rss_hash_conf_get = i40evf_dev_rss_hash_conf_get,\n };\n \n static int\n@@ -941,6 +958,8 @@ i40evf_init_vf(struct rte_eth_dev *dev)\n \tstruct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n \tstruct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);\n \n+\tvf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);\n+\tvf->dev_data = dev->data;\n \terr = i40evf_set_mac_type(hw);\n \tif (err) {\n \t\tPMD_INIT_LOG(ERR, \"set_mac_type failed: %d\\n\", err);\n@@ -1194,11 +1213,13 @@ i40evf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)\n static int\n i40evf_rx_init(struct rte_eth_dev *dev)\n {\n+\tstruct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);\n \tuint16_t i, j;\n \tstruct i40e_rx_queue **rxq =\n \t\t(struct i40e_rx_queue **)dev->data->rx_queues;\n \tstruct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n \n+\ti40evf_config_rss(vf);\n \tfor (i = 0; i < dev->data->nb_rx_queues; i++) {\n \t\tif (i40e_alloc_rx_queue_mbufs(rxq[i]) != 0) {\n \t\t\tPMD_DRV_LOG(ERR, \"alloc rx queues mbufs failed\\n\");\n@@ -1445,3 +1466,190 @@ i40evf_dev_close(struct rte_eth_dev *dev)\n \ti40evf_reset_vf(hw);\n \ti40e_shutdown_adminq(hw);\n }\n+\n+static int\n+i40evf_hw_rss_hash_set(struct i40e_hw *hw, struct rte_eth_rss_conf *rss_conf)\n+{\n+\tuint32_t *hash_key;\n+\tuint8_t hash_key_len;\n+\tuint64_t rss_hf, hena;\n+\n+\thash_key = (uint32_t *)(rss_conf->rss_key);\n+\thash_key_len = rss_conf->rss_key_len;\n+\tif (hash_key != NULL && hash_key_len >=\n+\t\t(I40E_VFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {\n+\t\tuint16_t i;\n+\n+\t\tfor (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)\n+\t\t\tI40E_WRITE_REG(hw, I40E_VFQF_HKEY(i), hash_key[i]);\n+\t}\n+\n+\trss_hf = rss_conf->rss_hf;\n+\thena = (uint64_t)I40E_READ_REG(hw, I40E_VFQF_HENA(0));\n+\thena |= ((uint64_t)I40E_READ_REG(hw, I40E_VFQF_HENA(1))) << 32;\n+\thena &= ~I40E_RSS_HENA_ALL;\n+\thena |= i40e_config_hena(rss_hf);\n+\tI40E_WRITE_REG(hw, I40E_VFQF_HENA(0), (uint32_t)hena);\n+\tI40E_WRITE_REG(hw, I40E_VFQF_HENA(1), (uint32_t)(hena >> 32));\n+\tI40EVF_WRITE_FLUSH(hw);\n+\n+\treturn 0;\n+}\n+\n+static void\n+i40evf_disable_rss(struct i40e_vf *vf)\n+{\n+\tstruct i40e_hw *hw = I40E_VF_TO_HW(vf);\n+\tuint64_t hena;\n+\n+\thena = (uint64_t)I40E_READ_REG(hw, I40E_VFQF_HENA(0));\n+\thena |= ((uint64_t)I40E_READ_REG(hw, I40E_VFQF_HENA(1))) << 32;\n+\thena &= ~I40E_RSS_HENA_ALL;\n+\tI40E_WRITE_REG(hw, I40E_VFQF_HENA(0), (uint32_t)hena);\n+\tI40E_WRITE_REG(hw, I40E_VFQF_HENA(1), (uint32_t)(hena >> 32));\n+\tI40EVF_WRITE_FLUSH(hw);\n+}\n+\n+static int\n+i40evf_config_rss(struct i40e_vf *vf)\n+{\n+\tstruct i40e_hw *hw = I40E_VF_TO_HW(vf);\n+\tstruct rte_eth_rss_conf rss_conf;\n+\tuint32_t i, j, lut = 0, nb_q = (I40E_VFQF_HLUT_MAX_INDEX + 1) * 4;\n+\n+\tif (vf->dev_data->dev_conf.rxmode.mq_mode != ETH_MQ_RX_RSS) {\n+\t\ti40evf_disable_rss(vf);\n+\t\tPMD_DRV_LOG(DEBUG, \"RSS not configured\\n\");\n+\t\treturn 0;\n+\t}\n+\n+\t/* Fill out the look up table */\n+\tfor (i = 0, j = 0; i < nb_q; i++, j++) {\n+\t\tif (j >= vf->num_queue_pairs)\n+\t\t\tj = 0;\n+\t\tlut = (lut << 8) | j;\n+\t\tif ((i & 3) == 3)\n+\t\t\tI40E_WRITE_REG(hw, I40E_VFQF_HLUT(i >> 2), lut);\n+\t}\n+\n+\trss_conf = vf->dev_data->dev_conf.rx_adv_conf.rss_conf;\n+\tif ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {\n+\t\ti40evf_disable_rss(vf);\n+\t\tPMD_DRV_LOG(DEBUG, \"No hash flag is set\\n\");\n+\t\treturn 0;\n+\t}\n+\n+\tif (rss_conf.rss_key == NULL || rss_conf.rss_key_len < nb_q) {\n+\t\t/* Calculate the default hash key */\n+\t\tfor (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)\n+\t\t\trss_key_default[i] = (uint32_t)rte_rand();\n+\t\trss_conf.rss_key = (uint8_t *)rss_key_default;\n+\t\trss_conf.rss_key_len = nb_q;\n+\t}\n+\n+\treturn i40evf_hw_rss_hash_set(hw, &rss_conf);\n+}\n+\n+static int\n+i40evf_dev_rss_reta_update(struct rte_eth_dev *dev,\n+\t\t\t struct rte_eth_rss_reta *reta_conf)\n+{\n+\tstruct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n+\tuint8_t i, j, mask, max = ETH_RSS_RETA_NUM_ENTRIES / 2;\n+\tuint32_t lut, l;\n+\n+\tfor (i = 0; i < ETH_RSS_RETA_NUM_ENTRIES; i += 4) {\n+\t\tif (i < max)\n+\t\t\tmask = (uint8_t)((reta_conf->mask_lo >> i) & 0xF);\n+\t\telse\n+\t\t\tmask = (uint8_t)((reta_conf->mask_hi >>\n+\t\t\t\t\t\t(i - max)) & 0xF);\n+\t\tif (!mask)\n+\t\t\tcontinue;\n+\t\tif (mask == 0xf)\n+\t\t\tl = 0;\n+\t\telse\n+\t\t\tl = I40E_READ_REG(hw, I40E_VFQF_HLUT(i >> 2));\n+\n+\t\tfor (j = 0, lut = 0; j < 4; j++) {\n+\t\t\tif (mask & (0x1 << j))\n+\t\t\t\tlut |= reta_conf->reta[i + j] << (8 * j);\n+\t\t\telse\n+\t\t\t\tlut |= l & (0xff << (8 * j));\n+\t\t}\n+\t\tI40E_WRITE_REG(hw, I40E_VFQF_HLUT(i >> 2), lut);\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int\n+i40evf_dev_rss_reta_query(struct rte_eth_dev *dev,\n+\t\t\t struct rte_eth_rss_reta *reta_conf)\n+{\n+\tstruct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n+\tuint8_t i, j, mask, max = ETH_RSS_RETA_NUM_ENTRIES / 2;\n+\tuint32_t lut;\n+\n+\tfor (i = 0; i < ETH_RSS_RETA_NUM_ENTRIES; i += 4) {\n+\t\tif (i < max)\n+\t\t\tmask = (uint8_t)((reta_conf->mask_lo >> i) & 0xF);\n+\t\telse\n+\t\t\tmask = (uint8_t)((reta_conf->mask_hi >>\n+\t\t\t\t\t\t(i - max)) & 0xF);\n+\t\tif (!mask)\n+\t\t\tcontinue;\n+\t\tlut = I40E_READ_REG(hw, I40E_VFQF_HLUT(i >> 2));\n+\t\tfor (j = 0; j < 4; j++) {\n+\t\t\tif (mask & (0x1 << j))\n+\t\t\t\treta_conf->reta[i + j] =\n+\t\t\t\t\t(uint8_t)((lut >> (8 * j)) & 0xFF);\n+\t\t}\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int\n+i40evf_dev_rss_hash_update(struct rte_eth_dev *dev,\n+\t\t\t struct rte_eth_rss_conf *rss_conf)\n+{\n+\tstruct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n+\tuint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;\n+\tuint64_t hena;\n+\n+\thena = (uint64_t)I40E_READ_REG(hw, I40E_VFQF_HENA(0));\n+\thena |= ((uint64_t)I40E_READ_REG(hw, I40E_VFQF_HENA(1))) << 32;\n+\tif (!(hena & I40E_RSS_HENA_ALL)) { /* RSS disabled */\n+\t\tif (rss_hf != 0) /* Enable RSS */\n+\t\t\treturn -EINVAL;\n+\t\treturn 0;\n+\t}\n+\n+\t/* RSS enabled */\n+\tif (rss_hf == 0) /* Disable RSS */\n+\t\treturn -EINVAL;\n+\n+\treturn i40evf_hw_rss_hash_set(hw, rss_conf);\n+}\n+\n+static int\n+i40evf_dev_rss_hash_conf_get(struct rte_eth_dev *dev,\n+\t\t\t struct rte_eth_rss_conf *rss_conf)\n+{\n+\tstruct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n+\tuint32_t *hash_key = (uint32_t *)(rss_conf->rss_key);\n+\tuint64_t hena;\n+\tuint16_t i;\n+\n+\tif (hash_key) {\n+\t\tfor (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)\n+\t\t\thash_key[i] = I40E_READ_REG(hw, I40E_VFQF_HKEY(i));\n+\t\trss_conf->rss_key_len = i * sizeof(uint32_t);\n+\t}\n+\thena = (uint64_t)I40E_READ_REG(hw, I40E_VFQF_HENA(0));\n+\thena |= ((uint64_t)I40E_READ_REG(hw, I40E_VFQF_HENA(1))) << 32;\n+\trss_conf->rss_hf = i40e_parse_hena(hena);\n+\n+\treturn 0;\n+}\n", "prefixes": [ "dpdk-dev", "1/3" ] }