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Update a patch.
GET /api/patches/50576/?format=api
{ "id": 50576, "url": "http://patches.dpdk.org/api/patches/50576/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20190228055650.25237-18-qi.z.zhang@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20190228055650.25237-18-qi.z.zhang@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20190228055650.25237-18-qi.z.zhang@intel.com", "date": "2019-02-28T05:56:30", "name": "[17/37] net/ice/base: update macros", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": true, "hash": "d3ead778ffdfaf5c3db623e31e2fb9423a05e9ca", "submitter": { "id": 504, "url": "http://patches.dpdk.org/api/people/504/?format=api", "name": "Qi Zhang", "email": "qi.z.zhang@intel.com" }, "delegate": { "id": 319, "url": "http://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20190228055650.25237-18-qi.z.zhang@intel.com/mbox/", "series": [ { "id": 3567, "url": "http://patches.dpdk.org/api/series/3567/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=3567", "date": "2019-02-28T05:56:13", "name": "share code update.", "version": 1, "mbox": "http://patches.dpdk.org/series/3567/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/50576/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/50576/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id B61B45F17;\n\tThu, 28 Feb 2019 06:55:36 +0100 (CET)", "from mga12.intel.com (mga12.intel.com [192.55.52.136])\n\tby dpdk.org (Postfix) with ESMTP id 1F8FF5688\n\tfor <dev@dpdk.org>; Thu, 28 Feb 2019 06:55:27 +0100 (CET)", "from fmsmga006.fm.intel.com ([10.253.24.20])\n\tby fmsmga106.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t27 Feb 2019 21:55:27 -0800", "from dpdk51.sh.intel.com ([10.67.110.190])\n\tby fmsmga006.fm.intel.com with ESMTP; 27 Feb 2019 21:55:26 -0800" ], "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.58,422,1544515200\"; d=\"scan'208\";a=\"322784326\"", "From": "Qi Zhang <qi.z.zhang@intel.com>", "To": "wenzhuo.lu@intel.com,\n\tqiming.yang@intel.com", "Cc": "paul.m.stillwell.jr@intel.com, dev@dpdk.org, ferruh.yigit@intel.com,\n\tQi Zhang <qi.z.zhang@intel.com>", "Date": "Thu, 28 Feb 2019 13:56:30 +0800", "Message-Id": "<20190228055650.25237-18-qi.z.zhang@intel.com>", "X-Mailer": "git-send-email 2.13.6", "In-Reply-To": "<20190228055650.25237-1-qi.z.zhang@intel.com>", "References": "<20190228055650.25237-1-qi.z.zhang@intel.com>", "Subject": "[dpdk-dev] [PATCH 17/37] net/ice/base: update macros", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Update macros for metadata and package flags.\n\nSigned-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>\nSigned-off-by: Qi Zhang <qi.z.zhang@intel.com>\n---\n drivers/net/ice/base/ice_common.c | 36 ++++++++---------\n drivers/net/ice/base/ice_flow.h | 17 ++++++--\n drivers/net/ice/base/ice_lan_tx_rx.h | 77 +++++++++++++++++++++++-------------\n 3 files changed, 80 insertions(+), 50 deletions(-)", "diff": "diff --git a/drivers/net/ice/base/ice_common.c b/drivers/net/ice/base/ice_common.c\nindex 4085ccc12..e0fe06e9c 100644\n--- a/drivers/net/ice/base/ice_common.c\n+++ b/drivers/net/ice/base/ice_common.c\n@@ -365,22 +365,22 @@ static void ice_init_flex_flags(struct ice_hw *hw, enum ice_rxdid prof_id)\n \t */\n \tcase ICE_RXDID_FLEX_NIC:\n \tcase ICE_RXDID_FLEX_NIC_2:\n-\t\tICE_PROG_FLG_ENTRY(hw, prof_id, ICE_RXFLG_PKT_FRG,\n-\t\t\t\t ICE_RXFLG_UDP_GRE, ICE_RXFLG_PKT_DSI,\n-\t\t\t\t ICE_RXFLG_FIN, idx++);\n+\t\tICE_PROG_FLG_ENTRY(hw, prof_id, ICE_FLG_PKT_FRG,\n+\t\t\t\t ICE_FLG_UDP_GRE, ICE_FLG_PKT_DSI,\n+\t\t\t\t ICE_FLG_FIN, idx++);\n \t\t/* flex flag 1 is not used for flexi-flag programming, skipping\n \t\t * these four FLG64 bits.\n \t\t */\n-\t\tICE_PROG_FLG_ENTRY(hw, prof_id, ICE_RXFLG_SYN, ICE_RXFLG_RST,\n-\t\t\t\t ICE_RXFLG_PKT_DSI, ICE_RXFLG_PKT_DSI, idx++);\n-\t\tICE_PROG_FLG_ENTRY(hw, prof_id, ICE_RXFLG_PKT_DSI,\n-\t\t\t\t ICE_RXFLG_PKT_DSI, ICE_RXFLG_EVLAN_x8100,\n-\t\t\t\t ICE_RXFLG_EVLAN_x9100, idx++);\n-\t\tICE_PROG_FLG_ENTRY(hw, prof_id, ICE_RXFLG_VLAN_x8100,\n-\t\t\t\t ICE_RXFLG_TNL_VLAN, ICE_RXFLG_TNL_MAC,\n-\t\t\t\t ICE_RXFLG_TNL0, idx++);\n-\t\tICE_PROG_FLG_ENTRY(hw, prof_id, ICE_RXFLG_TNL1, ICE_RXFLG_TNL2,\n-\t\t\t\t ICE_RXFLG_PKT_DSI, ICE_RXFLG_PKT_DSI, idx);\n+\t\tICE_PROG_FLG_ENTRY(hw, prof_id, ICE_FLG_SYN, ICE_FLG_RST,\n+\t\t\t\t ICE_FLG_PKT_DSI, ICE_FLG_PKT_DSI, idx++);\n+\t\tICE_PROG_FLG_ENTRY(hw, prof_id, ICE_FLG_PKT_DSI,\n+\t\t\t\t ICE_FLG_PKT_DSI, ICE_FLG_EVLAN_x8100,\n+\t\t\t\t ICE_FLG_EVLAN_x9100, idx++);\n+\t\tICE_PROG_FLG_ENTRY(hw, prof_id, ICE_FLG_VLAN_x8100,\n+\t\t\t\t ICE_FLG_TNL_VLAN, ICE_FLG_TNL_MAC,\n+\t\t\t\t ICE_FLG_TNL0, idx++);\n+\t\tICE_PROG_FLG_ENTRY(hw, prof_id, ICE_FLG_TNL1, ICE_FLG_TNL2,\n+\t\t\t\t ICE_FLG_PKT_DSI, ICE_FLG_PKT_DSI, idx);\n \t\tbreak;\n \n \tdefault:\n@@ -399,17 +399,17 @@ static void ice_init_flex_flags(struct ice_hw *hw, enum ice_rxdid prof_id)\n */\n static void ice_init_flex_flds(struct ice_hw *hw, enum ice_rxdid prof_id)\n {\n-\tenum ice_flex_rx_mdid mdid;\n+\tenum ice_flex_mdid mdid;\n \n \tswitch (prof_id) {\n \tcase ICE_RXDID_FLEX_NIC:\n \tcase ICE_RXDID_FLEX_NIC_2:\n-\t\tICE_PROG_FLEX_ENTRY(hw, prof_id, ICE_RX_MDID_HASH_LOW, 0);\n-\t\tICE_PROG_FLEX_ENTRY(hw, prof_id, ICE_RX_MDID_HASH_HIGH, 1);\n-\t\tICE_PROG_FLEX_ENTRY(hw, prof_id, ICE_RX_MDID_FLOW_ID_LOWER, 2);\n+\t\tICE_PROG_FLEX_ENTRY(hw, prof_id, ICE_MDID_RX_HASH_LOW, 0);\n+\t\tICE_PROG_FLEX_ENTRY(hw, prof_id, ICE_MDID_RX_HASH_HIGH, 1);\n+\t\tICE_PROG_FLEX_ENTRY(hw, prof_id, ICE_MDID_FLOW_ID_LOWER, 2);\n \n \t\tmdid = (prof_id == ICE_RXDID_FLEX_NIC_2) ?\n-\t\t\tICE_RX_MDID_SRC_VSI : ICE_RX_MDID_FLOW_ID_HIGH;\n+\t\t\tICE_MDID_SRC_VSI : ICE_MDID_FLOW_ID_HIGH;\n \n \t\tICE_PROG_FLEX_ENTRY(hw, prof_id, mdid, 3);\n \ndiff --git a/drivers/net/ice/base/ice_flow.h b/drivers/net/ice/base/ice_flow.h\nindex 265e1ee3e..3db10cd6f 100644\n--- a/drivers/net/ice/base/ice_flow.h\n+++ b/drivers/net/ice/base/ice_flow.h\n@@ -278,14 +278,23 @@ enum ice_flow_action_type {\n \tICE_FLOW_ACT_NOP,\n \tICE_FLOW_ACT_ALLOW,\n \tICE_FLOW_ACT_DROP,\n-\tICE_FLOW_ACT_COUNT,\n+\tICE_FLOW_ACT_CNTR_PKT,\n \tICE_FLOW_ACT_FWD_VSI,\n \tICE_FLOW_ACT_FWD_VSI_LIST,\t/* Should be abstracted away */\n \tICE_FLOW_ACT_FWD_QUEUE,\t\t/* Can Queues be abstracted away? */\n \tICE_FLOW_ACT_FWD_QUEUE_GROUP,\t/* Can Queues be abstracted away? */\n-\tICE_FLOW_ACTION_PUSH,\n-\tICE_FLOW_ACTION_POP,\n-\tICE_FLOW_ACTION_MODIFY,\n+\tICE_FLOW_ACT_PUSH,\n+\tICE_FLOW_ACT_POP,\n+\tICE_FLOW_ACT_MODIFY,\n+\tICE_FLOW_ACT_CNTR_BYTES,\n+\tICE_FLOW_ACT_CNTR_PKT_BYTES,\n+\tICE_FLOW_ACT_GENERIC_0,\n+\tICE_FLOW_ACT_GENERIC_1,\n+\tICE_FLOW_ACT_GENERIC_2,\n+\tICE_FLOW_ACT_GENERIC_3,\n+\tICE_FLOW_ACT_GENERIC_4,\n+\tICE_FLOW_ACT_RPT_FLOW_ID,\n+\tICE_FLOW_ACT_BUILD_PROF_IDX,\n };\n \n struct ice_flow_action {\ndiff --git a/drivers/net/ice/base/ice_lan_tx_rx.h b/drivers/net/ice/base/ice_lan_tx_rx.h\nindex 4a1ea0c7d..b1963b5eb 100644\n--- a/drivers/net/ice/base/ice_lan_tx_rx.h\n+++ b/drivers/net/ice/base/ice_lan_tx_rx.h\n@@ -627,39 +627,60 @@ enum ice_flex_opcode {\n \tICE_RX_OPC_PROTID\n };\n \n-/* Receive Descriptor MDID values */\n-enum ice_flex_rx_mdid {\n-\tICE_RX_MDID_FLOW_ID_LOWER\t= 5,\n-\tICE_RX_MDID_FLOW_ID_HIGH,\n-\tICE_RX_MDID_DST_VSI\t\t= 13,\n-\tICE_RX_MDID_SRC_VSI\t\t= 19,\n-\tICE_RX_MDID_HASH_LOW\t\t= 56,\n-\tICE_RX_MDID_HASH_HIGH,\n-\tICE_RX_MDID_ACL_CTR0\t\t= ICE_RX_MDID_HASH_LOW,\n-\tICE_RX_MDID_ACL_CTR1\t\t= ICE_RX_MDID_HASH_HIGH,\n-\tICE_RX_MDID_ACL_CTR2\t\t= 59\n+/* Receive Descriptor MDID values that access packet flags */\n+enum ice_flex_mdid_pkt_flags {\n+\tICE_RX_MDID_PKT_FLAGS_15_0\t= 20,\n+\tICE_RX_MDID_PKT_FLAGS_31_16,\n+\tICE_RX_MDID_PKT_FLAGS_47_32,\n+\tICE_RX_MDID_PKT_FLAGS_63_48,\n+};\n+\n+/* Generic descriptor MDID values */\n+enum ice_flex_mdid {\n+\tICE_MDID_GENERIC_WORD_0,\n+\tICE_MDID_GENERIC_WORD_1,\n+\tICE_MDID_GENERIC_WORD_2,\n+\tICE_MDID_GENERIC_WORD_3,\n+\tICE_MDID_GENERIC_WORD_4,\n+\tICE_MDID_FLOW_ID_LOWER,\n+\tICE_MDID_FLOW_ID_HIGH,\n+\tICE_MDID_RX_DESCR_PROF_IDX,\n+\tICE_MDID_RX_PKT_DROP,\n+\tICE_MDID_RX_DST_Q\t\t= 12,\n+\tICE_MDID_RX_DST_VSI,\n+\tICE_MDID_SRC_VSI\t\t= 19,\n+\tICE_MDID_ACL_NOP\t\t= 55,\n+\t/* Entry 56 */\n+\tICE_MDID_RX_HASH_LOW,\n+\tICE_MDID_ACL_CNTR_PKT\t\t= ICE_MDID_RX_HASH_LOW,\n+\t/* Entry 57 */\n+\tICE_MDID_RX_HASH_HIGH,\n+\tICE_MDID_ACL_CNTR_BYTES\t\t= ICE_MDID_RX_HASH_HIGH,\n+\tICE_MDID_ACL_CNTR_PKT_BYTES\n };\n \n /* for ice_32byte_rx_flex_desc.mir_id_umb_cast member */\n #define ICE_RX_FLEX_DESC_MIRROR_M\t(0x3F) /* 6-bits */\n \n-/* Rx Flag64 packet flag bits */\n-enum ice_rx_flg64_bits {\n-\tICE_RXFLG_PKT_DSI\t= 0,\n-\tICE_RXFLG_EVLAN_x8100\t= 15,\n-\tICE_RXFLG_EVLAN_x9100,\n-\tICE_RXFLG_VLAN_x8100,\n-\tICE_RXFLG_TNL_MAC\t= 22,\n-\tICE_RXFLG_TNL_VLAN,\n-\tICE_RXFLG_PKT_FRG,\n-\tICE_RXFLG_FIN\t\t= 32,\n-\tICE_RXFLG_SYN,\n-\tICE_RXFLG_RST,\n-\tICE_RXFLG_TNL0\t\t= 38,\n-\tICE_RXFLG_TNL1,\n-\tICE_RXFLG_TNL2,\n-\tICE_RXFLG_UDP_GRE,\n-\tICE_RXFLG_RSVD\t\t= 63\n+/* Rx/Tx Flag64 packet flag bits */\n+enum ice_flg64_bits {\n+\tICE_FLG_PKT_DSI\t\t= 0,\n+\t/* If there is a 1 in this bit position then that means Rx packet */\n+\tICE_FLG_PKT_DIR\t\t= 4,\n+\tICE_FLG_EVLAN_x8100\t= 15,\n+\tICE_FLG_EVLAN_x9100,\n+\tICE_FLG_VLAN_x8100,\n+\tICE_FLG_TNL_MAC\t\t= 22,\n+\tICE_FLG_TNL_VLAN,\n+\tICE_FLG_PKT_FRG,\n+\tICE_FLG_FIN\t\t= 32,\n+\tICE_FLG_SYN,\n+\tICE_FLG_RST,\n+\tICE_FLG_TNL0\t\t= 38,\n+\tICE_FLG_TNL1,\n+\tICE_FLG_TNL2,\n+\tICE_FLG_UDP_GRE,\n+\tICE_FLG_RSVD\t\t= 63\n };\n \n enum ice_rx_flex_desc_umb_cast_bits { /* field is 2 bits long */\n", "prefixes": [ "17/37" ] }