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GET /api/patches/47155/?format=api
{ "id": 47155, "url": "http://patches.dpdk.org/api/patches/47155/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20181022133021.11264-15-g.singh@nxp.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20181022133021.11264-15-g.singh@nxp.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20181022133021.11264-15-g.singh@nxp.com", "date": "2018-10-22T13:31:30", "name": "[v3,14/15] doc: add caam jr cryptodev details", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "5fcaf7b4507a776b38a77c5b6e713b952b764827", "submitter": { "id": 1068, "url": "http://patches.dpdk.org/api/people/1068/?format=api", "name": "Gagandeep Singh", "email": "g.singh@nxp.com" }, "delegate": { "id": 6690, "url": "http://patches.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20181022133021.11264-15-g.singh@nxp.com/mbox/", "series": [ { "id": 2011, "url": "http://patches.dpdk.org/api/series/2011/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=2011", "date": "2018-10-22T13:31:00", "name": "Introducing the NXP CAAM job ring driver", "version": 3, "mbox": "http://patches.dpdk.org/series/2011/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/47155/comments/", "check": "pending", "checks": "http://patches.dpdk.org/api/patches/47155/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 02CF94CA7;\n\tMon, 22 Oct 2018 15:31:46 +0200 (CEST)", "from EUR02-HE1-obe.outbound.protection.outlook.com\n\t(mail-eopbgr10048.outbound.protection.outlook.com [40.107.1.48])\n\tby dpdk.org (Postfix) with ESMTP id 6D5365F44\n\tfor <dev@dpdk.org>; Mon, 22 Oct 2018 15:31:32 +0200 (CEST)", "from HE1PR04MB1530.eurprd04.prod.outlook.com (10.164.48.20) by\n\tHE1PR04MB3131.eurprd04.prod.outlook.com (10.171.196.142) with\n\tMicrosoft SMTP Server (version=TLS1_2,\n\tcipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id\n\t15.20.1250.30; Mon, 22 Oct 2018 13:31:31 +0000", "from HE1PR04MB1530.eurprd04.prod.outlook.com\n\t([fe80::95cd:198:d5c5:59a4]) by\n\tHE1PR04MB1530.eurprd04.prod.outlook.com\n\t([fe80::95cd:198:d5c5:59a4%5]) with mapi id 15.20.1250.028;\n\tMon, 22 Oct 2018 13:31:31 +0000" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=nxp.com; s=selector1;\n\th=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n\tbh=ZAqpx/gYV/ROjiNefU1jjTOHFNFd5AQB9UYAkF/c3Jk=;\n\tb=xL08J8TXnSDkt/zP9b6/iC33K8yve0RJGdRpRb7/+ckiMCbVw4PUs2bV5klIuKAqh7bPaGLjJIQkPcl+jTQB14M6P/jMsBNLTE+91dlFRfBeAjQP8AARhtIDD0CkFqQKf+WjDr5RyU1hZvMDPQ4+1hkMGK4s0XjrcQrPm9KaZs0=", "From": "Gagandeep Singh <G.Singh@nxp.com>", "To": "\"dev@dpdk.org\" <dev@dpdk.org>, Akhil Goyal <akhil.goyal@nxp.com>", "CC": "Hemant Agrawal <hemant.agrawal@nxp.com>", "Thread-Topic": "[PATCH v3 14/15] doc: add caam jr cryptodev details", "Thread-Index": "AQHUaguKG1tFonT0u0eyiqUf2vRUVA==", "Date": "Mon, 22 Oct 2018 13:31:30 +0000", "Message-ID": "<20181022133021.11264-15-g.singh@nxp.com>", "References": "<20181012144055.9461-1-g.singh@nxp.com>\n\t<20181022133021.11264-1-g.singh@nxp.com>", "In-Reply-To": "<20181022133021.11264-1-g.singh@nxp.com>", "Accept-Language": "en-US", "Content-Language": "en-US", "X-MS-Has-Attach": "", "X-MS-TNEF-Correlator": "", "x-clientproxiedby": "BM1PR0101CA0016.INDPRD01.PROD.OUTLOOK.COM\n\t(2603:1096:b00:18::26) To HE1PR04MB1530.eurprd04.prod.outlook.com\n\t(2a01:111:e400:59a8::20)", "authentication-results": "spf=none (sender IP is )\n\tsmtp.mailfrom=G.Singh@nxp.com; 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SFP:1101; SCL:1; SRVR:HE1PR04MB3131;\n\tH:HE1PR04MB1530.eurprd04.prod.outlook.com; FPR:; SPF:None; LANG:en;\n\tPTR:InfoNoRecords; MX:1; A:1; ", "received-spf": "None (protection.outlook.com: nxp.com does not designate\n\tpermitted sender hosts)", "x-microsoft-antispam-message-info": "WR+qhbUviiVNpgKgu/okb+sW5SAgJHNMHQi/jgaMIyR1Npg89L5VnJt381AKsl3zZPuz1kc1135QjX8QYftxHAuU6FQHET9AOUEi9KB0Ks+T5xlS9cbNt/W0ic3LlMNNQ3me+dDFarifRAkiafg/hwJoJnqtWeh4gtcxT+xuz4IMUA4i3jJaR3dy0q4PbpDER90nMUjL7E9I1RO3dhvRWKdxdhva6HYwMUFC7wvkAbfaHNB7FPIDiX/vlOYakQgEDuWmNnXnwQBBJ55cFWWPgBLKbyg/rlFUselVht3alP0RmdOAXmzuszmTVw/7VkFYgBfs30UrWONI4uKjvyZnKWkfSc/DK0xhNtD7NSra2nk=", "spamdiagnosticoutput": "1:99", "spamdiagnosticmetadata": "NSPM", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-ID": "<35BAC3E6D3883E45BBAB1CA87820358F@eurprd04.prod.outlook.com>", "Content-Transfer-Encoding": "base64", "MIME-Version": "1.0", "X-OriginatorOrg": "nxp.com", "X-MS-Exchange-CrossTenant-Network-Message-Id": "d8467e10-8fa7-4616-c820-08d63822ad16", "X-MS-Exchange-CrossTenant-originalarrivaltime": "22 Oct 2018 13:31:30.8803\n\t(UTC)", "X-MS-Exchange-CrossTenant-fromentityheader": "Hosted", "X-MS-Exchange-CrossTenant-id": "686ea1d3-bc2b-4c6f-a92c-d99c5c301635", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "HE1PR04MB3131", "Subject": "[dpdk-dev] [PATCH v3 14/15] doc: add caam jr cryptodev details", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Hemant Agrawal <hemant.agrawal@nxp.com>\n\nadd caam jr driver details, supported features and algorithms\nin the document.\n\nrelease note and MAINTAINERS are also updated.\n\nSigned-off-by: Hemant Agrawal <hemant.agrawal@nxp.com>\nAcked-by: Akhil Goyal <akhil.goyal@nxp.com>\n---\n MAINTAINERS | 2 +\n doc/guides/cryptodevs/caam_jr.rst | 150 +++++++++++++++++++++\n doc/guides/cryptodevs/features/caam_jr.ini | 46 +++++++\n doc/guides/cryptodevs/index.rst | 1 +\n doc/guides/rel_notes/release_18_11.rst | 5 +\n 5 files changed, 204 insertions(+)\n create mode 100644 doc/guides/cryptodevs/caam_jr.rst\n create mode 100644 doc/guides/cryptodevs/features/caam_jr.ini", "diff": "diff --git a/MAINTAINERS b/MAINTAINERS\r\nindex 9de01189a..3079c187e 100644\r\n--- a/MAINTAINERS\r\n+++ b/MAINTAINERS\r\n@@ -855,6 +855,8 @@ NXP CAAM JR\r\n M: Gagandeep Singh <g.singh@nxp.com>\r\n M: Hemant Agrawal <hemant.agrawal@nxp.com>\r\n F: drivers/crypto/caam_jr/\r\n+F: doc/guides/cryptodevs/caam_jr.rst\r\n+F: doc/guides/cryptodevs/features/caam_jr.ini\r\n \r\n NXP DPAA_SEC\r\n M: Akhil Goyal <akhil.goyal@nxp.com>\r\ndiff --git a/doc/guides/cryptodevs/caam_jr.rst b/doc/guides/cryptodevs/caam_jr.rst\r\nnew file mode 100644\r\nindex 000000000..e87ff0915\r\n--- /dev/null\r\n+++ b/doc/guides/cryptodevs/caam_jr.rst\r\n@@ -0,0 +1,150 @@\r\n+.. SPDX-License-Identifier: BSD-3-Clause\r\n+ Copyright 2018 NXP\r\n+\r\n+\r\n+NXP CAAM JOB RING (caam_jr)\r\n+===========================\r\n+\r\n+The caam_jr PMD provides poll mode crypto driver support for NXP SEC 4.x+ (CAAM)\r\n+hardware accelerator. More information is available at:\r\n+\r\n+`NXP Cryptographic Acceleration Technology <https://www.nxp.com/applications/solutions/internet-of-things/secure-things/network-security-technology/cryptographic-acceleration-technology:NETWORK_SECURITY_CRYPTOG>`_.\r\n+\r\n+Architecture\r\n+------------\r\n+\r\n+SEC is the SOC's security engine, which serves as NXP's latest cryptographic\r\n+acceleration and offloading hardware. It combines functions previously\r\n+implemented in separate modules to create a modular and scalable acceleration\r\n+and assurance engine. It also implements block encryption algorithms, stream\r\n+cipher algorithms, hashing algorithms, public key algorithms, run-time\r\n+integrity checking, and a hardware random number generator. SEC performs\r\n+higher-level cryptographic operations than previous NXP cryptographic\r\n+accelerators. This provides significant improvement to system level performance.\r\n+\r\n+SEC HW accelerator above 4.x+ version are also known as CAAM.\r\n+\r\n+caam_jr PMD is one of DPAA drivers which uses uio interface to interact with\r\n+Linux kernel for configure and destroy the device instance (ring).\r\n+\r\n+\r\n+Implementation\r\n+--------------\r\n+\r\n+SEC provides platform assurance by working with SecMon, which is a companion\r\n+logic block that tracks the security state of the SOC. SEC is programmed by\r\n+means of descriptors (not to be confused with frame descriptors (FDs)) that\r\n+indicate the operations to be performed and link to the message and\r\n+associated data. SEC incorporates two DMA engines to fetch the descriptors,\r\n+read the message data, and write the results of the operations. The DMA\r\n+engine provides a scatter/gather capability so that SEC can read and write\r\n+data scattered in memory. SEC may be configured by means of software for\r\n+dynamic changes in byte ordering. The default configuration for this version\r\n+of SEC is little-endian mode.\r\n+\r\n+Note that one physical Job Ring represent one caam_jr device.\r\n+\r\n+Features\r\n+--------\r\n+\r\n+The CAAM_JR PMD has support for:\r\n+\r\n+Cipher algorithms:\r\n+\r\n+* ``RTE_CRYPTO_CIPHER_3DES_CBC``\r\n+* ``RTE_CRYPTO_CIPHER_AES128_CBC``\r\n+* ``RTE_CRYPTO_CIPHER_AES192_CBC``\r\n+* ``RTE_CRYPTO_CIPHER_AES256_CBC``\r\n+* ``RTE_CRYPTO_CIPHER_AES128_CTR``\r\n+* ``RTE_CRYPTO_CIPHER_AES192_CTR``\r\n+* ``RTE_CRYPTO_CIPHER_AES256_CTR``\r\n+\r\n+Hash algorithms:\r\n+\r\n+* ``RTE_CRYPTO_AUTH_SHA1_HMAC``\r\n+* ``RTE_CRYPTO_AUTH_SHA224_HMAC``\r\n+* ``RTE_CRYPTO_AUTH_SHA256_HMAC``\r\n+* ``RTE_CRYPTO_AUTH_SHA384_HMAC``\r\n+* ``RTE_CRYPTO_AUTH_SHA512_HMAC``\r\n+* ``RTE_CRYPTO_AUTH_MD5_HMAC``\r\n+\r\n+AEAD algorithms:\r\n+\r\n+* ``RTE_CRYPTO_AEAD_AES_GCM``\r\n+\r\n+Supported DPAA SoCs\r\n+--------------------\r\n+\r\n+* LS1046A/LS1026A\r\n+* LS1043A/LS1023A\r\n+* LS1028A\r\n+* LS1012A\r\n+\r\n+Limitations\r\n+-----------\r\n+\r\n+* Hash followed by Cipher mode is not supported\r\n+* Only supports the session-oriented API implementation (session-less APIs are not supported).\r\n+\r\n+Prerequisites\r\n+-------------\r\n+\r\n+caam_jr driver has following dependencies are not part of DPDK and must be installed separately:\r\n+\r\n+* **NXP Linux SDK**\r\n+\r\n+ NXP Linux software development kit (SDK) includes support for the family\r\n+ of QorIQ® ARM-Architecture-based system on chip (SoC) processors\r\n+ and corresponding boards.\r\n+\r\n+ It includes the Linux board support packages (BSPs) for NXP SoCs,\r\n+ a fully operational tool chain, kernel and board specific modules.\r\n+\r\n+ SDK and related information can be obtained from: `NXP QorIQ SDK <http://www.nxp.com/products/software-and-tools/run-time-software/linux-sdk/linux-sdk-for-qoriq-processors:SDKLINUX>`_.\r\n+\r\n+Currently supported by DPDK:\r\n+\r\n+* NXP SDK **18.09+**.\r\n+* Supported architectures: **arm64 LE**.\r\n+\r\n+* Follow the DPDK :ref:`Getting Started Guide for Linux <linux_gsg>` to setup the basic DPDK environment.\r\n+\r\n+Pre-Installation Configuration\r\n+------------------------------\r\n+\r\n+Config File Options\r\n+~~~~~~~~~~~~~~~~~~~\r\n+\r\n+The following options can be modified in the ``config`` file\r\n+to enable caam_jr PMD.\r\n+\r\n+Please note that enabling debugging options may affect system performance.\r\n+\r\n+* ``CONFIG_RTE_LIBRTE_PMD_CAAM_JR`` (default ``n``)\r\n+ By default it is only enabled in common_linuxapp config.\r\n+ Toggle compilation of the ``librte_pmd_caam_jr`` driver.\r\n+\r\n+* ``CONFIG_RTE_LIBRTE_PMD_CAAM_JR_BE`` (default ``n``)\r\n+ By default it is disabled.\r\n+ It can be used when the underlying hardware supports the CAAM in BE mode.\r\n+ e.g. LS1043A, LS1046A supports CAAM in BE mode.\r\n+ BE mode is enabled by default in defconfig-arm64-dpaa-linuxapp-gcc.\r\n+\r\n+Installations\r\n+-------------\r\n+To compile the caam_jr PMD for Linux arm64 gcc target, run the\r\n+following ``make`` command:\r\n+\r\n+.. code-block:: console\r\n+\r\n+ cd <DPDK-source-directory>\r\n+ make config T=arm64-armv8a-linuxapp-gcc install\r\n+\r\n+Enabling logs\r\n+-------------\r\n+\r\n+For enabling logs, use the following EAL parameter:\r\n+\r\n+.. code-block:: console\r\n+\r\n+ ./your_crypto_application <EAL args> --log-level=pmd.crypto.caam,<level>\r\ndiff --git a/doc/guides/cryptodevs/features/caam_jr.ini b/doc/guides/cryptodevs/features/caam_jr.ini\r\nnew file mode 100644\r\nindex 000000000..68f8d8195\r\n--- /dev/null\r\n+++ b/doc/guides/cryptodevs/features/caam_jr.ini\r\n@@ -0,0 +1,46 @@\r\n+;\r\n+; Supported features of the 'caam_jr' crypto driver.\r\n+;\r\n+; Refer to default.ini for the full list of available PMD features.\r\n+;\r\n+[Features]\r\n+Symmetric crypto = Y\r\n+Sym operation chaining = Y\r\n+HW Accelerated = Y\r\n+Protocol offload = Y\r\n+In Place SGL = Y\r\n+OOP SGL In SGL Out = Y\r\n+OOP SGL In LB Out = Y\r\n+OOP LB In SGL Out = Y\r\n+OOP LB In LB Out = Y\r\n+\r\n+;\r\n+; Supported crypto algorithms of the 'dpaa2_sec' crypto driver.\r\n+;\r\n+[Cipher]\r\n+AES CBC (128) = Y\r\n+AES CBC (192) = Y\r\n+AES CBC (256) = Y\r\n+AES CTR (128) = Y\r\n+AES CTR (192) = Y\r\n+AES CTR (256) = Y\r\n+3DES CBC = Y\r\n+\r\n+;\r\n+; Supported authentication algorithms of the 'dpaa2_sec' crypto driver.\r\n+;\r\n+[Auth]\r\n+MD5 HMAC = Y\r\n+SHA1 HMAC = Y\r\n+SHA224 HMAC = Y\r\n+SHA256 HMAC = Y\r\n+SHA384 HMAC = Y\r\n+SHA512 HMAC = Y\r\n+\r\n+;\r\n+; Supported AEAD algorithms of the 'dpaa2_sec' crypto driver.\r\n+;\r\n+[AEAD]\r\n+AES GCM (128) = Y\r\n+AES GCM (192) = Y\r\n+AES GCM (256) = Y\r\ndiff --git a/doc/guides/cryptodevs/index.rst b/doc/guides/cryptodevs/index.rst\r\nindex bd1588537..83610e64f 100644\r\n--- a/doc/guides/cryptodevs/index.rst\r\n+++ b/doc/guides/cryptodevs/index.rst\r\n@@ -13,6 +13,7 @@ Crypto Device Drivers\r\n aesni_mb\r\n aesni_gcm\r\n armv8\r\n+ caam_jr\r\n ccp\r\n dpaa2_sec\r\n dpaa_sec\r\ndiff --git a/doc/guides/rel_notes/release_18_11.rst b/doc/guides/rel_notes/release_18_11.rst\r\nindex a0dd1bed9..af9a6f89f 100644\r\n--- a/doc/guides/rel_notes/release_18_11.rst\r\n+++ b/doc/guides/rel_notes/release_18_11.rst\r\n@@ -186,6 +186,11 @@ New Features\r\n The AESNI MB PMD has been updated with additional support for AES-GCM\r\n algorithm support.\r\n \r\n+* **Added NXP CAAM JR PMD.**\r\n+\r\n+ Added the new caam job ring driver for NXP platforms. See the\r\n+ \"NXP CAAM JOB RING (caam_jr)\" document for more details on this new driver.\r\n+\r\n API Changes\r\n -----------\r\n \r\n", "prefixes": [ "v3", "14/15" ] }