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Update a patch.
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Update a patch.
GET /api/patches/46342/?format=api
{ "id": 46342, "url": "http://patches.dpdk.org/api/patches/46342/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1539076076-19786-22-git-send-email-anoob.joseph@caviumnetworks.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1539076076-19786-22-git-send-email-anoob.joseph@caviumnetworks.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1539076076-19786-22-git-send-email-anoob.joseph@caviumnetworks.com", "date": "2018-10-09T09:07:54", "name": "[v4,21/23] crypto/octeontx: add dequeue burst op", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "56b461080208a7f15eef29d3795576f5e6746969", "submitter": { "id": 893, "url": "http://patches.dpdk.org/api/people/893/?format=api", "name": "Anoob Joseph", "email": "anoob.joseph@caviumnetworks.com" }, "delegate": { "id": 6690, "url": "http://patches.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1539076076-19786-22-git-send-email-anoob.joseph@caviumnetworks.com/mbox/", "series": [ { "id": 1770, "url": "http://patches.dpdk.org/api/series/1770/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=1770", "date": "2018-10-09T09:07:33", "name": "Adding Cavium's OCTEON TX crypto PMD", "version": 4, "mbox": "http://patches.dpdk.org/series/1770/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/46342/comments/", "check": "fail", "checks": "http://patches.dpdk.org/api/patches/46342/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id AB7811B3A8;\n\tTue, 9 Oct 2018 11:10:14 +0200 (CEST)", "from NAM03-DM3-obe.outbound.protection.outlook.com\n\t(mail-dm3nam03on0081.outbound.protection.outlook.com [104.47.41.81])\n\tby dpdk.org (Postfix) with ESMTP id EC37C1B179\n\tfor <dev@dpdk.org>; Tue, 9 Oct 2018 11:10:06 +0200 (CEST)", "from ajoseph83.caveonetworks.com.com (115.113.156.2) by\n\tBN7PR07MB4897.namprd07.prod.outlook.com (2603:10b6:406:ef::26) with\n\tMicrosoft SMTP Server (version=TLS1_2,\n\tcipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id\n\t15.20.1207.28; Tue, 9 Oct 2018 09:10:02 +0000" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=CAVIUMNETWORKS.onmicrosoft.com; s=selector1-cavium-com;\n\th=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n\tbh=vxb29upSPMg6vfhE90hX6oCxvTqEXVDlVZwx12PmQso=;\n\tb=Wy9apppnIPle9GMXOaRwerjeI2aApVQCOfMJUx60qCmZcXpMdAaPFwvOq2XAGRIOcYbkDu8cXlwhqJ9X2tbnubFBEf8gyNAKXVJ9SoVGOItpsrF9BlnxvQ/Xxdbif8H7nYygDO8qcx706aGkOq9OfegjBENOJaENHlsVOQ60KHM=", "Authentication-Results": "spf=none (sender IP is )\n\tsmtp.mailfrom=Anoob.Joseph@cavium.com; ", "From": "Anoob Joseph <anoob.joseph@caviumnetworks.com>", "To": "Akhil Goyal <akhil.goyal@nxp.com>,\n\tPablo de Lara <pablo.de.lara.guarch@intel.com>,\n\tThomas Monjalon <thomas@monjalon.net>", "Cc": "Tejasree Kondoj <kondoj.tejasree@caviumnetworks.com>,\n\tJerin Jacob <jerin.jacob@caviumnetworks.com>,\n\tNarayana Prasad <narayanaprasad.athreya@caviumnetworks.com>,\n\tAnkur Dwivedi <ankur.dwivedi@caviumnetworks.com>,\n\tAnoob Joseph <anoob.joseph@caviumnetworks.com>,\n\tMurthy NSSR <nidadavolu.murthy@caviumnetworks.com>,\n\tNithin Dabilpuram <nithin.dabilpuram@caviumnetworks.com>,\n\tRagothaman Jayaraman <rjayaraman@caviumnetworks.com>,\n\tSrisivasubramanian S <ssrinivasan@caviumnetworks.com>, dev@dpdk.org", "Date": "Tue, 9 Oct 2018 14:37:54 +0530", "Message-Id": "<1539076076-19786-22-git-send-email-anoob.joseph@caviumnetworks.com>", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": "<1539076076-19786-1-git-send-email-anoob.joseph@caviumnetworks.com>", "References": "<1538744363-30340-1-git-send-email-anoob.joseph@caviumnetworks.com>\n\t<1539076076-19786-1-git-send-email-anoob.joseph@caviumnetworks.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Originating-IP": "[115.113.156.2]", "X-ClientProxiedBy": "PN1PR0101CA0004.INDPRD01.PROD.OUTLOOK.COM\n\t(2603:1096:c00:e::14) To BN7PR07MB4897.namprd07.prod.outlook.com\n\t(2603:10b6:406:ef::26)", "X-MS-PublicTrafficType": "Email", "X-MS-Office365-Filtering-Correlation-Id": "031c4ece-4bd5-4f67-48c7-08d62dc700bc", "X-Microsoft-Antispam": "BCL:0; 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PCL:0;\n\tRULEID:(8211001083)(6040522)(2401047)(5005006)(8121501046)(3002001)(93006095)(10201501046)(3231355)(944501410)(52105095)(149066)(150057)(6041310)(20161123560045)(201703131423095)(201702281528075)(20161123555045)(201703061421075)(201703061406153)(20161123562045)(20161123564045)(20161123558120)(201708071742011)(7699051);\n\tSRVR:BN7PR07MB4897; BCL:0; PCL:0; RULEID:; SRVR:BN7PR07MB4897; ", "X-Forefront-PRVS": "08200063E9", "X-Forefront-Antispam-Report": "SFV:NSPM;\n\tSFS:(10009020)(396003)(366004)(376002)(136003)(346002)(39860400002)(199004)(189003)(42882007)(47776003)(106356001)(6666003)(186003)(5660300001)(26005)(68736007)(16526019)(8936002)(25786009)(6116002)(2906002)(81156014)(50226002)(305945005)(81166006)(7736002)(3846002)(105586002)(478600001)(8676002)(54906003)(110136005)(48376002)(16586007)(14444005)(6486002)(6506007)(50466002)(316002)(53936002)(386003)(51416003)(52116002)(76176011)(11346002)(6512007)(44832011)(446003)(36756003)(55236004)(956004)(2616005)(486006)(4326008)(66066001)(97736004)(72206003)(476003);\n\tDIR:OUT; SFP:1101; SCL:1; SRVR:BN7PR07MB4897;\n\tH:ajoseph83.caveonetworks.com.com; FPR:; SPF:None; LANG:en;\n\tPTR:InfoNoRecords; A:1; MX:1; ", "Received-SPF": "None (protection.outlook.com: cavium.com does not designate\n\tpermitted sender hosts)", "X-Microsoft-Antispam-Message-Info": "yBT6EV3lr94rSq3zCkwD1J+22ZnW+75zviot6wT6ou7A8c4XXC+GyUvZAGc4tMUlPiF1dNeHxUEBnD+6PHi0J6vGaUPFpWHFAnSPkcQo5QqP4uX3bXJt/MXYqiygwTOUsgT67Ss8NGG4PKkhngPLiquY8wSfBMAML3T5ry6hP/0W/KhoDw8taGZAOVBg1TijluiWIExiQe0GXCn5s/gljwcDTxHQdBU5J29qhanr4zn/XsJPSnmUDms0i/wm3DnQ8o5jdyceSgSFHBYxNkv/K+c08UNvwCA7EYhxVVlxaNQ4aJAxrvrmL8TIDOzqahyrnGqHIei28jmXRFmsy0MsvXQN9AGTjrUE3/U787WkZ7M=", "SpamDiagnosticOutput": "1:99", "SpamDiagnosticMetadata": "NSPM", "X-OriginatorOrg": "caviumnetworks.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "09 Oct 2018 09:10:02.0051\n\t(UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "031c4ece-4bd5-4f67-48c7-08d62dc700bc", "X-MS-Exchange-CrossTenant-FromEntityHeader": "Hosted", "X-MS-Exchange-CrossTenant-Id": "711e4ccf-2e9b-4bcf-a551-4094005b6194", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "BN7PR07MB4897", "Subject": "[dpdk-dev] [PATCH v4 21/23] crypto/octeontx: add dequeue burst op", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Tejasree Kondoj <kondoj.tejasree@caviumnetworks.com>\n\nSigned-off-by: Ankur Dwivedi <ankur.dwivedi@caviumnetworks.com>\nSigned-off-by: Anoob Joseph <anoob.joseph@caviumnetworks.com>\nSigned-off-by: Murthy NSSR <nidadavolu.murthy@caviumnetworks.com>\nSigned-off-by: Nithin Dabilpuram <nithin.dabilpuram@caviumnetworks.com>\nSigned-off-by: Ragothaman Jayaraman <rjayaraman@caviumnetworks.com>\nSigned-off-by: Srisivasubramanian S <ssrinivasan@caviumnetworks.com>\nSigned-off-by: Tejasree Kondoj <kondoj.tejasree@caviumnetworks.com>\n---\n drivers/common/cpt/cpt_common.h | 2 +\n drivers/common/cpt/cpt_mcode_defines.h | 15 +++++\n drivers/common/cpt/cpt_request_mgr.h | 39 +++++++++++++\n drivers/common/cpt/cpt_ucode.h | 26 +++++++++\n drivers/crypto/octeontx/otx_cryptodev_hw_access.h | 69 +++++++++++++++++++++--\n drivers/crypto/octeontx/otx_cryptodev_ops.c | 47 ++++++++++++++-\n 6 files changed, 192 insertions(+), 6 deletions(-)", "diff": "diff --git a/drivers/common/cpt/cpt_common.h b/drivers/common/cpt/cpt_common.h\nindex 1823939..8461cd6 100644\n--- a/drivers/common/cpt/cpt_common.h\n+++ b/drivers/common/cpt/cpt_common.h\n@@ -15,6 +15,8 @@\n */\n #define CRYPTO_OCTEONTX\t\t0x1\n \n+#define TIME_IN_RESET_COUNT\t5\n+\n /* Default command timeout in seconds */\n #define DEFAULT_COMMAND_TIMEOUT\t4\n \ndiff --git a/drivers/common/cpt/cpt_mcode_defines.h b/drivers/common/cpt/cpt_mcode_defines.h\nindex 60be8b3..becc14f 100644\n--- a/drivers/common/cpt/cpt_mcode_defines.h\n+++ b/drivers/common/cpt/cpt_mcode_defines.h\n@@ -175,6 +175,21 @@ typedef enum {\n \tERR_ENODEV,\n } mc_error_code_t;\n \n+/**\n+ * Enumeration cpt_comp_e\n+ *\n+ * CPT Completion Enumeration\n+ * Enumerates the values of CPT_RES_S[COMPCODE].\n+ */\n+typedef enum {\n+\tCPT_8X_COMP_E_NOTDONE = (0x00),\n+\tCPT_8X_COMP_E_GOOD = (0x01),\n+\tCPT_8X_COMP_E_FAULT = (0x02),\n+\tCPT_8X_COMP_E_SWERR = (0x03),\n+\tCPT_8X_COMP_E_HWERR = (0x04),\n+\tCPT_8X_COMP_E_LAST_ENTRY = (0xFF)\n+} cpt_comp_e_t;\n+\n typedef struct sglist_comp {\n \tunion {\n \t\tuint64_t len;\ndiff --git a/drivers/common/cpt/cpt_request_mgr.h b/drivers/common/cpt/cpt_request_mgr.h\nindex dea89f8..4463cfb 100644\n--- a/drivers/common/cpt/cpt_request_mgr.h\n+++ b/drivers/common/cpt/cpt_request_mgr.h\n@@ -143,4 +143,43 @@ cpt_pmd_crypto_operation(struct cpt_instance *instance,\n \treturn ret;\n }\n \n+static __rte_always_inline int32_t __hot\n+cpt_dequeue_burst(struct cpt_instance *instance, uint16_t cnt,\n+\t\t void *resp[], uint8_t cc[], struct pending_queue *pqueue)\n+{\n+\tstruct cpt_request_info *user_req;\n+\tstruct rid *rid_e;\n+\tint i, count, pcount;\n+\tuint8_t ret;\n+\n+\tpcount = pqueue->pending_count;\n+\tcount = (cnt > pcount) ? pcount : cnt;\n+\n+\tfor (i = 0; i < count; i++) {\n+\t\trid_e = &pqueue->rid_queue[pqueue->deq_head];\n+\t\tuser_req = (struct cpt_request_info *)(rid_e->rid);\n+\n+\t\tif (likely((i+1) < count))\n+\t\t\trte_prefetch_non_temporal((void *)rid_e[1].rid);\n+\n+\t\tret = check_nb_command_id(user_req, instance);\n+\n+\t\tif (unlikely(ret == ERR_REQ_PENDING)) {\n+\t\t\t/* Stop checking for completions */\n+\t\t\tbreak;\n+\t\t}\n+\n+\t\t/* Return completion code and op handle */\n+\t\tcc[i] = (uint8_t)ret;\n+\t\tresp[i] = user_req->op;\n+\t\tCPT_LOG_DP_DEBUG(\"Request %p Op %p completed with code %d\",\n+\t\t\t user_req, user_req->op, ret);\n+\n+\t\tMOD_INC(pqueue->deq_head, DEFAULT_CMD_QLEN);\n+\t\tpqueue->pending_count -= 1;\n+\t}\n+\n+\treturn i;\n+}\n+\n #endif /* _CPT_REQUEST_MGR_H_ */\ndiff --git a/drivers/common/cpt/cpt_ucode.h b/drivers/common/cpt/cpt_ucode.h\nindex 4d892f2..c5a9f34 100644\n--- a/drivers/common/cpt/cpt_ucode.h\n+++ b/drivers/common/cpt/cpt_ucode.h\n@@ -3373,6 +3373,32 @@ fill_fc_params(struct rte_crypto_op *cop,\n \treturn prep_req;\n }\n \n+static __rte_always_inline void\n+compl_auth_verify(struct rte_crypto_op *op,\n+\t\t uint8_t *gen_mac,\n+\t\t uint64_t mac_len)\n+{\n+\tuint8_t *mac;\n+\tstruct rte_crypto_sym_op *sym_op = op->sym;\n+\n+\tif (sym_op->auth.digest.data)\n+\t\tmac = sym_op->auth.digest.data;\n+\telse\n+\t\tmac = rte_pktmbuf_mtod_offset(sym_op->m_src,\n+\t\t\t\t\t uint8_t *,\n+\t\t\t\t\t sym_op->auth.data.length +\n+\t\t\t\t\t sym_op->auth.data.offset);\n+\tif (!mac) {\n+\t\top->status = RTE_CRYPTO_OP_STATUS_ERROR;\n+\t\treturn;\n+\t}\n+\n+\tif (memcmp(mac, gen_mac, mac_len))\n+\t\top->status = RTE_CRYPTO_OP_STATUS_AUTH_FAILED;\n+\telse\n+\t\top->status = RTE_CRYPTO_OP_STATUS_SUCCESS;\n+}\n+\n static __rte_always_inline int\n instance_session_cfg(struct rte_crypto_sym_xform *xform, void *sess)\n {\ndiff --git a/drivers/crypto/octeontx/otx_cryptodev_hw_access.h b/drivers/crypto/octeontx/otx_cryptodev_hw_access.h\nindex 6f4d6e1..82b15ee 100644\n--- a/drivers/crypto/octeontx/otx_cryptodev_hw_access.h\n+++ b/drivers/crypto/octeontx/otx_cryptodev_hw_access.h\n@@ -1,19 +1,20 @@\n /* SPDX-License-Identifier: BSD-3-Clause\n * Copyright(c) 2018 Cavium, Inc\n */\n-\n #ifndef _OTX_CRYPTODEV_HW_ACCESS_H_\n #define _OTX_CRYPTODEV_HW_ACCESS_H_\n \n #include <stdbool.h>\n \n #include <rte_branch_prediction.h>\n+#include <rte_cycles.h>\n #include <rte_io.h>\n #include <rte_memory.h>\n #include <rte_prefetch.h>\n \n #include \"cpt_common.h\"\n #include \"cpt_hw_types.h\"\n+#include \"cpt_mcode_defines.h\"\n #include \"cpt_pmd_logs.h\"\n \n #define CPT_INTR_POLL_INTERVAL_MS\t(50)\n@@ -252,10 +253,68 @@ static __rte_always_inline uint8_t\n check_nb_command_id(struct cpt_request_info *user_req,\n \t\tstruct cpt_instance *instance)\n {\n-\t/* Required for dequeue operation. Adding a dummy routine for now */\n-\tRTE_SET_USED(user_req);\n-\tRTE_SET_USED(instance);\n-\treturn 0;\n+\tuint8_t ret = ERR_REQ_PENDING;\n+\tstruct cpt_vf *cptvf = (struct cpt_vf *)instance;\n+\tvolatile cpt_res_s_t *cptres;\n+\n+\tcptres = (volatile cpt_res_s_t *)user_req->completion_addr;\n+\n+\tif (unlikely(cptres->s8x.compcode == CPT_8X_COMP_E_NOTDONE)) {\n+\t\t/*\n+\t\t * Wait for some time for this command to get completed\n+\t\t * before timing out\n+\t\t */\n+\t\tif (rte_get_timer_cycles() < user_req->time_out)\n+\t\t\treturn ret;\n+\t\t/*\n+\t\t * TODO: See if alternate caddr can be used to not loop\n+\t\t * longer than needed.\n+\t\t */\n+\t\tif ((cptres->s8x.compcode == CPT_8X_COMP_E_NOTDONE) &&\n+\t\t (user_req->extra_time < TIME_IN_RESET_COUNT)) {\n+\t\t\tuser_req->extra_time++;\n+\t\t\treturn ret;\n+\t\t}\n+\n+\t\tif (cptres->s8x.compcode != CPT_8X_COMP_E_NOTDONE)\n+\t\t\tgoto complete;\n+\n+\t\tret = ERR_REQ_TIMEOUT;\n+\t\tCPT_LOG_DP_ERR(\"Request %p timedout\", user_req);\n+\t\totx_cpt_poll_misc(cptvf);\n+\t\tgoto exit;\n+\t}\n+\n+complete:\n+\tif (likely(cptres->s8x.compcode == CPT_8X_COMP_E_GOOD)) {\n+\t\tret = 0; /* success */\n+\t\tif (unlikely((uint8_t)*user_req->alternate_caddr)) {\n+\t\t\tret = (uint8_t)*user_req->alternate_caddr;\n+\t\t\tCPT_LOG_DP_ERR(\"Request %p : failed with microcode\"\n+\t\t\t\t\" error, MC completion code : 0x%x\", user_req,\n+\t\t\t\tret);\n+\t\t}\n+\t\tCPT_LOG_DP_DEBUG(\"MC status %.8x\\n\",\n+\t\t\t *((volatile uint32_t *)user_req->alternate_caddr));\n+\t\tCPT_LOG_DP_DEBUG(\"HW status %.8x\\n\",\n+\t\t\t *((volatile uint32_t *)user_req->completion_addr));\n+\t} else if ((cptres->s8x.compcode == CPT_8X_COMP_E_SWERR) ||\n+\t\t (cptres->s8x.compcode == CPT_8X_COMP_E_FAULT)) {\n+\t\tret = (uint8_t)*user_req->alternate_caddr;\n+\t\tif (!ret)\n+\t\t\tret = ERR_BAD_ALT_CCODE;\n+\t\tCPT_LOG_DP_DEBUG(\"Request %p : failed with %s : err code :%x\",\n+\t\t\t user_req,\n+\t\t\t (cptres->s8x.compcode == CPT_8X_COMP_E_FAULT) ?\n+\t\t\t \"DMA Fault\" : \"Software error\", ret);\n+\t} else {\n+\t\tCPT_LOG_DP_ERR(\"Request %p : unexpected completion code %d\",\n+\t\t\t user_req, cptres->s8x.compcode);\n+\t\tret = (uint8_t)*user_req->alternate_caddr;\n+\t}\n+\n+exit:\n+\treturn ret;\n }\n \n #endif /* _OTX_CRYPTODEV_HW_ACCESS_H_ */\ndiff --git a/drivers/crypto/octeontx/otx_cryptodev_ops.c b/drivers/crypto/octeontx/otx_cryptodev_ops.c\nindex 4240051..23f9659 100644\n--- a/drivers/crypto/octeontx/otx_cryptodev_ops.c\n+++ b/drivers/crypto/octeontx/otx_cryptodev_ops.c\n@@ -366,6 +366,51 @@ otx_cpt_pkt_enqueue(void *qptr, struct rte_crypto_op **ops, uint16_t nb_ops)\n \treturn count;\n }\n \n+static uint16_t\n+otx_cpt_pkt_dequeue(void *qptr, struct rte_crypto_op **ops, uint16_t nb_ops)\n+{\n+\tstruct cpt_instance *instance = (struct cpt_instance *)qptr;\n+\tstruct cpt_vf *cptvf = (struct cpt_vf *)instance;\n+\tstruct pending_queue *pqueue = &cptvf->pqueue;\n+\tuint16_t nb_completed, i = 0;\n+\tuint8_t compcode[nb_ops];\n+\n+\tnb_completed = cpt_dequeue_burst(instance, nb_ops,\n+\t\t\t\t\t (void **)ops, compcode, pqueue);\n+\twhile (likely(i < nb_completed)) {\n+\t\tstruct rte_crypto_op *cop;\n+\t\tvoid *metabuf;\n+\t\tuintptr_t *rsp;\n+\t\tuint8_t status;\n+\n+\t\trsp = (void *)ops[i];\n+\t\tstatus = compcode[i];\n+\t\tif (likely((i + 1) < nb_completed))\n+\t\t\trte_prefetch0(ops[i+1]);\n+\t\tmetabuf = (void *)rsp[0];\n+\t\tcop = (void *)rsp[1];\n+\n+\t\tops[i] = cop;\n+\n+\t\tif (likely(status == 0)) {\n+\t\t\tif (likely(!rsp[2]))\n+\t\t\t\tcop->status =\n+\t\t\t\t\tRTE_CRYPTO_OP_STATUS_SUCCESS;\n+\t\t\telse\n+\t\t\t\tcompl_auth_verify(cop, (uint8_t *)rsp[2],\n+\t\t\t\t\t\t rsp[3]);\n+\t\t} else if (status == ERR_GC_ICV_MISCOMPARE) {\n+\t\t\t/*auth data mismatch */\n+\t\t\tcop->status = RTE_CRYPTO_OP_STATUS_AUTH_FAILED;\n+\t\t} else {\n+\t\t\tcop->status = RTE_CRYPTO_OP_STATUS_ERROR;\n+\t\t}\n+\t\tfree_op_meta(metabuf, cptvf->meta_info.cptvf_meta_pool);\n+\t\ti++;\n+\t}\n+\treturn nb_completed;\n+}\n+\n static struct rte_cryptodev_ops cptvf_ops = {\n \t/* Device related operations */\n \t.dev_configure = otx_cpt_dev_config,\n@@ -458,7 +503,7 @@ otx_cpt_dev_create(struct rte_cryptodev *c_dev)\n \tc_dev->dev_ops = &cptvf_ops;\n \n \tc_dev->enqueue_burst = otx_cpt_pkt_enqueue;\n-\tc_dev->dequeue_burst = NULL;\n+\tc_dev->dequeue_burst = otx_cpt_pkt_dequeue;\n \n \tc_dev->feature_flags = RTE_CRYPTODEV_FF_SYMMETRIC_CRYPTO |\n \t\t\tRTE_CRYPTODEV_FF_HW_ACCELERATED |\n", "prefixes": [ "v4", "21/23" ] }