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GET /api/patches/46341/?format=api
{ "id": 46341, "url": "http://patches.dpdk.org/api/patches/46341/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1539076076-19786-21-git-send-email-anoob.joseph@caviumnetworks.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1539076076-19786-21-git-send-email-anoob.joseph@caviumnetworks.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1539076076-19786-21-git-send-email-anoob.joseph@caviumnetworks.com", "date": "2018-10-09T09:07:53", "name": "[v4,20/23] crypto/octeontx: add enqueue burst op", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "7cba81a451b43ffb54336d9ad09af6c2ed5019f5", "submitter": { "id": 893, "url": "http://patches.dpdk.org/api/people/893/?format=api", "name": "Anoob Joseph", "email": "anoob.joseph@caviumnetworks.com" }, "delegate": { "id": 6690, "url": "http://patches.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1539076076-19786-21-git-send-email-anoob.joseph@caviumnetworks.com/mbox/", "series": [ { "id": 1770, "url": "http://patches.dpdk.org/api/series/1770/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=1770", "date": "2018-10-09T09:07:33", "name": "Adding Cavium's OCTEON TX crypto PMD", "version": 4, "mbox": "http://patches.dpdk.org/series/1770/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/46341/comments/", "check": "fail", "checks": "http://patches.dpdk.org/api/patches/46341/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 05DA71B13D;\n\tTue, 9 Oct 2018 11:10:09 +0200 (CEST)", "from NAM03-DM3-obe.outbound.protection.outlook.com\n\t(mail-dm3nam03on0082.outbound.protection.outlook.com [104.47.41.82])\n\tby dpdk.org (Postfix) with ESMTP id D444A1B3AC\n\tfor <dev@dpdk.org>; Tue, 9 Oct 2018 11:10:02 +0200 (CEST)", "from ajoseph83.caveonetworks.com.com (115.113.156.2) by\n\tBN7PR07MB4897.namprd07.prod.outlook.com (2603:10b6:406:ef::26) with\n\tMicrosoft SMTP Server (version=TLS1_2,\n\tcipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id\n\t15.20.1207.28; Tue, 9 Oct 2018 09:09:58 +0000" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=CAVIUMNETWORKS.onmicrosoft.com; s=selector1-cavium-com;\n\th=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n\tbh=kR6bLZdHJs6diJtPoaJAtl1Hn1MFge8cmfUq6H3ZXcU=;\n\tb=lbWs1Xp6pbkT91pYVhKYn2f9LM6dij/PzlCXwR8X3DVxn3UxNQK2m8E9j0gR8WWak4ggwa00utMAAsk08rCPOov905IB5/qHEdSKIvGYZI+i6GfXYt5qvC3elHxxFXBjCQigkJB94MmEOuW6FRXCEQImChRSXGyMboMu1u4JlOo=", "Authentication-Results": "spf=none (sender IP is )\n\tsmtp.mailfrom=Anoob.Joseph@cavium.com; ", "From": "Anoob Joseph <anoob.joseph@caviumnetworks.com>", "To": "Akhil Goyal <akhil.goyal@nxp.com>,\n\tPablo de Lara <pablo.de.lara.guarch@intel.com>,\n\tThomas Monjalon <thomas@monjalon.net>", "Cc": "Tejasree Kondoj <kondoj.tejasree@caviumnetworks.com>,\n\tJerin Jacob <jerin.jacob@caviumnetworks.com>,\n\tNarayana Prasad <narayanaprasad.athreya@caviumnetworks.com>,\n\tAnkur Dwivedi <ankur.dwivedi@caviumnetworks.com>,\n\tAnoob Joseph <anoob.joseph@caviumnetworks.com>,\n\tMurthy NSSR <nidadavolu.murthy@caviumnetworks.com>,\n\tNithin Dabilpuram <nithin.dabilpuram@caviumnetworks.com>,\n\tRagothaman Jayaraman <rjayaraman@caviumnetworks.com>,\n\tSrisivasubramanian S <ssrinivasan@caviumnetworks.com>, dev@dpdk.org", "Date": "Tue, 9 Oct 2018 14:37:53 +0530", "Message-Id": "<1539076076-19786-21-git-send-email-anoob.joseph@caviumnetworks.com>", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": "<1539076076-19786-1-git-send-email-anoob.joseph@caviumnetworks.com>", "References": "<1538744363-30340-1-git-send-email-anoob.joseph@caviumnetworks.com>\n\t<1539076076-19786-1-git-send-email-anoob.joseph@caviumnetworks.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Originating-IP": "[115.113.156.2]", "X-ClientProxiedBy": "PN1PR0101CA0004.INDPRD01.PROD.OUTLOOK.COM\n\t(2603:1096:c00:e::14) To BN7PR07MB4897.namprd07.prod.outlook.com\n\t(2603:10b6:406:ef::26)", "X-MS-PublicTrafficType": "Email", "X-MS-Office365-Filtering-Correlation-Id": "9bd135a5-786f-4f8f-664c-08d62dc6fe53", "X-Microsoft-Antispam": "BCL:0; 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"Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Tejasree Kondoj <kondoj.tejasree@caviumnetworks.com>\n\nSigned-off-by: Ankur Dwivedi <ankur.dwivedi@caviumnetworks.com>\nSigned-off-by: Anoob Joseph <anoob.joseph@caviumnetworks.com>\nSigned-off-by: Murthy NSSR <nidadavolu.murthy@caviumnetworks.com>\nSigned-off-by: Nithin Dabilpuram <nithin.dabilpuram@caviumnetworks.com>\nSigned-off-by: Ragothaman Jayaraman <rjayaraman@caviumnetworks.com>\nSigned-off-by: Srisivasubramanian S <ssrinivasan@caviumnetworks.com>\nSigned-off-by: Tejasree Kondoj <kondoj.tejasree@caviumnetworks.com>\n---\n drivers/common/cpt/cpt_common.h | 3 ++\n drivers/common/cpt/cpt_request_mgr.h | 46 ++++++++++++++++++++++-\n drivers/crypto/octeontx/otx_cryptodev_hw_access.h | 18 +++++++++\n drivers/crypto/octeontx/otx_cryptodev_ops.c | 27 ++++++++++++-\n 4 files changed, 92 insertions(+), 2 deletions(-)", "diff": "diff --git a/drivers/common/cpt/cpt_common.h b/drivers/common/cpt/cpt_common.h\nindex 7333c13..1823939 100644\n--- a/drivers/common/cpt/cpt_common.h\n+++ b/drivers/common/cpt/cpt_common.h\n@@ -15,6 +15,9 @@\n */\n #define CRYPTO_OCTEONTX\t\t0x1\n \n+/* Default command timeout in seconds */\n+#define DEFAULT_COMMAND_TIMEOUT\t4\n+\n #define CPT_COUNT_THOLD\t\t32\n #define CPT_TIMER_THOLD\t\t0x3F\n \ndiff --git a/drivers/common/cpt/cpt_request_mgr.h b/drivers/common/cpt/cpt_request_mgr.h\nindex 4d21f46..dea89f8 100644\n--- a/drivers/common/cpt/cpt_request_mgr.h\n+++ b/drivers/common/cpt/cpt_request_mgr.h\n@@ -5,6 +5,9 @@\n #ifndef _CPT_REQUEST_MGR_H_\n #define _CPT_REQUEST_MGR_H_\n \n+#include <rte_branch_prediction.h>\n+#include <rte_cycles.h>\n+\n #include \"cpt_common.h\"\n #include \"cpt_mcode_defines.h\"\n \n@@ -34,6 +37,45 @@ cpt_get_session_size(void)\n \treturn (sizeof(struct cpt_sess_misc) + RTE_ALIGN_CEIL(ctx_len, 8));\n }\n \n+static __rte_always_inline int32_t __hot\n+cpt_enqueue_req(struct cpt_instance *instance, struct pending_queue *pqueue,\n+\t\tvoid *req)\n+{\n+\tstruct cpt_request_info *user_req = (struct cpt_request_info *)req;\n+\tint32_t ret = 0;\n+\n+\tif (unlikely(!req))\n+\t\treturn 0;\n+\n+\tif (unlikely(pqueue->pending_count >= DEFAULT_CMD_QLEN))\n+\t\treturn -EAGAIN;\n+\n+\tfill_cpt_inst(instance, req);\n+\n+\tCPT_LOG_DP_DEBUG(\"req: %p op: %p \", req, user_req->op);\n+\n+\t/* Fill time_out cycles */\n+\tuser_req->time_out = rte_get_timer_cycles() +\n+\t\t\tDEFAULT_COMMAND_TIMEOUT * rte_get_timer_hz();\n+\tuser_req->extra_time = 0;\n+\n+\t/* Default mode of software queue */\n+\tmark_cpt_inst(instance);\n+\n+\tpqueue->rid_queue[pqueue->enq_tail].rid =\n+\t\t(uintptr_t)user_req;\n+\t/* We will use soft queue length here to limit\n+\t * requests\n+\t */\n+\tMOD_INC(pqueue->enq_tail, DEFAULT_CMD_QLEN);\n+\tpqueue->pending_count += 1;\n+\n+\tCPT_LOG_DP_DEBUG(\"Submitted NB cmd with request: %p \"\n+\t\t\t \"op: %p\", user_req, user_req->op);\n+\n+\treturn ret;\n+}\n+\n static __rte_always_inline int __hot\n cpt_pmd_crypto_operation(struct cpt_instance *instance,\n \t\tstruct rte_crypto_op *op, struct pending_queue *pqueue,\n@@ -45,7 +87,6 @@ cpt_pmd_crypto_operation(struct cpt_instance *instance,\n \tint ret = 0;\n \tuint64_t cpt_op;\n \tstruct cpt_vf *cptvf = (struct cpt_vf *)instance;\n-\tRTE_SET_USED(pqueue);\n \n \tif (unlikely(op->sess_type == RTE_CRYPTO_OP_SESSIONLESS)) {\n \t\tint sess_len;\n@@ -83,6 +124,9 @@ cpt_pmd_crypto_operation(struct cpt_instance *instance,\n \t\tgoto req_fail;\n \t}\n \n+\t/* Enqueue prepared instruction to HW */\n+\tret = cpt_enqueue_req(instance, pqueue, prep_req);\n+\n \tif (unlikely(ret)) {\n \t\tif (unlikely(ret == -EAGAIN))\n \t\t\tgoto req_fail;\ndiff --git a/drivers/crypto/octeontx/otx_cryptodev_hw_access.h b/drivers/crypto/octeontx/otx_cryptodev_hw_access.h\nindex affbba1..6f4d6e1 100644\n--- a/drivers/crypto/octeontx/otx_cryptodev_hw_access.h\n+++ b/drivers/crypto/octeontx/otx_cryptodev_hw_access.h\n@@ -187,6 +187,15 @@ otx_cpt_read_vq_doorbell(struct cpt_vf *cptvf)\n \treturn vqx_dbell.s.dbell_cnt;\n }\n \n+static __rte_always_inline void\n+otx_cpt_ring_dbell(struct cpt_instance *instance, uint16_t count)\n+{\n+\tstruct cpt_vf *cptvf = (struct cpt_vf *)instance;\n+\t/* Memory barrier to flush pending writes */\n+\trte_smp_wmb();\n+\totx_cpt_write_vq_doorbell(cptvf, count);\n+}\n+\n static __rte_always_inline void *\n get_cpt_inst(struct command_queue *cqueue)\n {\n@@ -237,7 +246,16 @@ mark_cpt_inst(struct cpt_instance *instance)\n \t\tqueue->idx = 0;\n \t\tqueue->cchunk = cchunk;\n \t}\n+}\n \n+static __rte_always_inline uint8_t\n+check_nb_command_id(struct cpt_request_info *user_req,\n+\t\tstruct cpt_instance *instance)\n+{\n+\t/* Required for dequeue operation. Adding a dummy routine for now */\n+\tRTE_SET_USED(user_req);\n+\tRTE_SET_USED(instance);\n+\treturn 0;\n }\n \n #endif /* _OTX_CRYPTODEV_HW_ACCESS_H_ */\ndiff --git a/drivers/crypto/octeontx/otx_cryptodev_ops.c b/drivers/crypto/octeontx/otx_cryptodev_ops.c\nindex 16fad49..4240051 100644\n--- a/drivers/crypto/octeontx/otx_cryptodev_ops.c\n+++ b/drivers/crypto/octeontx/otx_cryptodev_ops.c\n@@ -341,6 +341,31 @@ otx_cpt_session_clear(struct rte_cryptodev *dev,\n \t}\n }\n \n+static uint16_t\n+otx_cpt_pkt_enqueue(void *qptr, struct rte_crypto_op **ops, uint16_t nb_ops)\n+{\n+\tstruct cpt_instance *instance = (struct cpt_instance *)qptr;\n+\tuint16_t count = 0;\n+\tint ret;\n+\tstruct cpt_vf *cptvf = (struct cpt_vf *)instance;\n+\tstruct pending_queue *pqueue = &cptvf->pqueue;\n+\n+\tcount = DEFAULT_CMD_QLEN - pqueue->pending_count;\n+\tif (nb_ops > count)\n+\t\tnb_ops = count;\n+\n+\tcount = 0;\n+\twhile (likely(count < nb_ops)) {\n+\t\tret = cpt_pmd_crypto_operation(instance, ops[count], pqueue,\n+\t\t\t\t\t\totx_cryptodev_driver_id);\n+\t\tif (unlikely(ret))\n+\t\t\tbreak;\n+\t\tcount++;\n+\t}\n+\totx_cpt_ring_dbell(instance, count);\n+\treturn count;\n+}\n+\n static struct rte_cryptodev_ops cptvf_ops = {\n \t/* Device related operations */\n \t.dev_configure = otx_cpt_dev_config,\n@@ -432,7 +457,7 @@ otx_cpt_dev_create(struct rte_cryptodev *c_dev)\n \n \tc_dev->dev_ops = &cptvf_ops;\n \n-\tc_dev->enqueue_burst = NULL;\n+\tc_dev->enqueue_burst = otx_cpt_pkt_enqueue;\n \tc_dev->dequeue_burst = NULL;\n \n \tc_dev->feature_flags = RTE_CRYPTODEV_FF_SYMMETRIC_CRYPTO |\n", "prefixes": [ "v4", "20/23" ] }