Patch Detail
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Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/46322/?format=api
{ "id": 46322, "url": "http://patches.dpdk.org/api/patches/46322/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1539076076-19786-2-git-send-email-anoob.joseph@caviumnetworks.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1539076076-19786-2-git-send-email-anoob.joseph@caviumnetworks.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1539076076-19786-2-git-send-email-anoob.joseph@caviumnetworks.com", "date": "2018-10-09T09:07:34", "name": "[v4,01/23] crypto/octeontx: add PMD skeleton", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "667b1263cd7de33218e66570ce544b45d9f6683d", "submitter": { "id": 893, "url": "http://patches.dpdk.org/api/people/893/?format=api", "name": "Anoob Joseph", "email": "anoob.joseph@caviumnetworks.com" }, "delegate": { "id": 6690, "url": "http://patches.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1539076076-19786-2-git-send-email-anoob.joseph@caviumnetworks.com/mbox/", "series": [ { "id": 1770, "url": "http://patches.dpdk.org/api/series/1770/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=1770", "date": "2018-10-09T09:07:33", "name": "Adding Cavium's OCTEON TX crypto PMD", "version": 4, "mbox": "http://patches.dpdk.org/series/1770/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/46322/comments/", "check": "fail", "checks": "http://patches.dpdk.org/api/patches/46322/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 3D71D1B10D;\n\tTue, 9 Oct 2018 11:08:44 +0200 (CEST)", "from NAM03-DM3-obe.outbound.protection.outlook.com\n\t(mail-dm3nam03on0059.outbound.protection.outlook.com [104.47.41.59])\n\tby dpdk.org (Postfix) with ESMTP id 91DD91B11B\n\tfor <dev@dpdk.org>; Tue, 9 Oct 2018 11:08:42 +0200 (CEST)", "from ajoseph83.caveonetworks.com.com (115.113.156.2) by\n\tBN7PR07MB4897.namprd07.prod.outlook.com (2603:10b6:406:ef::26) with\n\tMicrosoft SMTP Server (version=TLS1_2,\n\tcipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id\n\t15.20.1207.28; Tue, 9 Oct 2018 09:08:37 +0000" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=CAVIUMNETWORKS.onmicrosoft.com; s=selector1-cavium-com;\n\th=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n\tbh=YDOuc8Eg9PRCReTtdaU5PgIzJrEyjRf03jFTYgChdmM=;\n\tb=Y1RGUekXjvFym9qKKY0pMXA6hfLYJHpSv/Ta+JuxlXNn0/YdBXrdfhNdrMJi64X18I1I6kcnGEZ24qu/v/zn7q5ktM2K+VSP0iEWPfioCY4xbpFSBicUrpcDxvl9diQVhJhGgd+MaH171KFpnodzv+sY39ilbWWbiaYcGk4DmfM=", "Authentication-Results": "spf=none (sender IP is )\n\tsmtp.mailfrom=Anoob.Joseph@cavium.com; ", "From": "Anoob Joseph <anoob.joseph@caviumnetworks.com>", "To": "Akhil Goyal <akhil.goyal@nxp.com>,\n\tPablo de Lara <pablo.de.lara.guarch@intel.com>,\n\tThomas Monjalon <thomas@monjalon.net>", "Cc": "Anoob Joseph <anoob.joseph@caviumnetworks.com>,\n\tJerin Jacob <jerin.jacob@caviumnetworks.com>,\n\tNarayana Prasad <narayanaprasad.athreya@caviumnetworks.com>,\n\tAnkur Dwivedi <ankur.dwivedi@caviumnetworks.com>,\n\tMurthy NSSR <nidadavolu.murthy@caviumnetworks.com>,\n\tNithin Dabilpuram <nithin.dabilpuram@caviumnetworks.com>,\n\tRagothaman Jayaraman <rjayaraman@caviumnetworks.com>,\n\tSrisivasubramanian S <ssrinivasan@caviumnetworks.com>,\n\tTejasree Kondoj <kondoj.tejasree@caviumnetworks.com>, dev@dpdk.org", "Date": "Tue, 9 Oct 2018 14:37:34 +0530", "Message-Id": "<1539076076-19786-2-git-send-email-anoob.joseph@caviumnetworks.com>", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": "<1539076076-19786-1-git-send-email-anoob.joseph@caviumnetworks.com>", "References": "<1538744363-30340-1-git-send-email-anoob.joseph@caviumnetworks.com>\n\t<1539076076-19786-1-git-send-email-anoob.joseph@caviumnetworks.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Originating-IP": "[115.113.156.2]", "X-ClientProxiedBy": "PN1PR0101CA0004.INDPRD01.PROD.OUTLOOK.COM\n\t(2603:1096:c00:e::14) To BN7PR07MB4897.namprd07.prod.outlook.com\n\t(2603:10b6:406:ef::26)", "X-MS-PublicTrafficType": "Email", "X-MS-Office365-Filtering-Correlation-Id": "d4d708f8-d50f-4282-0335-08d62dc6ce69", "X-Microsoft-Antispam": "BCL:0; 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SFP:1101; SCL:1; SRVR:BN7PR07MB4897;\n\tH:ajoseph83.caveonetworks.com.com; FPR:; SPF:None; LANG:en;\n\tPTR:InfoNoRecords; A:1; MX:1; ", "Received-SPF": "None (protection.outlook.com: cavium.com does not designate\n\tpermitted sender hosts)", "X-Microsoft-Antispam-Message-Info": "cjFLTorSyCwrgGU72WHMikMM+66QwMC5z+bhS6Oh1h8ftfF4VDbvQ/tHawImQLQGeNfmT/W6GJ2lFO486kQ5wcygOatxGH07uqe01pmbadGxZJnt28sDGf+ppcQBSJ79CYf9UjB9Wn2A22haoLNMsf24cAElmzcNFIlNmLfbOQ1IFWZSNMVECjUoHJ1t3NMUO1VWgESzRV8eOU4zqYCXsWUBo4p1A+A7fEd5qIcoC869k9TCsTb8JB8zL9oh0ZwNV08oUAANuBJT6yJOwDjFz02E1sO1HLhaIYjn0LdyLJ5WaKCDdds2v3Q9AU8fnjDZ6BGmfrJTi9sKRtgAz5E+r/lTxkMdJg9UDJEb567vTFI=", "SpamDiagnosticOutput": "1:99", "SpamDiagnosticMetadata": "NSPM", "X-OriginatorOrg": "caviumnetworks.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "09 Oct 2018 09:08:37.2761\n\t(UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "d4d708f8-d50f-4282-0335-08d62dc6ce69", "X-MS-Exchange-CrossTenant-FromEntityHeader": "Hosted", "X-MS-Exchange-CrossTenant-Id": "711e4ccf-2e9b-4bcf-a551-4094005b6194", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "BN7PR07MB4897", "Subject": "[dpdk-dev] [PATCH v4 01/23] crypto/octeontx: add PMD skeleton", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Adding OCTEON TX crypto PMD skeleton. Updating the maintainers files to\nclaim responsibility. Also enabling driver by default by adding the\ncomponent in common_base.\n\nSigned-off-by: Ankur Dwivedi <ankur.dwivedi@caviumnetworks.com>\nSigned-off-by: Anoob Joseph <anoob.joseph@caviumnetworks.com>\nSigned-off-by: Murthy NSSR <nidadavolu.murthy@caviumnetworks.com>\nSigned-off-by: Nithin Dabilpuram <nithin.dabilpuram@caviumnetworks.com>\nSigned-off-by: Ragothaman Jayaraman <rjayaraman@caviumnetworks.com>\nSigned-off-by: Srisivasubramanian S <ssrinivasan@caviumnetworks.com>\nSigned-off-by: Tejasree Kondoj <kondoj.tejasree@caviumnetworks.com>\n---\n MAINTAINERS | 5 +\n config/common_base | 5 +\n drivers/common/cpt/cpt_pmd_logs.h | 50 ++++++++\n drivers/crypto/Makefile | 1 +\n drivers/crypto/meson.build | 2 +-\n drivers/crypto/octeontx/Makefile | 42 +++++++\n drivers/crypto/octeontx/meson.build | 14 +++\n drivers/crypto/octeontx/otx_cryptodev.c | 130 +++++++++++++++++++++\n drivers/crypto/octeontx/otx_cryptodev.h | 20 ++++\n drivers/crypto/octeontx/otx_cryptodev_ops.c | 15 +++\n drivers/crypto/octeontx/otx_cryptodev_ops.h | 11 ++\n .../octeontx/rte_pmd_octeontx_crypto_version.map | 4 +\n mk/rte.app.mk | 1 +\n 13 files changed, 299 insertions(+), 1 deletion(-)\n create mode 100644 drivers/common/cpt/cpt_pmd_logs.h\n create mode 100644 drivers/crypto/octeontx/Makefile\n create mode 100644 drivers/crypto/octeontx/meson.build\n create mode 100644 drivers/crypto/octeontx/otx_cryptodev.c\n create mode 100644 drivers/crypto/octeontx/otx_cryptodev.h\n create mode 100644 drivers/crypto/octeontx/otx_cryptodev_ops.c\n create mode 100644 drivers/crypto/octeontx/otx_cryptodev_ops.h\n create mode 100644 drivers/crypto/octeontx/rte_pmd_octeontx_crypto_version.map", "diff": "diff --git a/MAINTAINERS b/MAINTAINERS\nindex 84b9ff7..001bae9 100644\n--- a/MAINTAINERS\n+++ b/MAINTAINERS\n@@ -779,6 +779,11 @@ F: drivers/crypto/armv8/\n F: doc/guides/cryptodevs/armv8.rst\n F: doc/guides/cryptodevs/features/armv8.ini\n \n+Cavium OCTEON TX crypto\n+M: Anoob Joseph <anoob.joseph@caviumnetworks.com>\n+F: drivers/common/cpt/\n+F: drivers/crypto/octeontx/\n+\n Crypto Scheduler\n M: Fan Zhang <roy.fan.zhang@intel.com>\n F: drivers/crypto/scheduler/\ndiff --git a/config/common_base b/config/common_base\nindex 43c7e9a..85fad0c 100644\n--- a/config/common_base\n+++ b/config/common_base\n@@ -640,6 +640,11 @@ CONFIG_RTE_LIBRTE_PMD_DPAA_EVENTDEV=n\n CONFIG_RTE_LIBRTE_PMD_DPAA2_EVENTDEV=n\n \n #\n+# Compile PMD for Cavium OCTEON TX crypto device\n+#\n+CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO=y\n+\n+#\n # Compile raw device support\n # EXPERIMENTAL: API may change without prior notice\n #\ndiff --git a/drivers/common/cpt/cpt_pmd_logs.h b/drivers/common/cpt/cpt_pmd_logs.h\nnew file mode 100644\nindex 0000000..4cbec4e\n--- /dev/null\n+++ b/drivers/common/cpt/cpt_pmd_logs.h\n@@ -0,0 +1,50 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2018 Cavium, Inc\n+ */\n+\n+#ifndef _CPT_PMD_LOGS_H_\n+#define _CPT_PMD_LOGS_H_\n+\n+#include <rte_log.h>\n+\n+/*\n+ * This file defines log macros\n+ */\n+\n+#define CPT_PMD_DRV_LOG_RAW(level, fmt, args...) \\\n+\t\trte_log(RTE_LOG_ ## level, cpt_logtype, \\\n+\t\t\t\"cpt: %s(): \" fmt \"\\n\", __func__, ##args)\n+\n+#define CPT_PMD_INIT_FUNC_TRACE() CPT_PMD_DRV_LOG_RAW(DEBUG, \" >>\")\n+\n+#define CPT_LOG_INFO(fmt, args...) \\\n+\tCPT_PMD_DRV_LOG_RAW(INFO, fmt, ## args)\n+#define CPT_LOG_WARN(fmt, args...) \\\n+\tCPT_PMD_DRV_LOG_RAW(WARNING, fmt, ## args)\n+#define CPT_LOG_ERR(fmt, args...) \\\n+\tCPT_PMD_DRV_LOG_RAW(ERR, fmt, ## args)\n+\n+/*\n+ * DP logs, toggled out at compile time if level lower than current level.\n+ * DP logs would be logged under 'PMD' type. So for dynamic logging, the\n+ * level of 'pmd' has to be used.\n+ */\n+#define CPT_LOG_DP(level, fmt, args...) \\\n+\tRTE_LOG_DP(level, PMD, fmt \"\\n\", ## args)\n+\n+#define CPT_LOG_DP_DEBUG(fmt, args...) \\\n+\tCPT_LOG_DP(DEBUG, fmt, ## args)\n+#define CPT_LOG_DP_INFO(fmt, args...) \\\n+\tCPT_LOG_DP(INFO, fmt, ## args)\n+#define CPT_LOG_DP_WARN(fmt, args...) \\\n+\tCPT_LOG_DP(WARNING, fmt, ## args)\n+#define CPT_LOG_DP_ERR(fmt, args...) \\\n+\tCPT_LOG_DP(ERR, fmt, ## args)\n+\n+/*\n+ * cpt_logtype will be used for common logging. This field would be initialized\n+ * by otx_* driver routines during PCI probe.\n+ */\n+int cpt_logtype;\n+\n+#endif /* _CPT_PMD_LOGS_H_ */\ndiff --git a/drivers/crypto/Makefile b/drivers/crypto/Makefile\nindex c480cbd..c083e64 100644\n--- a/drivers/crypto/Makefile\n+++ b/drivers/crypto/Makefile\n@@ -7,6 +7,7 @@ DIRS-$(CONFIG_RTE_LIBRTE_PMD_AESNI_GCM) += aesni_gcm\n DIRS-$(CONFIG_RTE_LIBRTE_PMD_AESNI_MB) += aesni_mb\n DIRS-$(CONFIG_RTE_LIBRTE_PMD_ARMV8_CRYPTO) += armv8\n DIRS-$(CONFIG_RTE_LIBRTE_PMD_CCP) += ccp\n+DIRS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO) += octeontx\n DIRS-$(CONFIG_RTE_LIBRTE_PMD_OPENSSL) += openssl\n DIRS-$(CONFIG_RTE_LIBRTE_PMD_CRYPTO_SCHEDULER) += scheduler\n DIRS-$(CONFIG_RTE_LIBRTE_PMD_SNOW3G) += snow3g\ndiff --git a/drivers/crypto/meson.build b/drivers/crypto/meson.build\nindex 6ed853b..b09fe1b 100644\n--- a/drivers/crypto/meson.build\n+++ b/drivers/crypto/meson.build\n@@ -2,7 +2,7 @@\n # Copyright(c) 2017 Intel Corporation\n \n drivers = ['ccp', 'dpaa_sec', 'dpaa2_sec', 'mvsam',\n-\t'null', 'openssl', 'qat', 'scheduler', 'virtio']\n+\t'null', 'octeontx', 'openssl', 'qat', 'scheduler', 'virtio']\n \n std_deps = ['cryptodev'] # cryptodev pulls in all other needed deps\n config_flag_fmt = 'RTE_LIBRTE_@0@_PMD'\ndiff --git a/drivers/crypto/octeontx/Makefile b/drivers/crypto/octeontx/Makefile\nnew file mode 100644\nindex 0000000..12fec75\n--- /dev/null\n+++ b/drivers/crypto/octeontx/Makefile\n@@ -0,0 +1,42 @@\n+# SPDX-License-Identifier: BSD-3-Clause\n+# Copyright(c) 2018 Cavium, Inc\n+#\n+\n+include $(RTE_SDK)/mk/rte.vars.mk\n+\n+# library name\n+LIB = librte_pmd_octeontx_crypto.a\n+\n+# library version\n+LIBABIVER := 1\n+\n+# build flags\n+CFLAGS += $(WERROR_FLAGS)\n+\n+LDLIBS += -lrte_eal -lrte_mbuf -lrte_mempool -lrte_ring\n+LDLIBS += -lrte_cryptodev\n+LDLIBS += -lrte_pci -lrte_bus_pci\n+\n+VPATH += $(RTE_SDK)/drivers/crypto/octeontx\n+\n+CFLAGS += -O3 -DCPT_MODEL=CRYPTO_OCTEONTX\n+CFLAGS += -I$(RTE_SDK)/drivers/common/cpt\n+\n+# PMD code\n+SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO) += otx_cryptodev.c\n+SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO) += otx_cryptodev_ops.c\n+\n+# export include files\n+SYMLINK-y-include +=\n+\n+# versioning export map\n+EXPORT_MAP := rte_pmd_octeontx_crypto_version.map\n+\n+# library dependencies\n+DEPDIRS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO) += lib/librte_eal\n+DEPDIRS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO) += lib/librte_cryptodev\n+DEPDIRS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO) += lib/librte_mempool\n+DEPDIRS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO) += lib/librte_mbuf\n+DEPDIRS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO) += lib/librte_malloc\n+\n+include $(RTE_SDK)/mk/rte.lib.mk\ndiff --git a/drivers/crypto/octeontx/meson.build b/drivers/crypto/octeontx/meson.build\nnew file mode 100644\nindex 0000000..6564090\n--- /dev/null\n+++ b/drivers/crypto/octeontx/meson.build\n@@ -0,0 +1,14 @@\n+# SPDX-License-Identifier: BSD-3-Clause\n+# Copyright(c) 2018 Cavium, Inc\n+if host_machine.system() != 'linux'\n+\tbuild = false\n+endif\n+\n+deps += ['bus_pci']\n+name = 'octeontx_crypto'\n+\n+sources = files('otx_cryptodev.c',\n+\t\t'otx_cryptodev_ops.c')\n+\n+cflags += '-DCPT_MODEL=CRYPTO_OCTEONTX'\n+includes += include_directories('../../common/cpt')\ndiff --git a/drivers/crypto/octeontx/otx_cryptodev.c b/drivers/crypto/octeontx/otx_cryptodev.c\nnew file mode 100644\nindex 0000000..43933dd\n--- /dev/null\n+++ b/drivers/crypto/octeontx/otx_cryptodev.c\n@@ -0,0 +1,130 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2018 Cavium, Inc\n+ */\n+\n+#include <rte_bus_pci.h>\n+#include <rte_common.h>\n+#include <rte_cryptodev.h>\n+#include <rte_cryptodev_pmd.h>\n+#include <rte_log.h>\n+#include <rte_pci.h>\n+\n+/* CPT common headers */\n+#include \"cpt_pmd_logs.h\"\n+\n+#include \"otx_cryptodev.h\"\n+#include \"otx_cryptodev_ops.h\"\n+\n+static int otx_cryptodev_logtype;\n+\n+static struct rte_pci_id pci_id_cpt_table[] = {\n+\t{\n+\t\tRTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, CPT_81XX_PCI_VF_DEVICE_ID),\n+\t},\n+\t/* sentinel */\n+\t{\n+\t\t.device_id = 0\n+\t},\n+};\n+\n+static void\n+otx_cpt_logtype_init(void)\n+{\n+\tcpt_logtype = otx_cryptodev_logtype;\n+}\n+\n+static int\n+otx_cpt_pci_probe(struct rte_pci_driver *pci_drv,\n+\t\t\tstruct rte_pci_device *pci_dev)\n+{\n+\tstruct rte_cryptodev *cryptodev;\n+\tchar name[RTE_CRYPTODEV_NAME_MAX_LEN];\n+\tint retval;\n+\n+\tif (pci_drv == NULL)\n+\t\treturn -ENODEV;\n+\n+\trte_pci_device_name(&pci_dev->addr, name, sizeof(name));\n+\n+\tcryptodev = rte_cryptodev_pmd_allocate(name, rte_socket_id());\n+\tif (cryptodev == NULL)\n+\t\treturn -ENOMEM;\n+\n+\tcryptodev->device = &pci_dev->device;\n+\tcryptodev->device->driver = &pci_drv->driver;\n+\tcryptodev->driver_id = otx_cryptodev_driver_id;\n+\n+\t/* init user callbacks */\n+\tTAILQ_INIT(&(cryptodev->link_intr_cbs));\n+\n+\t/* init logtype used in common */\n+\totx_cpt_logtype_init();\n+\n+\t/* Invoke PMD device initialization function */\n+\tretval = otx_cpt_dev_create(cryptodev);\n+\tif (retval == 0)\n+\t\treturn 0;\n+\n+\tCPT_LOG_ERR(\"[DRV %s]: Failed to create device \"\n+\t\t\t\"(vendor_id: 0x%x device_id: 0x%x\",\n+\t\t\tpci_drv->driver.name,\n+\t\t\t(unsigned int) pci_dev->id.vendor_id,\n+\t\t\t(unsigned int) pci_dev->id.device_id);\n+\n+\tcryptodev->attached = RTE_CRYPTODEV_DETACHED;\n+\n+\treturn -ENXIO;\n+}\n+\n+static int\n+otx_cpt_pci_remove(struct rte_pci_device *pci_dev)\n+{\n+\tstruct rte_cryptodev *cryptodev;\n+\tchar name[RTE_CRYPTODEV_NAME_MAX_LEN];\n+\n+\tif (pci_dev == NULL)\n+\t\treturn -EINVAL;\n+\n+\trte_pci_device_name(&pci_dev->addr, name, sizeof(name));\n+\n+\tcryptodev = rte_cryptodev_pmd_get_named_dev(name);\n+\tif (cryptodev == NULL)\n+\t\treturn -ENODEV;\n+\n+\tif (pci_dev->driver == NULL)\n+\t\treturn -ENODEV;\n+\n+\t/* free crypto device */\n+\trte_cryptodev_pmd_release_device(cryptodev);\n+\n+\tif (rte_eal_process_type() == RTE_PROC_PRIMARY)\n+\t\trte_free(cryptodev->data->dev_private);\n+\n+\tcryptodev->device = NULL;\n+\tcryptodev->device->driver = NULL;\n+\tcryptodev->data = NULL;\n+\n+\treturn 0;\n+}\n+\n+static struct rte_pci_driver otx_cryptodev_pmd = {\n+\t.id_table = pci_id_cpt_table,\n+\t.drv_flags = RTE_PCI_DRV_NEED_MAPPING,\n+\t.probe = otx_cpt_pci_probe,\n+\t.remove = otx_cpt_pci_remove,\n+};\n+\n+static struct cryptodev_driver otx_cryptodev_drv;\n+\n+RTE_PMD_REGISTER_PCI(CRYPTODEV_NAME_OCTEONTX_PMD, otx_cryptodev_pmd);\n+RTE_PMD_REGISTER_PCI_TABLE(CRYPTODEV_NAME_OCTEONTX_PMD, pci_id_cpt_table);\n+RTE_PMD_REGISTER_CRYPTO_DRIVER(otx_cryptodev_drv, otx_cryptodev_pmd.driver,\n+\t\totx_cryptodev_driver_id);\n+\n+RTE_INIT(otx_cpt_init_log)\n+{\n+\t/* Bus level logs */\n+\totx_cryptodev_logtype = rte_log_register(\"pmd.crypto.octeontx\");\n+\tif (otx_cryptodev_logtype >= 0)\n+\t\trte_log_set_level(otx_cryptodev_logtype, RTE_LOG_NOTICE);\n+}\ndiff --git a/drivers/crypto/octeontx/otx_cryptodev.h b/drivers/crypto/octeontx/otx_cryptodev.h\nnew file mode 100644\nindex 0000000..6c2871d\n--- /dev/null\n+++ b/drivers/crypto/octeontx/otx_cryptodev.h\n@@ -0,0 +1,20 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2018 Cavium, Inc\n+ */\n+\n+#ifndef _OTX_CRYPTODEV_H_\n+#define _OTX_CRYPTODEV_H_\n+\n+/* Cavium OCTEON TX crypto PMD device name */\n+#define CRYPTODEV_NAME_OCTEONTX_PMD\tcrypto_octeontx\n+\n+/* Device ID */\n+#define PCI_VENDOR_ID_CAVIUM\t\t0x177d\n+#define CPT_81XX_PCI_VF_DEVICE_ID\t0xa041\n+\n+/*\n+ * Crypto device driver ID\n+ */\n+uint8_t otx_cryptodev_driver_id;\n+\n+#endif /* _OTX_CRYPTODEV_H_ */\ndiff --git a/drivers/crypto/octeontx/otx_cryptodev_ops.c b/drivers/crypto/octeontx/otx_cryptodev_ops.c\nnew file mode 100644\nindex 0000000..1b5f108\n--- /dev/null\n+++ b/drivers/crypto/octeontx/otx_cryptodev_ops.c\n@@ -0,0 +1,15 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2018 Cavium, Inc\n+ */\n+\n+#include <rte_cryptodev.h>\n+\n+#include \"otx_cryptodev.h\"\n+#include \"otx_cryptodev_ops.h\"\n+\n+int\n+otx_cpt_dev_create(struct rte_cryptodev *c_dev)\n+{\n+\tRTE_SET_USED(c_dev);\n+\treturn 0;\n+}\ndiff --git a/drivers/crypto/octeontx/otx_cryptodev_ops.h b/drivers/crypto/octeontx/otx_cryptodev_ops.h\nnew file mode 100644\nindex 0000000..3f2d829\n--- /dev/null\n+++ b/drivers/crypto/octeontx/otx_cryptodev_ops.h\n@@ -0,0 +1,11 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2018 Cavium, Inc\n+ */\n+\n+#ifndef _OTX_CRYPTODEV_OPS_H_\n+#define _OTX_CRYPTODEV_OPS_H_\n+\n+int\n+otx_cpt_dev_create(struct rte_cryptodev *c_dev);\n+\n+#endif /* _OTX_CRYPTODEV_OPS_H_ */\ndiff --git a/drivers/crypto/octeontx/rte_pmd_octeontx_crypto_version.map b/drivers/crypto/octeontx/rte_pmd_octeontx_crypto_version.map\nnew file mode 100644\nindex 0000000..521e51f\n--- /dev/null\n+++ b/drivers/crypto/octeontx/rte_pmd_octeontx_crypto_version.map\n@@ -0,0 +1,4 @@\n+DPDK_18.11 {\n+\n+\tlocal: *;\n+};\ndiff --git a/mk/rte.app.mk b/mk/rte.app.mk\nindex 73d20c3..9661cdf 100644\n--- a/mk/rte.app.mk\n+++ b/mk/rte.app.mk\n@@ -217,6 +217,7 @@ _LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_ZUC) += -L$(LIBSSO_ZUC_PATH)/build -lsso\n _LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_ARMV8_CRYPTO) += -lrte_pmd_armv8\n _LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_ARMV8_CRYPTO) += -L$(ARMV8_CRYPTO_LIB_PATH) -larmv8_crypto\n _LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_MVSAM_CRYPTO) += -L$(LIBMUSDK_PATH)/lib -lrte_pmd_mvsam_crypto -lmusdk\n+_LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO) += -lrte_pmd_octeontx_crypto\n _LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_CRYPTO_SCHEDULER) += -lrte_pmd_crypto_scheduler\n ifeq ($(CONFIG_RTE_EAL_VFIO)$(CONFIG_RTE_LIBRTE_FSLMC_BUS),yy)\n _LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_DPAA2_SEC) += -lrte_pmd_dpaa2_sec\n", "prefixes": [ "v4", "01/23" ] }