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GET /api/patches/45440/?format=api
{ "id": 45440, "url": "http://patches.dpdk.org/api/patches/45440/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20180926180440.31726-8-shreyansh.jain@nxp.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20180926180440.31726-8-shreyansh.jain@nxp.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20180926180440.31726-8-shreyansh.jain@nxp.com", "date": "2018-09-26T18:04:32", "name": "[v2,07/15] bus/fslmc: support 32 enq and deq for LX2 platform", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "bf505fa309e4424ddf7025eec98f0d1d789bd5b9", "submitter": { "id": 497, "url": "http://patches.dpdk.org/api/people/497/?format=api", "name": "Shreyansh Jain", "email": "shreyansh.jain@nxp.com" }, "delegate": { "id": 1, "url": "http://patches.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20180926180440.31726-8-shreyansh.jain@nxp.com/mbox/", "series": [ { "id": 1525, "url": "http://patches.dpdk.org/api/series/1525/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=1525", "date": "2018-09-26T18:04:25", "name": "Upgrade DPAA2 FW and other feature/bug fixes", "version": 2, "mbox": "http://patches.dpdk.org/series/1525/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/45440/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/45440/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id A51541B4A1;\n\tWed, 26 Sep 2018 20:06:09 +0200 (CEST)", "from EUR03-VE1-obe.outbound.protection.outlook.com\n\t(mail-eopbgr50088.outbound.protection.outlook.com [40.107.5.88])\n\tby dpdk.org (Postfix) with ESMTP id 058791B48F\n\tfor <dev@dpdk.org>; Wed, 26 Sep 2018 20:06:04 +0200 (CEST)", "from Tophie.ap.freescale.net (14.142.187.166) by\n\tAM6PR04MB4679.eurprd04.prod.outlook.com (2603:10a6:20b:1c::18) with\n\tMicrosoft SMTP Server (version=TLS1_2,\n\tcipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id\n\t15.20.1164.22; Wed, 26 Sep 2018 18:06:01 +0000" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=nxp.com; s=selector1;\n\th=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n\tbh=O4Mjz3SEY2B0sR/4KHSeQm+tRBXWckOJrTjlGCa+YWk=;\n\tb=mRde2eJBEYSt+vV8ksK+r3ym0B+gmL73z+8cbikMR6JgUGPENlDqXmgSB69fa1RMSptGbWpDOI6W0B2bpsjH7dlTAhxqzHmPuAiZzYnMt2r0dqvvOePb+Dgzag4MaQHx+lM9SIc9ptMcic2Ly7/rPbhq6vebLqqFZAP8YJGtQk0=", "Authentication-Results": "spf=none (sender IP is )\n\tsmtp.mailfrom=shreyansh.jain@nxp.com; ", "From": "Shreyansh Jain <shreyansh.jain@nxp.com>", "To": "dev@dpdk.org,\n\tferruh.yigit@intel.com", "Cc": "thomas@monjalon.net,\n\tNipun Gupta <nipun.gupta@nxp.com>", "Date": "Wed, 26 Sep 2018 23:34:32 +0530", "Message-Id": "<20180926180440.31726-8-shreyansh.jain@nxp.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20180926180440.31726-1-shreyansh.jain@nxp.com>", "References": "<20180917103631.32304-1-shreyansh.jain@nxp.com>\n\t<20180926180440.31726-1-shreyansh.jain@nxp.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Originating-IP": "[14.142.187.166]", "X-ClientProxiedBy": "MA1PR0101CA0014.INDPRD01.PROD.OUTLOOK.COM\n\t(2603:1096:a00:21::24) To AM6PR04MB4679.eurprd04.prod.outlook.com\n\t(2603:10a6:20b:1c::18)", "X-MS-PublicTrafficType": "Email", "X-MS-Office365-Filtering-Correlation-Id": "04526ce8-4bf5-4aad-8b6e-08d623dab8d8", "X-MS-Office365-Filtering-HT": "Tenant", "X-Microsoft-Antispam": "BCL:0; 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", "X-MS-Exchange-SenderADCheck": "1", "X-Exchange-Antispam-Report-CFA-Test": "BCL:0; PCL:0;\n\tRULEID:(8211001083)(6040522)(2401047)(5005006)(8121501046)(93006095)(93001095)(10201501046)(3231355)(944501410)(52105095)(3002001)(6055026)(149066)(150057)(6041310)(20161123564045)(201703131423095)(201702281528075)(20161123555045)(201703061421075)(201703061406153)(20161123562045)(20161123558120)(20161123560045)(201708071742011)(7699051);\n\tSRVR:AM6PR04MB4679; BCL:0; PCL:0; RULEID:; SRVR:AM6PR04MB4679; ", "X-Forefront-PRVS": "08076ABC99", "X-Forefront-Antispam-Report": "SFV:NSPM;\n\tSFS:(10009020)(376002)(136003)(396003)(346002)(366004)(39860400002)(189003)(199004)(11346002)(50226002)(446003)(47776003)(44832011)(956004)(476003)(106356001)(486006)(2616005)(6512007)(66066001)(305945005)(7736002)(6486002)(105586002)(36756003)(86362001)(478600001)(8936002)(16526019)(81166006)(50466002)(186003)(26005)(25786009)(8676002)(55236004)(48376002)(81156014)(4326008)(3846002)(6116002)(1076002)(6666003)(52116002)(34290500001)(5009440100003)(2906002)(16586007)(51416003)(316002)(97736004)(6506007)(76176011)(5660300001)(386003)(68736007)(14444005)(53936002)(110426005);\n\tDIR:OUT; SFP:1101; SCL:1; SRVR:AM6PR04MB4679;\n\tH:Tophie.ap.freescale.net; FPR:; \n\tSPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; ", "Received-SPF": "None (protection.outlook.com: nxp.com does not designate\n\tpermitted sender hosts)", "X-Microsoft-Antispam-Message-Info": "xNLxi3vDhxL1Tt0BRZ8+HwKmc1WOMuYpL/R3Tu3rRO1jRPxQTAI5Nz7I7AK0RqxH7HJs7FgWUTBQMIlnz/D2cv+eO8B1d62P/Jvf71OVI/Kl6Tcw5V0ZAtT3IRzkwwtVCu8J3h4L3OCqyvsPODAd9/9rh+ER4nAEFvlKwpdmRuTiG2d/EiOd05rnHv6XxNvWmQQE3gHLMvYV1oIUNXJKQ1i95pKwQZf+qe5BIWRXMqJAuvV77Xwe7PuwlXJOiBQ/5Os2rF3TNLdLMk0E31BRpGY+HCdcAVGu86jnQDdPJNUvZ6e4LIgdqJyr1mc0OWqU00StDSTMEPjIEsZCCbFwcVzOEBOz7A/wxcy+geyKr4Y=", "SpamDiagnosticOutput": "1:99", "SpamDiagnosticMetadata": "NSPM", "X-OriginatorOrg": "nxp.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "26 Sep 2018 18:06:01.4139\n\t(UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "04526ce8-4bf5-4aad-8b6e-08d623dab8d8", "X-MS-Exchange-CrossTenant-FromEntityHeader": "Hosted", "X-MS-Exchange-CrossTenant-Id": "686ea1d3-bc2b-4c6f-a92c-d99c5c301635", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "AM6PR04MB4679", "Subject": "[dpdk-dev] [PATCH v2 07/15] bus/fslmc: support 32 enq and deq for\n\tLX2 platform", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Nipun Gupta <nipun.gupta@nxp.com>\n\nLX2 can support upto 32 frames in one hw pull request.\n\nSigned-off-by: Nipun Gupta <nipun.gupta@nxp.com>\n---\n drivers/bus/fslmc/portal/dpaa2_hw_dpio.c | 17 ++++++++++++++--\n drivers/bus/fslmc/portal/dpaa2_hw_dpio.h | 4 ++++\n drivers/bus/fslmc/portal/dpaa2_hw_pvt.h | 22 ++++++++++++++++-----\n drivers/bus/fslmc/rte_bus_fslmc_version.map | 2 ++\n drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c | 7 ++++---\n drivers/event/dpaa2/dpaa2_eventdev.c | 4 ++--\n drivers/net/dpaa2/dpaa2_rxtx.c | 8 ++++----\n 7 files changed, 48 insertions(+), 16 deletions(-)", "diff": "diff --git a/drivers/bus/fslmc/portal/dpaa2_hw_dpio.c b/drivers/bus/fslmc/portal/dpaa2_hw_dpio.c\nindex 76f80b951..ce0699842 100644\n--- a/drivers/bus/fslmc/portal/dpaa2_hw_dpio.c\n+++ b/drivers/bus/fslmc/portal/dpaa2_hw_dpio.c\n@@ -53,6 +53,11 @@ static uint32_t io_space_count;\n /* Variable to store DPAA2 platform type */\n uint32_t dpaa2_svr_family;\n \n+/* Variable to store DPAA2 DQRR size */\n+uint8_t dpaa2_dqrr_size;\n+/* Variable to store DPAA2 EQCR size */\n+uint8_t dpaa2_eqcr_size;\n+\n /*Stashing Macros default for LS208x*/\n static int dpaa2_core_cluster_base = 0x04;\n static int dpaa2_cluster_sz = 2;\n@@ -125,7 +130,7 @@ static void dpaa2_affine_dpio_intr_to_respective_core(int32_t dpio_id)\n \t\t cpu_mask, token);\n \tret = system(command);\n \tif (ret < 0)\n-\t\tDPAA2_BUS_WARN(\n+\t\tDPAA2_BUS_DEBUG(\n \t\t\t\"Failed to affine interrupts on respective core\");\n \telse\n \t\tDPAA2_BUS_DEBUG(\" %s command is executed\", command);\n@@ -409,6 +414,14 @@ dpaa2_create_dpio_device(int vdev_fd,\n \t\t\tDPAA2_BUS_DEBUG(\"LX2160 Platform Detected\");\n \t\t}\n \t\tdpaa2_svr_family = (mc_plat_info.svr & 0xffff0000);\n+\n+\t\tif (dpaa2_svr_family == SVR_LX2160A) {\n+\t\t\tdpaa2_dqrr_size = DPAA2_LX2_DQRR_RING_SIZE;\n+\t\t\tdpaa2_eqcr_size = DPAA2_LX2_EQCR_RING_SIZE;\n+\t\t} else {\n+\t\t\tdpaa2_dqrr_size = DPAA2_DQRR_RING_SIZE;\n+\t\t\tdpaa2_eqcr_size = DPAA2_EQCR_RING_SIZE;\n+\t\t}\n \t}\n \n \tif (dpaa2_svr_family == SVR_LX2160A)\n@@ -492,7 +505,7 @@ dpaa2_alloc_dq_storage(struct queue_storage_info_t *q_storage)\n \n \tfor (i = 0; i < NUM_DQS_PER_QUEUE; i++) {\n \t\tq_storage->dq_storage[i] = rte_malloc(NULL,\n-\t\t\tDPAA2_DQRR_RING_SIZE * sizeof(struct qbman_result),\n+\t\t\tdpaa2_dqrr_size * sizeof(struct qbman_result),\n \t\t\tRTE_CACHE_LINE_SIZE);\n \t\tif (!q_storage->dq_storage[i])\n \t\t\tgoto fail;\ndiff --git a/drivers/bus/fslmc/portal/dpaa2_hw_dpio.h b/drivers/bus/fslmc/portal/dpaa2_hw_dpio.h\nindex d593eea74..462501a2e 100644\n--- a/drivers/bus/fslmc/portal/dpaa2_hw_dpio.h\n+++ b/drivers/bus/fslmc/portal/dpaa2_hw_dpio.h\n@@ -30,6 +30,10 @@ RTE_DECLARE_PER_LCORE(struct dpaa2_io_portal_t, _dpaa2_io);\n \n /* Variable to store DPAA2 platform type */\n extern uint32_t dpaa2_svr_family;\n+/* Variable to store DPAA2 DQRR size */\n+extern uint8_t dpaa2_dqrr_size;\n+/* Variable to store DPAA2 EQCR size */\n+extern uint8_t dpaa2_eqcr_size;\n \n extern struct dpaa2_io_portal_t dpaa2_io_portal[RTE_MAX_LCORE];\n \ndiff --git a/drivers/bus/fslmc/portal/dpaa2_hw_pvt.h b/drivers/bus/fslmc/portal/dpaa2_hw_pvt.h\nindex f2eebe65d..ec8f42806 100644\n--- a/drivers/bus/fslmc/portal/dpaa2_hw_pvt.h\n+++ b/drivers/bus/fslmc/portal/dpaa2_hw_pvt.h\n@@ -1,7 +1,7 @@\n /* SPDX-License-Identifier: BSD-3-Clause\n *\n * Copyright (c) 2016 Freescale Semiconductor, Inc. All rights reserved.\n- * Copyright 2016 NXP\n+ * Copyright 2016-2018 NXP\n *\n */\n \n@@ -31,11 +31,23 @@\n #define VLAN_TAG_SIZE 4 /** < Vlan Header Length */\n #endif\n \n-#define MAX_TX_RING_SLOTS\t8\n-\t/** <Maximum number of slots available in TX ring*/\n+/* Maximum number of slots available in TX ring */\n+#define MAX_TX_RING_SLOTS\t\t\t32\n \n-#define DPAA2_DQRR_RING_SIZE\t16\n-\t/** <Maximum number of slots available in RX ring*/\n+/* Maximum number of slots available in RX ring */\n+#define DPAA2_EQCR_RING_SIZE\t\t8\n+/* Maximum number of slots available in RX ring on LX2 */\n+#define DPAA2_LX2_EQCR_RING_SIZE\t32\n+\n+/* Maximum number of slots available in RX ring */\n+#define DPAA2_DQRR_RING_SIZE\t\t16\n+/* Maximum number of slots available in RX ring on LX2 */\n+#define DPAA2_LX2_DQRR_RING_SIZE\t32\n+\n+/* EQCR shift to get EQCR size (2 >> 3) = 8 for LS2/LS2 */\n+#define DPAA2_EQCR_SHIFT\t\t3\n+/* EQCR shift to get EQCR size for LX2 (2 >> 5) = 32 for LX2 */\n+#define DPAA2_LX2_EQCR_SHIFT\t\t5\n \n #define DPAA2_SWP_CENA_REGION\t\t0\n #define DPAA2_SWP_CINH_REGION\t\t1\ndiff --git a/drivers/bus/fslmc/rte_bus_fslmc_version.map b/drivers/bus/fslmc/rte_bus_fslmc_version.map\nindex 8717373dd..dcc4e082e 100644\n--- a/drivers/bus/fslmc/rte_bus_fslmc_version.map\n+++ b/drivers/bus/fslmc/rte_bus_fslmc_version.map\n@@ -121,6 +121,8 @@ DPDK_18.05 {\n DPDK_18.11 {\n \tglobal:\n \n+\tdpaa2_dqrr_size;\n+\tdpaa2_eqcr_size;\n \tdpci_get_link_state;\n \tdpci_get_opr;\n \tdpci_get_peer_attributes;\ndiff --git a/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c b/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c\nindex e77039870..7765b8d80 100644\n--- a/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c\n+++ b/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c\n@@ -1173,7 +1173,8 @@ dpaa2_sec_enqueue_burst(void *qp, struct rte_crypto_op **ops,\n \tswp = DPAA2_PER_LCORE_PORTAL;\n \n \twhile (nb_ops) {\n-\t\tframes_to_send = (nb_ops >> 3) ? MAX_TX_RING_SLOTS : nb_ops;\n+\t\tframes_to_send = (nb_ops > dpaa2_eqcr_size) ?\n+\t\t\tdpaa2_eqcr_size : nb_ops;\n \n \t\tfor (loop = 0; loop < frames_to_send; loop++) {\n \t\t\t/*Clear the unused FD fields before sending*/\n@@ -1322,8 +1323,8 @@ dpaa2_sec_dequeue_burst(void *qp, struct rte_crypto_op **ops,\n \n \tqbman_pull_desc_clear(&pulldesc);\n \tqbman_pull_desc_set_numframes(&pulldesc,\n-\t\t\t\t (nb_ops > DPAA2_DQRR_RING_SIZE) ?\n-\t\t\t\t DPAA2_DQRR_RING_SIZE : nb_ops);\n+\t\t\t\t (nb_ops > dpaa2_dqrr_size) ?\n+\t\t\t\t dpaa2_dqrr_size : nb_ops);\n \tqbman_pull_desc_set_fq(&pulldesc, fqid);\n \tqbman_pull_desc_set_storage(&pulldesc, dq_storage,\n \t\t\t\t (dma_addr_t)DPAA2_VADDR_TO_IOVA(dq_storage),\ndiff --git a/drivers/event/dpaa2/dpaa2_eventdev.c b/drivers/event/dpaa2/dpaa2_eventdev.c\nindex ea1e5cc67..2831e141e 100644\n--- a/drivers/event/dpaa2/dpaa2_eventdev.c\n+++ b/drivers/event/dpaa2/dpaa2_eventdev.c\n@@ -80,8 +80,8 @@ dpaa2_eventdev_enqueue_burst(void *port, const struct rte_event ev[],\n \tswp = DPAA2_PER_LCORE_PORTAL;\n \n \twhile (nb_events) {\n-\t\tframes_to_send = (nb_events >> 3) ?\n-\t\t\tMAX_TX_RING_SLOTS : nb_events;\n+\t\tframes_to_send = (nb_events > dpaa2_eqcr_size) ?\n+\t\t\tdpaa2_eqcr_size : nb_events;\n \n \t\tfor (loop = 0; loop < frames_to_send; loop++) {\n \t\t\tconst struct rte_event *event = &ev[num_tx + loop];\ndiff --git a/drivers/net/dpaa2/dpaa2_rxtx.c b/drivers/net/dpaa2/dpaa2_rxtx.c\nindex ef109a621..89cfd2929 100644\n--- a/drivers/net/dpaa2/dpaa2_rxtx.c\n+++ b/drivers/net/dpaa2/dpaa2_rxtx.c\n@@ -1,7 +1,7 @@\n /* SPDX-License-Identifier: BSD-3-Clause\n *\n * Copyright (c) 2016 Freescale Semiconductor, Inc. All rights reserved.\n- * Copyright 2016 NXP\n+ * Copyright 2016-2018 NXP\n *\n */\n \n@@ -476,8 +476,7 @@ dpaa2_dev_prefetch_rx(void *queue, struct rte_mbuf **bufs, uint16_t nb_pkts)\n \t\t}\n \t}\n \tswp = DPAA2_PER_LCORE_ETHRX_PORTAL;\n-\tpull_size = (nb_pkts > DPAA2_DQRR_RING_SIZE) ?\n-\t\t\t\t\t DPAA2_DQRR_RING_SIZE : nb_pkts;\n+\tpull_size = (nb_pkts > dpaa2_dqrr_size) ? dpaa2_dqrr_size : nb_pkts;\n \tif (unlikely(!q_storage->active_dqs)) {\n \t\tq_storage->toggle = 0;\n \t\tdq_storage = q_storage->dq_storage[q_storage->toggle];\n@@ -699,7 +698,8 @@ dpaa2_dev_tx(void *queue, struct rte_mbuf **bufs, uint16_t nb_pkts)\n \t\t\t\tgoto skip_tx;\n \t\t}\n \n-\t\tframes_to_send = (nb_pkts >> 3) ? MAX_TX_RING_SLOTS : nb_pkts;\n+\t\tframes_to_send = (nb_pkts > dpaa2_eqcr_size) ?\n+\t\t\tdpaa2_eqcr_size : nb_pkts;\n \n \t\tfor (loop = 0; loop < frames_to_send; loop++) {\n \t\t\tif ((*bufs)->seqn) {\n", "prefixes": [ "v2", "07/15" ] }