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GET /api/patches/45297/?format=api
{ "id": 45297, "url": "http://patches.dpdk.org/api/patches/45297/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1537859109-25659-10-git-send-email-amo@semihalf.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1537859109-25659-10-git-send-email-amo@semihalf.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1537859109-25659-10-git-send-email-amo@semihalf.com", "date": "2018-09-25T07:05:05", "name": "[v3,09/13] net/mvpp2: align with MUSDK 18.09", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "93c665590838da30f14e109949147b083567eecb", "submitter": { "id": 1112, "url": "http://patches.dpdk.org/api/people/1112/?format=api", "name": "Andrzej Ostruszka", "email": "amo@semihalf.com" }, "delegate": { "id": 319, "url": "http://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1537859109-25659-10-git-send-email-amo@semihalf.com/mbox/", "series": [ { "id": 1482, "url": "http://patches.dpdk.org/api/series/1482/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=1482", "date": "2018-09-25T07:04:56", "name": "net/mvpp2: add new features", "version": 3, "mbox": "http://patches.dpdk.org/series/1482/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/45297/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/45297/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 6B1635699;\n\tTue, 25 Sep 2018 09:05:56 +0200 (CEST)", "from mail-lj1-f171.google.com (mail-lj1-f171.google.com\n\t[209.85.208.171]) by dpdk.org (Postfix) with ESMTP id AAFC74CE4\n\tfor <dev@dpdk.org>; Tue, 25 Sep 2018 09:05:22 +0200 (CEST)", "by mail-lj1-f171.google.com with SMTP id r83-v6so2612323ljr.7\n\tfor <dev@dpdk.org>; Tue, 25 Sep 2018 00:05:22 -0700 (PDT)", "from amok.semihalf.local (31-172-191-173.noc.fibertech.net.pl.\n\t[31.172.191.173]) by smtp.googlemail.com with ESMTPSA id\n\t24-v6sm238306ljb.76.2018.09.25.00.05.20\n\t(version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128);\n\tTue, 25 Sep 2018 00:05:21 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=semihalf-com.20150623.gappssmtp.com; s=20150623;\n\th=from:to:cc:subject:date:message-id:in-reply-to:references;\n\tbh=gtP5mRcSyeEthVynAK7KjKlotlJi+43kXiOBWPWXBaE=;\n\tb=DwErOcI5mZB8H8FwYce2VfvIQHcdNiokD0CPhzcCLJ71mvUNLtHSBm4gl7tjPwjgNZ\n\tdMY43YMoDFsGLJ8wnMXpmP+M+UaFcR+C3zke7ia0UU3d+gowIcvbr2DpUskSi9c04HjC\n\tanGO2tQyU9aCZ5hFQR2zELqsb1eJap4dMPq7PSS97QFtVcpO6+gBvFPxnV/706oeV/ls\n\tXBcYHc/ucnxNRZj/AX/M54A6GPQF/5rr0k44//XsOTe39WykRwRHiZm2CZjK6U/FScxZ\n\twTSuU6ROCQooYwmhH7mYrVc4OBic44HDLe25QMRFGX703AcJ2mZ6i7p5Uf2wI24m8u+R\n\ty7TA==", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to\n\t:references;\n\tbh=gtP5mRcSyeEthVynAK7KjKlotlJi+43kXiOBWPWXBaE=;\n\tb=WTM9pnuD0sl7hMdM4rzePaoqsX5RQUJyudusH2+2Fa/2hEZbypEVKDkSkkhtqVKE5/\n\t/Iqwk9UVEath6TCQgYQDS9nW+WiGIw7zhlD7wLQSycsKHhJ4UDyHdc16uDDgkc4iPoz8\n\thM5GRgHE9HZHLnWku88nXC2i9EpvLeF4gU/iB2HPI0N0wGZbCThEyCmLNubU0c28PYrI\n\tyJvU0eRjGugahcnIokQBRtxFmzTL1uwiR45cgBdVXX7ga5kjvLMSJtZI7+hsODZRTmD+\n\tHLrJ8qd/XxFG85Psqn9ynbFKzJosTZZCPOaUjvs7osevJuen9RSXWYeEA3aA6wrHWvde\n\tLz5w==", "X-Gm-Message-State": "ABuFfojlT1PAiJSwkMB8EMA34ja8ji/SWr5GmfgUImQ8T3pOHre5MrXS\n\t/uqjDsrmhX0+epcXYMf/CQ+/Q59VgcVrYA==", "X-Google-Smtp-Source": "ACcGV63GF+IGkqLEm3FrJmKSWoBn4brVeyLm8Ingn3IsVkW7se6l8ggOXhp9ngcnQ400rWRhQfaePw==", "X-Received": "by 2002:a2e:91d3:: with SMTP id\n\tu19-v6mr1403581ljg.64.1537859122062; \n\tTue, 25 Sep 2018 00:05:22 -0700 (PDT)", "From": "Andrzej Ostruszka <amo@semihalf.com>", "To": "dev@dpdk.org", "Cc": "mw@semihalf.com, nadavh@marvell.com, Tomasz Duszynski <tdu@semihalf.com>,\n\tNatalie Samsonov <nsamsono@marvell.com>,\n\tYuval Caduri <cyuval@marvell.com>", "Date": "Tue, 25 Sep 2018 09:05:05 +0200", "Message-Id": "<1537859109-25659-10-git-send-email-amo@semihalf.com>", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": "<1537859109-25659-1-git-send-email-amo@semihalf.com>", "References": "<1536068953-9352-1-git-send-email-tdu@semihalf.com>\n\t<1537859109-25659-1-git-send-email-amo@semihalf.com>", "Subject": "[dpdk-dev] [PATCH v3 09/13] net/mvpp2: align with MUSDK 18.09", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Tomasz Duszynski <tdu@semihalf.com>\n\nThis patch introduces necessary changes required by MUSDK 18.09 library.\n\n* As of MUSDK 18.09, pp2_cookie_t is no longer available. Now\n RX descriptor cookie is defined as plain u64 so existing cast\n is no longer valid.\n\n* MUSDK 18.09 increased number of available bpools (buffer hw pools) by\n introducing dma regions support. Update mvpp2 driver accordingly.\n\n* replace MV_NET_IP4_F_TOS with MV_NET_IP4_F_DSCP\n\n Before this patch, API allowed to configure a classification rule\n according to IPv4 TOS, which was not supported in classifier. This patch\n fixes this by using proper field.\n\n* use 48 bit address mask\n\n We cannot get pointers exceeding 48 bits thus using 48 bit\n mask for extracting higher IOVA address bits is enough.\n\nSigned-off-by: Natalie Samsonov <nsamsono@marvell.com>\nSigned-off-by: Yuval Caduri <cyuval@marvell.com>\nSigned-off-by: Tomasz Duszynski <tdu@semihalf.com>\nReviewed-by: Shlomi Gridish <sgridish@marvell.com>\nReviewed-by: Alan Winkowski <walan@marvell.com>\nReviewed-by: Liron Himi <lironh@marvell.com>\n---\n drivers/net/mvpp2/mrvl_ethdev.c | 10 ++++------\n drivers/net/mvpp2/mrvl_flow.c | 3 ++-\n drivers/net/mvpp2/mrvl_qos.c | 2 +-\n 3 files changed, 7 insertions(+), 8 deletions(-)", "diff": "diff --git a/drivers/net/mvpp2/mrvl_ethdev.c b/drivers/net/mvpp2/mrvl_ethdev.c\nindex 24bd0a5..26497ef 100644\n--- a/drivers/net/mvpp2/mrvl_ethdev.c\n+++ b/drivers/net/mvpp2/mrvl_ethdev.c\n@@ -54,9 +54,7 @@\n #define MRVL_ARP_LENGTH 28\n \n #define MRVL_COOKIE_ADDR_INVALID ~0ULL\n-\n-#define MRVL_COOKIE_HIGH_ADDR_SHIFT\t(sizeof(pp2_cookie_t) * 8)\n-#define MRVL_COOKIE_HIGH_ADDR_MASK\t(~0ULL << MRVL_COOKIE_HIGH_ADDR_SHIFT)\n+#define MRVL_COOKIE_HIGH_ADDR_MASK 0xffffff0000000000\n \n /** Port Rx offload capabilities */\n #define MRVL_RX_OFFLOADS (DEV_RX_OFFLOAD_VLAN_FILTER | \\\n@@ -1534,7 +1532,7 @@ mrvl_fill_bpool(struct mrvl_rxq *rxq, int num)\n \n \t\tentries[i].buff.addr =\n \t\t\trte_mbuf_data_iova_default(mbufs[i]);\n-\t\tentries[i].buff.cookie = (pp2_cookie_t)(uint64_t)mbufs[i];\n+\t\tentries[i].buff.cookie = (uint64_t)mbufs[i];\n \t\tentries[i].bpool = bpool;\n \t}\n \n@@ -2170,7 +2168,7 @@ mrvl_rx_pkt_burst(void *rxq, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)\n \t\tif (unlikely(status != PP2_DESC_ERR_OK)) {\n \t\t\tstruct pp2_buff_inf binf = {\n \t\t\t\t.addr = rte_mbuf_data_iova_default(mbuf),\n-\t\t\t\t.cookie = (pp2_cookie_t)(uint64_t)mbuf,\n+\t\t\t\t.cookie = (uint64_t)mbuf,\n \t\t\t};\n \n \t\t\tpp2_bpool_put_buff(hif, bpool, &binf);\n@@ -2431,7 +2429,7 @@ mrvl_tx_pkt_burst(void *txq, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)\n \t\t\trte_mbuf_prefetch_part2(pref_pkt_hdr);\n \t\t}\n \n-\t\tsq->ent[sq->head].buff.cookie = (pp2_cookie_t)(uint64_t)mbuf;\n+\t\tsq->ent[sq->head].buff.cookie = (uint64_t)mbuf;\n \t\tsq->ent[sq->head].buff.addr =\n \t\t\trte_mbuf_data_iova_default(mbuf);\n \t\tsq->ent[sq->head].bpool =\ndiff --git a/drivers/net/mvpp2/mrvl_flow.c b/drivers/net/mvpp2/mrvl_flow.c\nindex 065b1aa..ffd1dab 100644\n--- a/drivers/net/mvpp2/mrvl_flow.c\n+++ b/drivers/net/mvpp2/mrvl_flow.c\n@@ -2437,7 +2437,8 @@ mrvl_create_cls_table(struct rte_eth_dev *dev, struct rte_flow *first_flow)\n \n \tif (first_flow->pattern & F_IP4_TOS) {\n \t\tkey->proto_field[key->num_fields].proto = MV_NET_PROTO_IP4;\n-\t\tkey->proto_field[key->num_fields].field.ipv4 = MV_NET_IP4_F_TOS;\n+\t\tkey->proto_field[key->num_fields].field.ipv4 =\n+\t\t\t\t\t\t\tMV_NET_IP4_F_DSCP;\n \t\tkey->key_size += 1;\n \t\tkey->num_fields += 1;\n \t}\ndiff --git a/drivers/net/mvpp2/mrvl_qos.c b/drivers/net/mvpp2/mrvl_qos.c\nindex 5d80c3e..7fd9703 100644\n--- a/drivers/net/mvpp2/mrvl_qos.c\n+++ b/drivers/net/mvpp2/mrvl_qos.c\n@@ -654,7 +654,7 @@ setup_tc(struct pp2_ppio_tc_params *param, uint8_t inqs,\n \tstruct pp2_ppio_inq_params *inq_params;\n \n \tparam->pkt_offset = MRVL_PKT_OFFS;\n-\tparam->pools[0] = bpool;\n+\tparam->pools[0][0] = bpool;\n \tparam->default_color = color;\n \n \tinq_params = rte_zmalloc_socket(\"inq_params\",\n", "prefixes": [ "v3", "09/13" ] }